1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 ARM Ltd.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <linux/kvm_host.h>
8 #include <linux/random.h>
9 #include <linux/memblock.h>
10 #include <asm/alternative.h>
11 #include <asm/debug-monitors.h>
12 #include <asm/insn.h>
13 #include <asm/kvm_mmu.h>
14 #include <asm/memory.h>
15 #include <asm/patching.h>
16
17 /*
18 * The LSB of the HYP VA tag
19 */
20 static u8 tag_lsb;
21 /*
22 * The HYP VA tag value with the region bit
23 */
24 static u64 tag_val;
25 static u64 va_mask;
26
27 /*
28 * Compute HYP VA by using the same computation as kern_hyp_va().
29 */
__early_kern_hyp_va(u64 addr)30 static u64 __early_kern_hyp_va(u64 addr)
31 {
32 addr &= va_mask;
33 addr |= tag_val << tag_lsb;
34 return addr;
35 }
36
37 /*
38 * Store a hyp VA <-> PA offset into a EL2-owned variable.
39 */
init_hyp_physvirt_offset(void)40 static void init_hyp_physvirt_offset(void)
41 {
42 u64 kern_va, hyp_va;
43
44 /* Compute the offset from the hyp VA and PA of a random symbol. */
45 kern_va = (u64)lm_alias(__hyp_text_start);
46 hyp_va = __early_kern_hyp_va(kern_va);
47 hyp_physvirt_offset = (s64)__pa(kern_va) - (s64)hyp_va;
48 }
49
50 /*
51 * We want to generate a hyp VA with the following format (with V ==
52 * vabits_actual):
53 *
54 * 63 ... V | V-1 | V-2 .. tag_lsb | tag_lsb - 1 .. 0
55 * ---------------------------------------------------------
56 * | 0000000 | hyp_va_msb | random tag | kern linear VA |
57 * |--------- tag_val -----------|----- va_mask ---|
58 *
59 * which does not conflict with the idmap regions.
60 */
kvm_compute_layout(void)61 __init void kvm_compute_layout(void)
62 {
63 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
64 u64 hyp_va_msb;
65
66 /* Where is my RAM region? */
67 hyp_va_msb = idmap_addr & BIT(vabits_actual - 1);
68 hyp_va_msb ^= BIT(vabits_actual - 1);
69
70 tag_lsb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
71 (u64)(high_memory - 1));
72
73 va_mask = GENMASK_ULL(tag_lsb - 1, 0);
74 tag_val = hyp_va_msb;
75
76 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && tag_lsb != (vabits_actual - 1)) {
77 /* We have some free bits to insert a random tag. */
78 tag_val |= get_random_long() & GENMASK_ULL(vabits_actual - 2, tag_lsb);
79 }
80 tag_val >>= tag_lsb;
81
82 init_hyp_physvirt_offset();
83 }
84
85 /*
86 * The .hyp.reloc ELF section contains a list of kimg positions that
87 * contains kimg VAs but will be accessed only in hyp execution context.
88 * Convert them to hyp VAs. See gen-hyprel.c for more details.
89 */
kvm_apply_hyp_relocations(void)90 __init void kvm_apply_hyp_relocations(void)
91 {
92 int32_t *rel;
93 int32_t *begin = (int32_t *)__hyp_reloc_begin;
94 int32_t *end = (int32_t *)__hyp_reloc_end;
95
96 for (rel = begin; rel < end; ++rel) {
97 uintptr_t *ptr, kimg_va;
98
99 /*
100 * Each entry contains a 32-bit relative offset from itself
101 * to a kimg VA position.
102 */
103 ptr = (uintptr_t *)lm_alias((char *)rel + *rel);
104
105 /* Read the kimg VA value at the relocation address. */
106 kimg_va = *ptr;
107
108 /* Convert to hyp VA and store back to the relocation address. */
109 *ptr = __early_kern_hyp_va((uintptr_t)lm_alias(kimg_va));
110 }
111 }
112
kvm_apply_hyp_module_relocations(void * mod_start,void * hyp_va,kvm_nvhe_reloc_t * begin,kvm_nvhe_reloc_t * end)113 void kvm_apply_hyp_module_relocations(void *mod_start, void *hyp_va,
114 kvm_nvhe_reloc_t *begin,
115 kvm_nvhe_reloc_t *end)
116 {
117 kvm_nvhe_reloc_t *rel;
118
119 for (rel = begin; rel < end; ++rel) {
120 u32 **ptr, *va;
121
122 /*
123 * Each entry contains a 32-bit relative offset from itself
124 * to a VA position in the module area.
125 */
126 ptr = (u32 **)((char *)rel + *rel);
127
128 /* Read the module VA value at the relocation address. */
129 va = *ptr;
130
131 /* Convert the module VA of the reloc to a hyp VA */
132 WARN_ON(aarch64_addr_write(ptr, (u64)(((void *)va - mod_start) + hyp_va)));
133 }
134 }
135
compute_instruction(int n,u32 rd,u32 rn)136 static u32 compute_instruction(int n, u32 rd, u32 rn)
137 {
138 u32 insn = AARCH64_BREAK_FAULT;
139
140 switch (n) {
141 case 0:
142 insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
143 AARCH64_INSN_VARIANT_64BIT,
144 rn, rd, va_mask);
145 break;
146
147 case 1:
148 /* ROR is a variant of EXTR with Rm = Rn */
149 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
150 rn, rn, rd,
151 tag_lsb);
152 break;
153
154 case 2:
155 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
156 tag_val & GENMASK(11, 0),
157 AARCH64_INSN_VARIANT_64BIT,
158 AARCH64_INSN_ADSB_ADD);
159 break;
160
161 case 3:
162 insn = aarch64_insn_gen_add_sub_imm(rd, rn,
163 tag_val & GENMASK(23, 12),
164 AARCH64_INSN_VARIANT_64BIT,
165 AARCH64_INSN_ADSB_ADD);
166 break;
167
168 case 4:
169 /* ROR is a variant of EXTR with Rm = Rn */
170 insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
171 rn, rn, rd, 64 - tag_lsb);
172 break;
173 }
174
175 return insn;
176 }
177
kvm_update_va_mask(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)178 void __init kvm_update_va_mask(struct alt_instr *alt,
179 __le32 *origptr, __le32 *updptr, int nr_inst)
180 {
181 int i;
182
183 BUG_ON(nr_inst != 5);
184
185 for (i = 0; i < nr_inst; i++) {
186 u32 rd, rn, insn, oinsn;
187
188 /*
189 * VHE doesn't need any address translation, let's NOP
190 * everything.
191 *
192 * Alternatively, if the tag is zero (because the layout
193 * dictates it and we don't have any spare bits in the
194 * address), NOP everything after masking the kernel VA.
195 */
196 if (has_vhe() || (!tag_val && i > 0)) {
197 updptr[i] = cpu_to_le32(aarch64_insn_gen_nop());
198 continue;
199 }
200
201 oinsn = le32_to_cpu(origptr[i]);
202 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
203 rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
204
205 insn = compute_instruction(i, rd, rn);
206 BUG_ON(insn == AARCH64_BREAK_FAULT);
207
208 updptr[i] = cpu_to_le32(insn);
209 }
210 }
211
kvm_patch_vector_branch(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)212 void kvm_patch_vector_branch(struct alt_instr *alt,
213 __le32 *origptr, __le32 *updptr, int nr_inst)
214 {
215 u64 addr;
216 u32 insn;
217
218 BUG_ON(nr_inst != 4);
219
220 if (!cpus_have_const_cap(ARM64_SPECTRE_V3A) || WARN_ON_ONCE(has_vhe()))
221 return;
222
223 /*
224 * Compute HYP VA by using the same computation as kern_hyp_va()
225 */
226 addr = __early_kern_hyp_va((u64)kvm_ksym_ref(__kvm_hyp_vector));
227
228 /* Use PC[10:7] to branch to the same vector in KVM */
229 addr |= ((u64)origptr & GENMASK_ULL(10, 7));
230
231 /*
232 * Branch over the preamble in order to avoid the initial store on
233 * the stack (which we already perform in the hardening vectors).
234 */
235 addr += KVM_VECTOR_PREAMBLE;
236
237 /* movz x0, #(addr & 0xffff) */
238 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
239 (u16)addr,
240 0,
241 AARCH64_INSN_VARIANT_64BIT,
242 AARCH64_INSN_MOVEWIDE_ZERO);
243 *updptr++ = cpu_to_le32(insn);
244
245 /* movk x0, #((addr >> 16) & 0xffff), lsl #16 */
246 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
247 (u16)(addr >> 16),
248 16,
249 AARCH64_INSN_VARIANT_64BIT,
250 AARCH64_INSN_MOVEWIDE_KEEP);
251 *updptr++ = cpu_to_le32(insn);
252
253 /* movk x0, #((addr >> 32) & 0xffff), lsl #32 */
254 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_0,
255 (u16)(addr >> 32),
256 32,
257 AARCH64_INSN_VARIANT_64BIT,
258 AARCH64_INSN_MOVEWIDE_KEEP);
259 *updptr++ = cpu_to_le32(insn);
260
261 /* br x0 */
262 insn = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_0,
263 AARCH64_INSN_BRANCH_NOLINK);
264 *updptr++ = cpu_to_le32(insn);
265 }
266
generate_mov_q(u64 val,__le32 * origptr,__le32 * updptr,int nr_inst)267 static void generate_mov_q(u64 val, __le32 *origptr, __le32 *updptr, int nr_inst)
268 {
269 u32 insn, oinsn, rd;
270
271 BUG_ON(nr_inst != 4);
272
273 /* Compute target register */
274 oinsn = le32_to_cpu(*origptr);
275 rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
276
277 /* movz rd, #(val & 0xffff) */
278 insn = aarch64_insn_gen_movewide(rd,
279 (u16)val,
280 0,
281 AARCH64_INSN_VARIANT_64BIT,
282 AARCH64_INSN_MOVEWIDE_ZERO);
283 *updptr++ = cpu_to_le32(insn);
284
285 /* movk rd, #((val >> 16) & 0xffff), lsl #16 */
286 insn = aarch64_insn_gen_movewide(rd,
287 (u16)(val >> 16),
288 16,
289 AARCH64_INSN_VARIANT_64BIT,
290 AARCH64_INSN_MOVEWIDE_KEEP);
291 *updptr++ = cpu_to_le32(insn);
292
293 /* movk rd, #((val >> 32) & 0xffff), lsl #32 */
294 insn = aarch64_insn_gen_movewide(rd,
295 (u16)(val >> 32),
296 32,
297 AARCH64_INSN_VARIANT_64BIT,
298 AARCH64_INSN_MOVEWIDE_KEEP);
299 *updptr++ = cpu_to_le32(insn);
300
301 /* movk rd, #((val >> 48) & 0xffff), lsl #48 */
302 insn = aarch64_insn_gen_movewide(rd,
303 (u16)(val >> 48),
304 48,
305 AARCH64_INSN_VARIANT_64BIT,
306 AARCH64_INSN_MOVEWIDE_KEEP);
307 *updptr++ = cpu_to_le32(insn);
308 }
309
kvm_get_kimage_voffset(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)310 void kvm_get_kimage_voffset(struct alt_instr *alt,
311 __le32 *origptr, __le32 *updptr, int nr_inst)
312 {
313 generate_mov_q(kimage_voffset, origptr, updptr, nr_inst);
314 }
315
kvm_compute_final_ctr_el0(struct alt_instr * alt,__le32 * origptr,__le32 * updptr,int nr_inst)316 void kvm_compute_final_ctr_el0(struct alt_instr *alt,
317 __le32 *origptr, __le32 *updptr, int nr_inst)
318 {
319 generate_mov_q(read_sanitised_ftr_reg(SYS_CTR_EL0),
320 origptr, updptr, nr_inst);
321 }
322