1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/percpu.h>
20 #include <linux/psci.h>
21 #include <asm/arch_gicv3.h>
22 #include <asm/barrier.h>
23 #include <asm/cpufeature.h>
24 #include <asm/cputype.h>
25 #include <asm/daifflags.h>
26 #include <asm/fpsimd.h>
27 #include <asm/kvm.h>
28 #include <asm/kvm_asm.h>
29
30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
31
32 #define KVM_HALT_POLL_NS_DEFAULT 500000
33
34 #include <kvm/arm_vgic.h>
35 #include <kvm/arm_arch_timer.h>
36 #include <kvm/arm_pmu.h>
37
38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
39
40 #define KVM_VCPU_MAX_FEATURES 7
41
42 #define KVM_REQ_SLEEP \
43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
48 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
49 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
50
51 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
52 KVM_DIRTY_LOG_INITIALLY_SET)
53
54 #define KVM_HAVE_MMU_RWLOCK
55
56 /*
57 * Mode of operation configurable with kvm-arm.mode early param.
58 * See Documentation/admin-guide/kernel-parameters.txt for more information.
59 */
60 enum kvm_mode {
61 KVM_MODE_DEFAULT,
62 KVM_MODE_PROTECTED,
63 KVM_MODE_NONE,
64 };
65 enum kvm_mode kvm_get_mode(void);
66
67 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
68
69 extern unsigned int kvm_sve_max_vl;
70 extern unsigned int kvm_host_sve_max_vl;
71 int kvm_arm_init_sve(void);
72
73 u32 __attribute_const__ kvm_target_cpu(void);
74 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
75 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
76
77 struct kvm_hyp_memcache {
78 phys_addr_t head;
79 unsigned long nr_pages;
80 };
81
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))82 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
83 phys_addr_t *p,
84 phys_addr_t (*to_pa)(void *virt))
85 {
86 *p = mc->head;
87 mc->head = to_pa(p);
88 mc->nr_pages++;
89 }
90
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))91 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
92 void *(*to_va)(phys_addr_t phys))
93 {
94 phys_addr_t *p = to_va(mc->head);
95
96 if (!mc->nr_pages)
97 return NULL;
98
99 mc->head = *p;
100 mc->nr_pages--;
101
102 return p;
103 }
104
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)105 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
106 unsigned long min_pages,
107 void *(*alloc_fn)(void *arg),
108 phys_addr_t (*to_pa)(void *virt),
109 void *arg)
110 {
111 while (mc->nr_pages < min_pages) {
112 phys_addr_t *p = alloc_fn(arg);
113
114 if (!p)
115 return -ENOMEM;
116 push_hyp_memcache(mc, p, to_pa);
117 }
118
119 return 0;
120 }
121
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)122 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
123 void (*free_fn)(void *virt, void *arg),
124 void *(*to_va)(phys_addr_t phys),
125 void *arg)
126 {
127 while (mc->nr_pages)
128 free_fn(pop_hyp_memcache(mc, to_va), arg);
129 }
130
131 void free_hyp_memcache(struct kvm_hyp_memcache *mc, struct kvm *kvm);
132 void free_hyp_stage2_memcache(struct kvm_hyp_memcache *mc, struct kvm *kvm);
133 int topup_hyp_memcache(struct kvm_vcpu *vcpu);
134
135 struct kvm_vmid {
136 atomic64_t id;
137 };
138
139 struct kvm_s2_mmu {
140 struct kvm_vmid vmid;
141
142 /*
143 * stage2 entry level table
144 *
145 * Two kvm_s2_mmu structures in the same VM can point to the same
146 * pgd here. This happens when running a guest using a
147 * translation regime that isn't affected by its own stage-2
148 * translation, such as a non-VHE hypervisor running at vEL2, or
149 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
150 * canonical stage-2 page tables.
151 */
152 phys_addr_t pgd_phys;
153 struct kvm_pgtable *pgt;
154
155 /* The last vcpu id that ran on each physical CPU */
156 int __percpu *last_vcpu_ran;
157
158 struct kvm_arch *arch;
159 };
160
161 struct kvm_arch_memory_slot {
162 };
163
164 /**
165 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
166 *
167 * @std_bmap: Bitmap of standard secure service calls
168 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
169 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
170 */
171 struct kvm_smccc_features {
172 unsigned long std_bmap;
173 unsigned long std_hyp_bmap;
174 unsigned long vendor_hyp_bmap;
175 };
176
177 struct kvm_pinned_page {
178 struct rb_node node;
179 struct page *page;
180 u64 ipa;
181 };
182
183 typedef unsigned int pkvm_handle_t;
184
185 struct kvm_protected_vm {
186 pkvm_handle_t handle;
187 struct kvm_hyp_memcache teardown_mc;
188 struct kvm_hyp_memcache teardown_stage2_mc;
189 struct rb_root pinned_pages;
190 gpa_t pvmfw_load_addr;
191 bool enabled;
192 };
193
194 struct kvm_arch {
195 struct kvm_s2_mmu mmu;
196
197 /* VTCR_EL2 value for this VM */
198 u64 vtcr;
199
200 /* The maximum number of vCPUs depends on the used GIC model */
201 int max_vcpus;
202
203 /* Interrupt controller */
204 struct vgic_dist vgic;
205
206 /* Mandated version of PSCI */
207 u32 psci_version;
208
209 #ifndef __GENKSYMS__
210 /* Protects VM-scoped configuration data */
211 struct mutex config_lock;
212 #endif
213
214 /*
215 * If we encounter a data abort without valid instruction syndrome
216 * information, report this to user space. User space can (and
217 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
218 * supported.
219 */
220 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
221 /* Memory Tagging Extension enabled for the guest */
222 #define KVM_ARCH_FLAG_MTE_ENABLED 1
223 /* At least one vCPU has ran in the VM */
224 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
225 /*
226 * The following two bits are used to indicate the guest's EL1
227 * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT
228 * bit is valid only when KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED is set.
229 * Otherwise, the guest's EL1 register width has not yet been
230 * determined yet.
231 */
232 #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3
233 #define KVM_ARCH_FLAG_EL1_32BIT 4
234 /* PSCI SYSTEM_SUSPEND enabled for the guest */
235 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
236 /* Guest has bought into the MMIO guard extension */
237 #define KVM_ARCH_FLAG_MMIO_GUARD 6
238 unsigned long flags;
239
240 /*
241 * VM-wide PMU filter, implemented as a bitmap and big enough for
242 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
243 */
244 unsigned long *pmu_filter;
245 struct arm_pmu *arm_pmu;
246
247 cpumask_var_t supported_cpus;
248
249 u8 pfr0_csv2;
250 u8 pfr0_csv3;
251
252 /* Hypercall features firmware registers' descriptor */
253 struct kvm_smccc_features smccc_feat;
254
255 /*
256 * For an untrusted host VM, 'pkvm.handle' is used to lookup
257 * the associated pKVM instance in the hypervisor.
258 */
259 struct kvm_protected_vm pkvm;
260 };
261
262 struct kvm_vcpu_fault_info {
263 u32 esr_el2; /* Hyp Syndrom Register */
264 u64 far_el2; /* Hyp Fault Address Register */
265 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
266 u64 disr_el1; /* Deferred [SError] Status Register */
267 };
268
269 enum vcpu_sysreg {
270 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
271 MPIDR_EL1, /* MultiProcessor Affinity Register */
272 CSSELR_EL1, /* Cache Size Selection Register */
273 SCTLR_EL1, /* System Control Register */
274 ACTLR_EL1, /* Auxiliary Control Register */
275 CPACR_EL1, /* Coprocessor Access Control */
276 ZCR_EL1, /* SVE Control */
277 TTBR0_EL1, /* Translation Table Base Register 0 */
278 TTBR1_EL1, /* Translation Table Base Register 1 */
279 TCR_EL1, /* Translation Control Register */
280 ESR_EL1, /* Exception Syndrome Register */
281 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
282 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
283 FAR_EL1, /* Fault Address Register */
284 MAIR_EL1, /* Memory Attribute Indirection Register */
285 VBAR_EL1, /* Vector Base Address Register */
286 CONTEXTIDR_EL1, /* Context ID Register */
287 TPIDR_EL0, /* Thread ID, User R/W */
288 TPIDRRO_EL0, /* Thread ID, User R/O */
289 TPIDR_EL1, /* Thread ID, Privileged */
290 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
291 CNTKCTL_EL1, /* Timer Control Register (EL1) */
292 PAR_EL1, /* Physical Address Register */
293 MDSCR_EL1, /* Monitor Debug System Control Register */
294 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
295 OSLSR_EL1, /* OS Lock Status Register */
296 DISR_EL1, /* Deferred Interrupt Status Register */
297
298 /* Performance Monitors Registers */
299 PMCR_EL0, /* Control Register */
300 PMSELR_EL0, /* Event Counter Selection Register */
301 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
302 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
303 PMCCNTR_EL0, /* Cycle Counter Register */
304 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
305 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
306 PMCCFILTR_EL0, /* Cycle Count Filter Register */
307 PMCNTENSET_EL0, /* Count Enable Set Register */
308 PMINTENSET_EL1, /* Interrupt Enable Set Register */
309 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
310 PMUSERENR_EL0, /* User Enable Register */
311
312 /* Pointer Authentication Registers in a strict increasing order. */
313 APIAKEYLO_EL1,
314 APIAKEYHI_EL1,
315 APIBKEYLO_EL1,
316 APIBKEYHI_EL1,
317 APDAKEYLO_EL1,
318 APDAKEYHI_EL1,
319 APDBKEYLO_EL1,
320 APDBKEYHI_EL1,
321 APGAKEYLO_EL1,
322 APGAKEYHI_EL1,
323
324 ELR_EL1,
325 SP_EL1,
326 SPSR_EL1,
327
328 CNTVOFF_EL2,
329 CNTV_CVAL_EL0,
330 CNTV_CTL_EL0,
331 CNTP_CVAL_EL0,
332 CNTP_CTL_EL0,
333
334 /* Memory Tagging Extension registers */
335 RGSR_EL1, /* Random Allocation Tag Seed Register */
336 GCR_EL1, /* Tag Control Register */
337 TFSR_EL1, /* Tag Fault Status Register (EL1) */
338 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
339
340 /* 32bit specific registers. Keep them at the end of the range */
341 DACR32_EL2, /* Domain Access Control Register */
342 IFSR32_EL2, /* Instruction Fault Status Register */
343 FPEXC32_EL2, /* Floating-Point Exception Control Register */
344 DBGVCR32_EL2, /* Debug Vector Catch Register */
345
346 NR_SYS_REGS /* Nothing after this line! */
347 };
348
349 struct kvm_cpu_context {
350 struct user_pt_regs regs; /* sp = sp_el0 */
351
352 u64 spsr_abt;
353 u64 spsr_und;
354 u64 spsr_irq;
355 u64 spsr_fiq;
356
357 struct user_fpsimd_state fp_regs;
358
359 u64 sys_regs[NR_SYS_REGS];
360
361 #ifdef __GENKSYMS__
362 struct kvm_vcpu *__hyp_running_vcpu;
363 #else
364 void *__hyp_running_vcpu;
365 #endif
366 };
367
368 struct kvm_host_data {
369 struct kvm_cpu_context host_ctxt;
370 };
371
372 struct kvm_host_psci_config {
373 /* PSCI version used by host. */
374 u32 version;
375 u32 smccc_version;
376
377 /* Function IDs used by host if version is v0.1. */
378 struct psci_0_1_function_ids function_ids_0_1;
379
380 bool psci_0_1_cpu_suspend_implemented;
381 bool psci_0_1_cpu_on_implemented;
382 bool psci_0_1_cpu_off_implemented;
383 bool psci_0_1_migrate_implemented;
384 };
385
386 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
387 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
388
389 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
390 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
391
392 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
393 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
394
395 enum pkvm_iommu_pm_event {
396 PKVM_IOMMU_PM_SUSPEND,
397 PKVM_IOMMU_PM_RESUME,
398 };
399
400 struct pkvm_iommu_ops;
401
402 struct pkvm_iommu_driver {
403 const struct pkvm_iommu_ops *ops;
404 struct list_head list;
405 atomic_t state;
406 };
407
408 int pkvm_iommu_driver_init(u64 drv, void *data, size_t size);
409 int pkvm_iommu_register(struct device *dev, u64 drv, phys_addr_t pa,
410 size_t size, struct device *parent, u8 flags);
411 int pkvm_iommu_suspend(struct device *dev);
412 int pkvm_iommu_resume(struct device *dev);
413
414 /*
415 * Reject future calls to pkvm_iommu_driver_init() and pkvm_iommu_register()
416 * and report errors if found. Incase of errors pKVM can take proper actions
417 * as erasing pvmfw.
418 */
419 int pkvm_iommu_finalize(int err);
420
421 bool pkvm_iommu_finalized(void);
422
423 struct vcpu_reset_state {
424 unsigned long pc;
425 unsigned long r0;
426 bool be;
427 bool reset;
428 };
429
430 struct kvm_vcpu_arch {
431 struct kvm_cpu_context ctxt;
432
433 /* Guest floating point state */
434 void *sve_state;
435 unsigned int sve_max_vl;
436 u64 svcr;
437
438 /* Stage 2 paging state used by the hardware on next switch */
439 struct kvm_s2_mmu *hw_mmu;
440
441 /* Values of trap registers for the guest. */
442 u64 hcr_el2;
443 u64 mdcr_el2;
444 u64 cptr_el2;
445
446 /* Values of trap registers for the host before guest entry. */
447 u64 mdcr_el2_host;
448
449 /* Exception Information */
450 struct kvm_vcpu_fault_info fault;
451
452 /* Ownership of the FP regs */
453 enum {
454 FP_STATE_FREE,
455 FP_STATE_HOST_OWNED,
456 FP_STATE_GUEST_OWNED,
457 } fp_state;
458
459 /* Configuration flags, set once and for all before the vcpu can run */
460 u8 cflags;
461
462 /* Input flags to the hypervisor code, potentially cleared after use */
463 u8 iflags;
464
465 /* State flags for kernel bookkeeping, unused by the hypervisor code */
466 u8 sflags;
467
468 /*
469 * Don't run the guest (internal implementation need).
470 *
471 * Contrary to the flags above, this is set/cleared outside of
472 * a vcpu context, and thus cannot be mixed with the flags
473 * themselves (or the flag accesses need to be made atomic).
474 */
475 bool pause;
476
477 /*
478 * We maintain more than a single set of debug registers to support
479 * debugging the guest from the host and to maintain separate host and
480 * guest state during world switches. vcpu_debug_state are the debug
481 * registers of the vcpu as the guest sees them. host_debug_state are
482 * the host registers which are saved and restored during
483 * world switches. external_debug_state contains the debug
484 * values we want to debug the guest. This is set via the
485 * KVM_SET_GUEST_DEBUG ioctl.
486 *
487 * debug_ptr points to the set of debug registers that should be loaded
488 * onto the hardware when running the guest.
489 */
490 struct kvm_guest_debug_arch *debug_ptr;
491 struct kvm_guest_debug_arch vcpu_debug_state;
492 struct kvm_guest_debug_arch external_debug_state;
493
494 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
495
496 struct {
497 /* {Break,watch}point registers */
498 struct kvm_guest_debug_arch regs;
499 /* Statistical profiling extension */
500 u64 pmscr_el1;
501 /* Self-hosted trace */
502 u64 trfcr_el1;
503 } host_debug_state;
504
505 /* VGIC state */
506 struct vgic_cpu vgic_cpu;
507 struct arch_timer_cpu timer_cpu;
508 struct kvm_pmu pmu;
509
510 /*
511 * Guest registers we preserve during guest debugging.
512 *
513 * These shadow registers are updated by the kvm_handle_sys_reg
514 * trap handler if the guest accesses or updates them while we
515 * are using guest debug.
516 */
517 struct {
518 u32 mdscr_el1;
519 bool pstate_ss;
520 } guest_debug_preserved;
521
522 /* vcpu power state */
523 struct kvm_mp_state mp_state;
524 #ifndef __GENKSYMS__
525 spinlock_t mp_state_lock;
526 #endif
527
528 union {
529 /* Cache some mmu pages needed inside spinlock regions */
530 struct kvm_mmu_memory_cache mmu_page_cache;
531 /* Pages to be donated to pkvm/EL2 if it runs out */
532 struct kvm_hyp_memcache pkvm_memcache;
533 };
534
535 /* Target CPU and feature flags */
536 int target;
537 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
538
539 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
540 u64 vsesr_el2;
541
542 /* Additional reset state */
543 struct vcpu_reset_state reset_state;
544
545 /* Guest PV state */
546 struct {
547 u64 last_steal;
548 gpa_t base;
549 } steal;
550 };
551
552 /*
553 * Each 'flag' is composed of a comma-separated triplet:
554 *
555 * - the flag-set it belongs to in the vcpu->arch structure
556 * - the value for that flag
557 * - the mask for that flag
558 *
559 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
560 * unpack_vcpu_flag() extract the flag value from the triplet for
561 * direct use outside of the flag accessors.
562 */
563 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
564
565 #define __unpack_flag(_set, _f, _m) _f
566 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
567
568 #define __build_check_flag(v, flagset, f, m) \
569 do { \
570 typeof(v->arch.flagset) *_fset; \
571 \
572 /* Check that the flags fit in the mask */ \
573 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
574 /* Check that the flags fit in the type */ \
575 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
576 } while (0)
577
578 #define __vcpu_get_flag(v, flagset, f, m) \
579 ({ \
580 __build_check_flag(v, flagset, f, m); \
581 \
582 READ_ONCE(v->arch.flagset) & (m); \
583 })
584
585 /*
586 * Note that the set/clear accessors must be preempt-safe in order to
587 * avoid nesting them with load/put which also manipulate flags...
588 */
589 #ifdef __KVM_NVHE_HYPERVISOR__
590 /* the nVHE hypervisor is always non-preemptible */
591 #define __vcpu_flags_preempt_disable()
592 #define __vcpu_flags_preempt_enable()
593 #else
594 #define __vcpu_flags_preempt_disable() preempt_disable()
595 #define __vcpu_flags_preempt_enable() preempt_enable()
596 #endif
597
598 #define __vcpu_set_flag(v, flagset, f, m) \
599 do { \
600 typeof(v->arch.flagset) *fset; \
601 \
602 __build_check_flag(v, flagset, f, m); \
603 \
604 fset = &v->arch.flagset; \
605 __vcpu_flags_preempt_disable(); \
606 if (HWEIGHT(m) > 1) \
607 *fset &= ~(m); \
608 *fset |= (f); \
609 __vcpu_flags_preempt_enable(); \
610 } while (0)
611
612 #define __vcpu_clear_flag(v, flagset, f, m) \
613 do { \
614 typeof(v->arch.flagset) *fset; \
615 \
616 __build_check_flag(v, flagset, f, m); \
617 \
618 fset = &v->arch.flagset; \
619 __vcpu_flags_preempt_disable(); \
620 *fset &= ~(m); \
621 __vcpu_flags_preempt_enable(); \
622 } while (0)
623
624 #define __vcpu_copy_flag(vt, vs, flagset, f, m) \
625 do { \
626 typeof(vs->arch.flagset) tmp, val; \
627 \
628 __build_check_flag(vs, flagset, f, m); \
629 \
630 __vcpu_flags_preempt_disable(); \
631 val = READ_ONCE(vs->arch.flagset); \
632 val &= (m); \
633 tmp = READ_ONCE(vt->arch.flagset); \
634 tmp &= ~(m); \
635 tmp |= val; \
636 WRITE_ONCE(vt->arch.flagset, tmp); \
637 __vcpu_flags_preempt_enable(); \
638 } while (0)
639
640
641 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
642 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
643 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
644 #define vcpu_copy_flag(vt, vs,...) __vcpu_copy_flag((vt), (vs), __VA_ARGS__)
645
646 /* SVE exposed to guest */
647 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0))
648 /* SVE config completed */
649 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
650 /* PTRAUTH exposed to guest */
651 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2))
652
653 /* Exception pending */
654 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
655 /*
656 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
657 * be set together with an exception...
658 */
659 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
660 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
661 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
662 /* Cover both PENDING_EXCEPTION and EXCEPT_MASK for global operations */
663 #define PC_UPDATE_REQ __vcpu_single_flag(iflags, GENMASK(3, 0))
664
665 /* Helpers to encode exceptions with minimum fuss */
666 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
667 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
668 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
669
670 /*
671 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
672 * values:
673 *
674 * For AArch32 EL1:
675 */
676 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
677 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
678 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
679 /* For AArch64: */
680 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
681 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
682 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
683 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
684 /* For AArch64 with NV (one day): */
685 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
686 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
687 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
688 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
689 /* Guest debug is live */
690 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
691 /* Save SPE context if active */
692 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
693 /* Save TRBE context if active */
694 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
695 /* pKVM host vcpu state is dirty, needs resync */
696 #define PKVM_HOST_STATE_DIRTY __vcpu_single_flag(iflags, BIT(7))
697
698 /* SVE enabled for host EL0 */
699 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
700 /* SME enabled for EL0 */
701 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1))
702 /* Physical CPU not in supported_cpus */
703 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
704 /* WFIT instruction trapped */
705 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
706 /* vcpu system registers loaded on physical CPU */
707 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
708 /* Software step state is Active-pending */
709 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
710
711
712 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
713 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
714 sve_ffr_offset((vcpu)->arch.sve_max_vl))
715
716 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
717
718 #define vcpu_sve_state_size(vcpu) ({ \
719 size_t __size_ret; \
720 unsigned int __vcpu_vq; \
721 \
722 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
723 __size_ret = 0; \
724 } else { \
725 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
726 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
727 } \
728 \
729 __size_ret; \
730 })
731
732 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
733 KVM_GUESTDBG_USE_SW_BP | \
734 KVM_GUESTDBG_USE_HW | \
735 KVM_GUESTDBG_SINGLESTEP)
736
737 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
738 vcpu_get_flag(vcpu, GUEST_HAS_SVE))
739
740 #ifdef CONFIG_ARM64_PTR_AUTH
741 #define vcpu_has_ptrauth(vcpu) \
742 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
743 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
744 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
745 #else
746 #define vcpu_has_ptrauth(vcpu) false
747 #endif
748
749 #define vcpu_on_unsupported_cpu(vcpu) \
750 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
751
752 #define vcpu_set_on_unsupported_cpu(vcpu) \
753 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
754
755 #define vcpu_clear_on_unsupported_cpu(vcpu) \
756 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
757
758 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
759
760 /*
761 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
762 * memory backed version of a register, and not the one most recently
763 * accessed by a running VCPU. For example, for userspace access or
764 * for system registers that are never context switched, but only
765 * emulated.
766 */
767 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
768
769 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
770
771 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
772
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)773 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
774 {
775 /*
776 * *** VHE ONLY ***
777 *
778 * System registers listed in the switch are not saved on every
779 * exit from the guest but are only saved on vcpu_put.
780 *
781 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
782 * should never be listed below, because the guest cannot modify its
783 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
784 * thread when emulating cross-VCPU communication.
785 */
786 if (!has_vhe())
787 return false;
788
789 switch (reg) {
790 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
791 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
792 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
793 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
794 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
795 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
796 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
797 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
798 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
799 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
800 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
801 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
802 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
803 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
804 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
805 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
806 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
807 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
808 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
809 case PAR_EL1: *val = read_sysreg_par(); break;
810 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
811 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
812 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
813 default: return false;
814 }
815
816 return true;
817 }
818
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)819 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
820 {
821 /*
822 * *** VHE ONLY ***
823 *
824 * System registers listed in the switch are not restored on every
825 * entry to the guest but are only restored on vcpu_load.
826 *
827 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
828 * should never be listed below, because the MPIDR should only be set
829 * once, before running the VCPU, and never changed later.
830 */
831 if (!has_vhe())
832 return false;
833
834 switch (reg) {
835 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
836 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
837 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
838 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
839 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
840 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
841 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
842 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
843 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
844 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
845 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
846 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
847 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
848 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
849 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
850 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
851 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
852 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
853 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
854 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
855 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
856 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
857 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
858 default: return false;
859 }
860
861 return true;
862 }
863
864 #define vcpu_read_sys_reg(__vcpu, reg) \
865 ({ \
866 u64 __val = 0x8badf00d8badf00d; \
867 \
868 /* SYSREGS_ON_CPU is only used in VHE */ \
869 ((!is_nvhe_hyp_code() && \
870 vcpu_get_flag(__vcpu, SYSREGS_ON_CPU) && \
871 __vcpu_read_sys_reg_from_cpu(reg, &__val))) ? \
872 __val \
873 : \
874 ctxt_sys_reg(&__vcpu->arch.ctxt, reg); \
875 })
876
877 #define vcpu_write_sys_reg(__vcpu, __val, reg) \
878 do { \
879 /* SYSREGS_ON_CPU is only used in VHE */ \
880 if (is_nvhe_hyp_code() || \
881 !vcpu_get_flag(__vcpu, SYSREGS_ON_CPU) || \
882 !__vcpu_write_sys_reg_to_cpu(__val, reg)) \
883 ctxt_sys_reg(&__vcpu->arch.ctxt, reg) = __val; \
884 } while (0)
885
886 struct kvm_vm_stat {
887 struct kvm_vm_stat_generic generic;
888 atomic64_t protected_hyp_mem;
889 atomic64_t protected_shared_mem;
890 };
891
892 struct kvm_vcpu_stat {
893 struct kvm_vcpu_stat_generic generic;
894 u64 hvc_exit_stat;
895 u64 wfe_exit_stat;
896 u64 wfi_exit_stat;
897 u64 mmio_exit_user;
898 u64 mmio_exit_kernel;
899 u64 signal_exits;
900 u64 exits;
901 };
902
903 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
904 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
905 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
906 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
907 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
908
909 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
910 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
911
912 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
913 struct kvm_vcpu_events *events);
914
915 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
916 struct kvm_vcpu_events *events);
917
918 #define KVM_ARCH_WANT_MMU_NOTIFIER
919
920 void kvm_arm_halt_guest(struct kvm *kvm);
921 void kvm_arm_resume_guest(struct kvm *kvm);
922
923 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
924
925 #ifndef __KVM_NVHE_HYPERVISOR__
926 #define kvm_call_hyp_nvhe(f, ...) \
927 ({ \
928 struct arm_smccc_res res; \
929 \
930 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
931 ##__VA_ARGS__, &res); \
932 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
933 \
934 res.a1; \
935 })
936
937 /*
938 * The couple of isb() below are there to guarantee the same behaviour
939 * on VHE as on !VHE, where the eret to EL1 acts as a context
940 * synchronization event.
941 */
942 #define kvm_call_hyp(f, ...) \
943 do { \
944 if (has_vhe()) { \
945 f(__VA_ARGS__); \
946 isb(); \
947 } else { \
948 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
949 } \
950 } while(0)
951
952 #define kvm_call_hyp_ret(f, ...) \
953 ({ \
954 typeof(f(__VA_ARGS__)) ret; \
955 \
956 if (has_vhe()) { \
957 ret = f(__VA_ARGS__); \
958 isb(); \
959 } else { \
960 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
961 } \
962 \
963 ret; \
964 })
965 #else /* __KVM_NVHE_HYPERVISOR__ */
966 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
967 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
968 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
969 #endif /* __KVM_NVHE_HYPERVISOR__ */
970
971 void force_vm_exit(const cpumask_t *mask);
972
973 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
974 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
975
976 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
977 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
978 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
979 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
980 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
981 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
982 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
983
984 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
985
986 int kvm_sys_reg_table_init(void);
987
988 /* MMIO helpers */
989 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
990 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
991
992 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
993 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
994
995 /*
996 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
997 * arrived in guest context. For arm64, any event that arrives while a vCPU is
998 * loaded is considered to be "in guest".
999 */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1000 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1001 {
1002 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1003 }
1004
1005 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1006 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1007 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1008
1009 bool kvm_arm_pvtime_supported(void);
1010 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1011 struct kvm_device_attr *attr);
1012 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1013 struct kvm_device_attr *attr);
1014 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1015 struct kvm_device_attr *attr);
1016
1017 extern unsigned int kvm_arm_vmid_bits;
1018 int kvm_arm_vmid_alloc_init(void);
1019 void kvm_arm_vmid_alloc_free(void);
1020 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1021 void kvm_arm_vmid_clear_active(void);
1022
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1023 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1024 {
1025 vcpu_arch->steal.base = GPA_INVALID;
1026 }
1027
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1028 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1029 {
1030 return (vcpu_arch->steal.base != GPA_INVALID);
1031 }
1032
1033 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1034
1035 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1036
1037 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1038
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1039 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1040 {
1041 /* The host's MPIDR is immutable, so let's set it up at boot time */
1042 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1043 }
1044
kvm_system_needs_idmapped_vectors(void)1045 static inline bool kvm_system_needs_idmapped_vectors(void)
1046 {
1047 return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1048 }
1049
1050 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
1051
kvm_arch_hardware_unsetup(void)1052 static inline void kvm_arch_hardware_unsetup(void) {}
kvm_arch_sync_events(struct kvm * kvm)1053 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)1054 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
kvm_arch_vcpu_block_finish(struct kvm_vcpu * vcpu)1055 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
1056
1057 void kvm_arm_init_debug(void);
1058 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1059 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1060 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1061 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1062
1063 #define __vcpu_save_guest_debug_regs(vcpu) \
1064 do { \
1065 u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1); \
1066 \
1067 (vcpu)->arch.guest_debug_preserved.mdscr_el1 = val; \
1068 } while(0)
1069
1070 #define __vcpu_restore_guest_debug_regs(vcpu) \
1071 do { \
1072 u64 val = (vcpu)->arch.guest_debug_preserved.mdscr_el1; \
1073 \
1074 vcpu_write_sys_reg(vcpu, val, MDSCR_EL1); \
1075 } while (0)
1076
1077 #define kvm_vcpu_os_lock_enabled(vcpu) \
1078 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
1079
1080 #define kvm_vcpu_needs_debug_regs(vcpu) \
1081 ((vcpu)->guest_debug || kvm_vcpu_os_lock_enabled(vcpu))
1082
1083 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1084 struct kvm_device_attr *attr);
1085 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1086 struct kvm_device_attr *attr);
1087 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1088 struct kvm_device_attr *attr);
1089
1090 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1091 struct kvm_arm_copy_mte_tags *copy_tags);
1092
1093 /* Guest/host FPSIMD coordination helpers */
1094 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1095 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1096 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1097 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1098 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1099
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1100 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1101 {
1102 return (!has_vhe() && attr->exclude_host);
1103 }
1104
1105 /* Flags for host debug state */
1106 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1107 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1108
1109 #ifdef CONFIG_KVM
1110 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1111 void kvm_clr_pmu_events(u32 clr);
1112 #else
kvm_set_pmu_events(u32 set,struct perf_event_attr * attr)1113 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u32 clr)1114 static inline void kvm_clr_pmu_events(u32 clr) {}
1115 #endif
1116
1117 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1118 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1119
1120 int kvm_set_ipa_limit(void);
1121
1122 #define __KVM_HAVE_ARCH_VM_ALLOC
1123 struct kvm *kvm_arch_alloc_vm(void);
1124 void kvm_arch_free_vm(struct kvm *kvm);
1125
1126 #define kvm_vm_is_protected(kvm) ((kvm)->arch.pkvm.enabled)
1127
1128 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1129
1130 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1131 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1132
1133 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1134
1135 #define kvm_has_mte(kvm) \
1136 (system_supports_mte() && \
1137 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1138
1139 #define kvm_supports_32bit_el0() \
1140 (system_supports_32bit_el0() && \
1141 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1142
1143 int kvm_trng_call(struct kvm_vcpu *vcpu);
1144 #ifdef CONFIG_KVM
1145 extern phys_addr_t hyp_mem_base;
1146 extern phys_addr_t hyp_mem_size;
1147 void __init kvm_hyp_reserve(void);
1148 #else
kvm_hyp_reserve(void)1149 static inline void kvm_hyp_reserve(void) { }
1150 #endif
1151
1152 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1153 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1154
1155 #endif /* __ARM64_KVM_HOST_H__ */
1156