1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/auxiliary_bus.h>
8 #include <linux/bits.h>
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/i2c.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20
21 #include <asm/unaligned.h>
22
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_dp_aux_bus.h>
27 #include <drm/drm_dp_helper.h>
28 #include <drm/drm_mipi_dsi.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33
34 #define SN_DEVICE_REV_REG 0x08
35 #define SN_DPPLL_SRC_REG 0x0A
36 #define DPPLL_CLK_SRC_DSICLK BIT(0)
37 #define REFCLK_FREQ_MASK GENMASK(3, 1)
38 #define REFCLK_FREQ(x) ((x) << 1)
39 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
40 #define SN_PLL_ENABLE_REG 0x0D
41 #define SN_DSI_LANES_REG 0x10
42 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
43 #define CHA_DSI_LANES(x) ((x) << 3)
44 #define SN_DSIA_CLK_FREQ_REG 0x12
45 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
46 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
47 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
48 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
49 #define CHA_HSYNC_POLARITY BIT(7)
50 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
51 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
52 #define CHA_VSYNC_POLARITY BIT(7)
53 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
54 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
55 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
56 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
57 #define SN_LN_ASSIGN_REG 0x59
58 #define LN_ASSIGN_WIDTH 2
59 #define SN_ENH_FRAME_REG 0x5A
60 #define VSTREAM_ENABLE BIT(3)
61 #define LN_POLRS_OFFSET 4
62 #define LN_POLRS_MASK 0xf0
63 #define SN_DATA_FORMAT_REG 0x5B
64 #define BPP_18_RGB BIT(0)
65 #define SN_HPD_DISABLE_REG 0x5C
66 #define HPD_DISABLE BIT(0)
67 #define SN_GPIO_IO_REG 0x5E
68 #define SN_GPIO_INPUT_SHIFT 4
69 #define SN_GPIO_OUTPUT_SHIFT 0
70 #define SN_GPIO_CTRL_REG 0x5F
71 #define SN_GPIO_MUX_INPUT 0
72 #define SN_GPIO_MUX_OUTPUT 1
73 #define SN_GPIO_MUX_SPECIAL 2
74 #define SN_GPIO_MUX_MASK 0x3
75 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
76 #define SN_AUX_ADDR_19_16_REG 0x74
77 #define SN_AUX_ADDR_15_8_REG 0x75
78 #define SN_AUX_ADDR_7_0_REG 0x76
79 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
80 #define SN_AUX_LENGTH_REG 0x77
81 #define SN_AUX_CMD_REG 0x78
82 #define AUX_CMD_SEND BIT(0)
83 #define AUX_CMD_REQ(x) ((x) << 4)
84 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
85 #define SN_SSC_CONFIG_REG 0x93
86 #define DP_NUM_LANES_MASK GENMASK(5, 4)
87 #define DP_NUM_LANES(x) ((x) << 4)
88 #define SN_DATARATE_CONFIG_REG 0x94
89 #define DP_DATARATE_MASK GENMASK(7, 5)
90 #define DP_DATARATE(x) ((x) << 5)
91 #define SN_ML_TX_MODE_REG 0x96
92 #define ML_TX_MAIN_LINK_OFF 0
93 #define ML_TX_NORMAL_MODE BIT(0)
94 #define SN_AUX_CMD_STATUS_REG 0xF4
95 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
96 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
97 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
98
99 #define MIN_DSI_CLK_FREQ_MHZ 40
100
101 /* fudge factor required to account for 8b/10b encoding */
102 #define DP_CLK_FUDGE_NUM 10
103 #define DP_CLK_FUDGE_DEN 8
104
105 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
106 #define SN_AUX_MAX_PAYLOAD_BYTES 16
107
108 #define SN_REGULATOR_SUPPLY_NUM 4
109
110 #define SN_MAX_DP_LANES 4
111 #define SN_NUM_GPIOS 4
112 #define SN_GPIO_PHYSICAL_OFFSET 1
113
114 #define SN_LINK_TRAINING_TRIES 10
115
116 /**
117 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
118 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
119 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
120 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
121 *
122 * @dev: Pointer to the top level (i2c) device.
123 * @regmap: Regmap for accessing i2c.
124 * @aux: Our aux channel.
125 * @bridge: Our bridge.
126 * @connector: Our connector.
127 * @host_node: Remote DSI node.
128 * @dsi: Our MIPI DSI source.
129 * @refclk: Our reference clock.
130 * @next_bridge: The bridge on the eDP side.
131 * @enable_gpio: The GPIO we toggle to enable the bridge.
132 * @supplies: Data for bulk enabling/disabling our regulators.
133 * @dp_lanes: Count of dp_lanes we're using.
134 * @ln_assign: Value to program to the LN_ASSIGN register.
135 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
136 * @comms_enabled: If true then communication over the aux channel is enabled.
137 * @comms_mutex: Protects modification of comms_enabled.
138 *
139 * @gchip: If we expose our GPIOs, this is used.
140 * @gchip_output: A cache of whether we've set GPIOs to output. This
141 * serves double-duty of keeping track of the direction and
142 * also keeping track of whether we've incremented the
143 * pm_runtime reference count for this pin, which we do
144 * whenever a pin is configured as an output. This is a
145 * bitmap so we can do atomic ops on it without an extra
146 * lock so concurrent users of our 4 GPIOs don't stomp on
147 * each other's read-modify-write.
148 */
149 struct ti_sn65dsi86 {
150 struct auxiliary_device *bridge_aux;
151 struct auxiliary_device *gpio_aux;
152 struct auxiliary_device *aux_aux;
153
154 struct device *dev;
155 struct regmap *regmap;
156 struct drm_dp_aux aux;
157 struct drm_bridge bridge;
158 struct drm_connector connector;
159 struct device_node *host_node;
160 struct mipi_dsi_device *dsi;
161 struct clk *refclk;
162 struct drm_bridge *next_bridge;
163 struct gpio_desc *enable_gpio;
164 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
165 int dp_lanes;
166 u8 ln_assign;
167 u8 ln_polrs;
168 bool comms_enabled;
169 struct mutex comms_mutex;
170
171 #if defined(CONFIG_OF_GPIO)
172 struct gpio_chip gchip;
173 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
174 #endif
175 };
176
177 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
178 { .range_min = 0, .range_max = 0xFF },
179 };
180
181 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
182 .yes_ranges = ti_sn65dsi86_volatile_ranges,
183 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
184 };
185
186 static const struct regmap_config ti_sn65dsi86_regmap_config = {
187 .reg_bits = 8,
188 .val_bits = 8,
189 .volatile_table = &ti_sn_bridge_volatile_table,
190 .cache_type = REGCACHE_NONE,
191 .max_register = 0xFF,
192 };
193
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)194 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
195 unsigned int reg, u16 val)
196 {
197 regmap_write(pdata->regmap, reg, val & 0xFF);
198 regmap_write(pdata->regmap, reg + 1, val >> 8);
199 }
200
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata)201 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
202 {
203 u32 bit_rate_khz, clk_freq_khz;
204 struct drm_display_mode *mode =
205 &pdata->bridge.encoder->crtc->state->adjusted_mode;
206
207 bit_rate_khz = mode->clock *
208 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
209 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
210
211 return clk_freq_khz;
212 }
213
214 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
215 static const u32 ti_sn_bridge_refclk_lut[] = {
216 12000000,
217 19200000,
218 26000000,
219 27000000,
220 38400000,
221 };
222
223 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
224 static const u32 ti_sn_bridge_dsiclk_lut[] = {
225 468000000,
226 384000000,
227 416000000,
228 486000000,
229 460800000,
230 };
231
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata)232 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
233 {
234 int i;
235 u32 refclk_rate;
236 const u32 *refclk_lut;
237 size_t refclk_lut_size;
238
239 if (pdata->refclk) {
240 refclk_rate = clk_get_rate(pdata->refclk);
241 refclk_lut = ti_sn_bridge_refclk_lut;
242 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
243 clk_prepare_enable(pdata->refclk);
244 } else {
245 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
246 refclk_lut = ti_sn_bridge_dsiclk_lut;
247 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
248 }
249
250 /* for i equals to refclk_lut_size means default frequency */
251 for (i = 0; i < refclk_lut_size; i++)
252 if (refclk_lut[i] == refclk_rate)
253 break;
254
255 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
256 REFCLK_FREQ(i));
257 }
258
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata)259 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
260 {
261 mutex_lock(&pdata->comms_mutex);
262
263 /* configure bridge ref_clk */
264 ti_sn_bridge_set_refclk_freq(pdata);
265
266 /*
267 * HPD on this bridge chip is a bit useless. This is an eDP bridge
268 * so the HPD is an internal signal that's only there to signal that
269 * the panel is done powering up. ...but the bridge chip debounces
270 * this signal by between 100 ms and 400 ms (depending on process,
271 * voltage, and temperate--I measured it at about 200 ms). One
272 * particular panel asserted HPD 84 ms after it was powered on meaning
273 * that we saw HPD 284 ms after power on. ...but the same panel said
274 * that instead of looking at HPD you could just hardcode a delay of
275 * 200 ms. We'll assume that the panel driver will have the hardcoded
276 * delay in its prepare and always disable HPD.
277 *
278 * If HPD somehow makes sense on some future panel we'll have to
279 * change this to be conditional on someone specifying that HPD should
280 * be used.
281 */
282 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
283 HPD_DISABLE);
284
285 pdata->comms_enabled = true;
286
287 mutex_unlock(&pdata->comms_mutex);
288 }
289
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)290 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
291 {
292 mutex_lock(&pdata->comms_mutex);
293
294 pdata->comms_enabled = false;
295 clk_disable_unprepare(pdata->refclk);
296
297 mutex_unlock(&pdata->comms_mutex);
298 }
299
ti_sn65dsi86_resume(struct device * dev)300 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
301 {
302 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
303 int ret;
304
305 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
306 if (ret) {
307 DRM_ERROR("failed to enable supplies %d\n", ret);
308 return ret;
309 }
310
311 /* td2: min 100 us after regulators before enabling the GPIO */
312 usleep_range(100, 110);
313
314 gpiod_set_value(pdata->enable_gpio, 1);
315
316 /*
317 * If we have a reference clock we can enable communication w/ the
318 * panel (including the aux channel) w/out any need for an input clock
319 * so we can do it in resume which lets us read the EDID before
320 * pre_enable(). Without a reference clock we need the MIPI reference
321 * clock so reading early doesn't work.
322 */
323 if (pdata->refclk)
324 ti_sn65dsi86_enable_comms(pdata);
325
326 return ret;
327 }
328
ti_sn65dsi86_suspend(struct device * dev)329 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
330 {
331 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
332 int ret;
333
334 if (pdata->refclk)
335 ti_sn65dsi86_disable_comms(pdata);
336
337 gpiod_set_value(pdata->enable_gpio, 0);
338
339 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
340 if (ret)
341 DRM_ERROR("failed to disable supplies %d\n", ret);
342
343 return ret;
344 }
345
346 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
347 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
348 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
349 pm_runtime_force_resume)
350 };
351
status_show(struct seq_file * s,void * data)352 static int status_show(struct seq_file *s, void *data)
353 {
354 struct ti_sn65dsi86 *pdata = s->private;
355 unsigned int reg, val;
356
357 seq_puts(s, "STATUS REGISTERS:\n");
358
359 pm_runtime_get_sync(pdata->dev);
360
361 /* IRQ Status Registers, see Table 31 in datasheet */
362 for (reg = 0xf0; reg <= 0xf8; reg++) {
363 regmap_read(pdata->regmap, reg, &val);
364 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
365 }
366
367 pm_runtime_put_autosuspend(pdata->dev);
368
369 return 0;
370 }
371
372 DEFINE_SHOW_ATTRIBUTE(status);
373
ti_sn65dsi86_debugfs_remove(void * data)374 static void ti_sn65dsi86_debugfs_remove(void *data)
375 {
376 debugfs_remove_recursive(data);
377 }
378
ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 * pdata)379 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
380 {
381 struct device *dev = pdata->dev;
382 struct dentry *debugfs;
383 int ret;
384
385 debugfs = debugfs_create_dir(dev_name(dev), NULL);
386
387 /*
388 * We might get an error back if debugfs wasn't enabled in the kernel
389 * so let's just silently return upon failure.
390 */
391 if (IS_ERR_OR_NULL(debugfs))
392 return;
393
394 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
395 if (ret)
396 return;
397
398 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
399 }
400
401 /* -----------------------------------------------------------------------------
402 * Auxiliary Devices (*not* AUX)
403 */
404
ti_sn65dsi86_uninit_aux(void * data)405 static void ti_sn65dsi86_uninit_aux(void *data)
406 {
407 auxiliary_device_uninit(data);
408 }
409
ti_sn65dsi86_delete_aux(void * data)410 static void ti_sn65dsi86_delete_aux(void *data)
411 {
412 auxiliary_device_delete(data);
413 }
414
ti_sn65dsi86_aux_device_release(struct device * dev)415 static void ti_sn65dsi86_aux_device_release(struct device *dev)
416 {
417 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
418
419 kfree(aux);
420 }
421
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device ** aux_out,const char * name)422 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
423 struct auxiliary_device **aux_out,
424 const char *name)
425 {
426 struct device *dev = pdata->dev;
427 struct auxiliary_device *aux;
428 int ret;
429
430 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
431 if (!aux)
432 return -ENOMEM;
433
434 aux->name = name;
435 aux->dev.parent = dev;
436 aux->dev.release = ti_sn65dsi86_aux_device_release;
437 device_set_of_node_from_dev(&aux->dev, dev);
438 ret = auxiliary_device_init(aux);
439 if (ret) {
440 kfree(aux);
441 return ret;
442 }
443 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
444 if (ret)
445 return ret;
446
447 ret = auxiliary_device_add(aux);
448 if (ret)
449 return ret;
450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
451 if (!ret)
452 *aux_out = aux;
453
454 return ret;
455 }
456
457 /* -----------------------------------------------------------------------------
458 * AUX Adapter
459 */
460
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)461 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
462 {
463 return container_of(aux, struct ti_sn65dsi86, aux);
464 }
465
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)466 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
467 struct drm_dp_aux_msg *msg)
468 {
469 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
470 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
471 u32 request_val = AUX_CMD_REQ(msg->request);
472 u8 *buf = msg->buffer;
473 unsigned int len = msg->size;
474 unsigned int short_len;
475 unsigned int val;
476 int ret;
477 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
478
479 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
480 return -EINVAL;
481
482 pm_runtime_get_sync(pdata->dev);
483 mutex_lock(&pdata->comms_mutex);
484
485 /*
486 * If someone tries to do a DDC over AUX transaction before pre_enable()
487 * on a device without a dedicated reference clock then we just can't
488 * do it. Fail right away. This prevents non-refclk users from reading
489 * the EDID before enabling the panel but such is life.
490 */
491 if (!pdata->comms_enabled) {
492 ret = -EIO;
493 goto exit;
494 }
495
496 switch (request) {
497 case DP_AUX_NATIVE_WRITE:
498 case DP_AUX_I2C_WRITE:
499 case DP_AUX_NATIVE_READ:
500 case DP_AUX_I2C_READ:
501 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
502 /* Assume it's good */
503 msg->reply = 0;
504 break;
505 default:
506 ret = -EINVAL;
507 goto exit;
508 }
509
510 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
511 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
512 addr_len);
513 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
514 ARRAY_SIZE(addr_len));
515
516 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
517 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
518
519 /* Clear old status bits before start so we don't get confused */
520 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
521 AUX_IRQ_STATUS_NAT_I2C_FAIL |
522 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
523 AUX_IRQ_STATUS_AUX_SHORT);
524
525 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
526
527 /* Zero delay loop because i2c transactions are slow already */
528 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
529 !(val & AUX_CMD_SEND), 0, 50 * 1000);
530 if (ret)
531 goto exit;
532
533 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
534 if (ret)
535 goto exit;
536
537 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
538 /*
539 * The hardware tried the message seven times per the DP spec
540 * but it hit a timeout. We ignore defers here because they're
541 * handled in hardware.
542 */
543 ret = -ETIMEDOUT;
544 goto exit;
545 }
546
547 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
548 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
549 len = min(len, short_len);
550 if (ret)
551 goto exit;
552 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
553 switch (request) {
554 case DP_AUX_I2C_WRITE:
555 case DP_AUX_I2C_READ:
556 msg->reply |= DP_AUX_I2C_REPLY_NACK;
557 break;
558 case DP_AUX_NATIVE_READ:
559 case DP_AUX_NATIVE_WRITE:
560 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
561 break;
562 }
563 len = 0;
564 goto exit;
565 }
566
567 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
568 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
569
570 exit:
571 mutex_unlock(&pdata->comms_mutex);
572 pm_runtime_mark_last_busy(pdata->dev);
573 pm_runtime_put_autosuspend(pdata->dev);
574
575 if (ret)
576 return ret;
577 return len;
578 }
579
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)580 static int ti_sn_aux_probe(struct auxiliary_device *adev,
581 const struct auxiliary_device_id *id)
582 {
583 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
584 int ret;
585
586 pdata->aux.name = "ti-sn65dsi86-aux";
587 pdata->aux.dev = &adev->dev;
588 pdata->aux.transfer = ti_sn_aux_transfer;
589 drm_dp_aux_init(&pdata->aux);
590
591 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
592 if (ret)
593 return ret;
594
595 /*
596 * The eDP to MIPI bridge parts don't work until the AUX channel is
597 * setup so we don't add it in the main driver probe, we add it now.
598 */
599 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
600 }
601
602 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
603 { .name = "ti_sn65dsi86.aux", },
604 {},
605 };
606
607 static struct auxiliary_driver ti_sn_aux_driver = {
608 .name = "aux",
609 .probe = ti_sn_aux_probe,
610 .id_table = ti_sn_aux_id_table,
611 };
612
613 /* -----------------------------------------------------------------------------
614 * DRM Connector Operations
615 */
616
617 static struct ti_sn65dsi86 *
connector_to_ti_sn65dsi86(struct drm_connector * connector)618 connector_to_ti_sn65dsi86(struct drm_connector *connector)
619 {
620 return container_of(connector, struct ti_sn65dsi86, connector);
621 }
622
ti_sn_bridge_connector_get_modes(struct drm_connector * connector)623 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
624 {
625 struct ti_sn65dsi86 *pdata = connector_to_ti_sn65dsi86(connector);
626
627 return drm_bridge_get_modes(pdata->next_bridge, connector);
628 }
629
630 static enum drm_mode_status
ti_sn_bridge_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)631 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
632 struct drm_display_mode *mode)
633 {
634 /* maximum supported resolution is 4K at 60 fps */
635 if (mode->clock > 594000)
636 return MODE_CLOCK_HIGH;
637
638 return MODE_OK;
639 }
640
641 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
642 .get_modes = ti_sn_bridge_connector_get_modes,
643 .mode_valid = ti_sn_bridge_connector_mode_valid,
644 };
645
646 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
647 .fill_modes = drm_helper_probe_single_connector_modes,
648 .destroy = drm_connector_cleanup,
649 .reset = drm_atomic_helper_connector_reset,
650 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
651 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
652 };
653
ti_sn_bridge_connector_init(struct ti_sn65dsi86 * pdata)654 static int ti_sn_bridge_connector_init(struct ti_sn65dsi86 *pdata)
655 {
656 int ret;
657
658 ret = drm_connector_init(pdata->bridge.dev, &pdata->connector,
659 &ti_sn_bridge_connector_funcs,
660 DRM_MODE_CONNECTOR_eDP);
661 if (ret) {
662 DRM_ERROR("Failed to initialize connector with drm\n");
663 return ret;
664 }
665
666 drm_connector_helper_add(&pdata->connector,
667 &ti_sn_bridge_connector_helper_funcs);
668 drm_connector_attach_encoder(&pdata->connector, pdata->bridge.encoder);
669
670 return 0;
671 }
672
673 /*------------------------------------------------------------------------------
674 * DRM Bridge
675 */
676
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)677 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
678 {
679 return container_of(bridge, struct ti_sn65dsi86, bridge);
680 }
681
ti_sn_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)682 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
683 enum drm_bridge_attach_flags flags)
684 {
685 int ret, val;
686 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
687 struct mipi_dsi_host *host;
688 struct mipi_dsi_device *dsi;
689 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
690 .channel = 0,
691 .node = NULL,
692 };
693
694 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
695 DRM_ERROR("Fix bridge driver to make connector optional!");
696 return -EINVAL;
697 }
698
699 pdata->aux.drm_dev = bridge->dev;
700 ret = drm_dp_aux_register(&pdata->aux);
701 if (ret < 0) {
702 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
703 return ret;
704 }
705
706 ret = ti_sn_bridge_connector_init(pdata);
707 if (ret < 0)
708 goto err_conn_init;
709
710 /*
711 * TODO: ideally finding host resource and dsi dev registration needs
712 * to be done in bridge probe. But some existing DSI host drivers will
713 * wait for any of the drm_bridge/drm_panel to get added to the global
714 * bridge/panel list, before completing their probe. So if we do the
715 * dsi dev registration part in bridge probe, before populating in
716 * the global bridge list, then it will cause deadlock as dsi host probe
717 * will never complete, neither our bridge probe. So keeping it here
718 * will satisfy most of the existing host drivers. Once the host driver
719 * is fixed we can move the below code to bridge probe safely.
720 */
721 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
722 if (!host) {
723 DRM_ERROR("failed to find dsi host\n");
724 ret = -ENODEV;
725 goto err_dsi_host;
726 }
727
728 dsi = mipi_dsi_device_register_full(host, &info);
729 if (IS_ERR(dsi)) {
730 DRM_ERROR("failed to create dsi device\n");
731 ret = PTR_ERR(dsi);
732 goto err_dsi_host;
733 }
734
735 /* TODO: setting to 4 MIPI lanes always for now */
736 dsi->lanes = 4;
737 dsi->format = MIPI_DSI_FMT_RGB888;
738 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
739
740 /* check if continuous dsi clock is required or not */
741 pm_runtime_get_sync(pdata->dev);
742 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
743 pm_runtime_put_autosuspend(pdata->dev);
744 if (!(val & DPPLL_CLK_SRC_DSICLK))
745 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
746
747 ret = mipi_dsi_attach(dsi);
748 if (ret < 0) {
749 DRM_ERROR("failed to attach dsi to host\n");
750 goto err_dsi_attach;
751 }
752 pdata->dsi = dsi;
753
754 /* We never want the next bridge to *also* create a connector: */
755 flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
756
757 /* Attach the next bridge */
758 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
759 &pdata->bridge, flags);
760 if (ret < 0)
761 goto err_dsi_detach;
762
763 return 0;
764
765 err_dsi_detach:
766 mipi_dsi_detach(dsi);
767 err_dsi_attach:
768 mipi_dsi_device_unregister(dsi);
769 err_dsi_host:
770 drm_connector_cleanup(&pdata->connector);
771 err_conn_init:
772 drm_dp_aux_unregister(&pdata->aux);
773 return ret;
774 }
775
ti_sn_bridge_detach(struct drm_bridge * bridge)776 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
777 {
778 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
779 }
780
ti_sn_bridge_disable(struct drm_bridge * bridge)781 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
782 {
783 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
784
785 /* disable video stream */
786 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
787 }
788
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata)789 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
790 {
791 unsigned int bit_rate_mhz, clk_freq_mhz;
792 unsigned int val;
793 struct drm_display_mode *mode =
794 &pdata->bridge.encoder->crtc->state->adjusted_mode;
795
796 /* set DSIA clk frequency */
797 bit_rate_mhz = (mode->clock / 1000) *
798 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
799 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
800
801 /* for each increment in val, frequency increases by 5MHz */
802 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
803 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
804 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
805 }
806
ti_sn_bridge_get_bpp(struct ti_sn65dsi86 * pdata)807 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
808 {
809 if (pdata->connector.display_info.bpc <= 6)
810 return 18;
811 else
812 return 24;
813 }
814
815 /*
816 * LUT index corresponds to register value and
817 * LUT values corresponds to dp data rate supported
818 * by the bridge in Mbps unit.
819 */
820 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
821 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
822 };
823
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata)824 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
825 {
826 unsigned int bit_rate_khz, dp_rate_mhz;
827 unsigned int i;
828 struct drm_display_mode *mode =
829 &pdata->bridge.encoder->crtc->state->adjusted_mode;
830
831 /* Calculate minimum bit rate based on our pixel clock. */
832 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
833
834 /* Calculate minimum DP data rate, taking 80% as per DP spec */
835 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
836 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
837
838 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
839 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
840 break;
841
842 return i;
843 }
844
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)845 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
846 {
847 unsigned int valid_rates = 0;
848 unsigned int rate_per_200khz;
849 unsigned int rate_mhz;
850 u8 dpcd_val;
851 int ret;
852 int i, j;
853
854 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
855 if (ret != 1) {
856 DRM_DEV_ERROR(pdata->dev,
857 "Can't read eDP rev (%d), assuming 1.1\n", ret);
858 dpcd_val = DP_EDP_11;
859 }
860
861 if (dpcd_val >= DP_EDP_14) {
862 /* eDP 1.4 devices must provide a custom table */
863 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
864
865 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
866 sink_rates, sizeof(sink_rates));
867
868 if (ret != sizeof(sink_rates)) {
869 DRM_DEV_ERROR(pdata->dev,
870 "Can't read supported rate table (%d)\n", ret);
871
872 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
873 memset(sink_rates, 0, sizeof(sink_rates));
874 }
875
876 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
877 rate_per_200khz = le16_to_cpu(sink_rates[i]);
878
879 if (!rate_per_200khz)
880 break;
881
882 rate_mhz = rate_per_200khz * 200 / 1000;
883 for (j = 0;
884 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
885 j++) {
886 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
887 valid_rates |= BIT(j);
888 }
889 }
890
891 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
892 if (valid_rates & BIT(i))
893 return valid_rates;
894 }
895 DRM_DEV_ERROR(pdata->dev,
896 "No matching eDP rates in table; falling back\n");
897 }
898
899 /* On older versions best we can do is use DP_MAX_LINK_RATE */
900 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
901 if (ret != 1) {
902 DRM_DEV_ERROR(pdata->dev,
903 "Can't read max rate (%d); assuming 5.4 GHz\n",
904 ret);
905 dpcd_val = DP_LINK_BW_5_4;
906 }
907
908 switch (dpcd_val) {
909 default:
910 DRM_DEV_ERROR(pdata->dev,
911 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
912 (int)dpcd_val);
913 fallthrough;
914 case DP_LINK_BW_5_4:
915 valid_rates |= BIT(7);
916 fallthrough;
917 case DP_LINK_BW_2_7:
918 valid_rates |= BIT(4);
919 fallthrough;
920 case DP_LINK_BW_1_62:
921 valid_rates |= BIT(1);
922 break;
923 }
924
925 return valid_rates;
926 }
927
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata)928 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
929 {
930 struct drm_display_mode *mode =
931 &pdata->bridge.encoder->crtc->state->adjusted_mode;
932 u8 hsync_polarity = 0, vsync_polarity = 0;
933
934 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
935 hsync_polarity = CHA_HSYNC_POLARITY;
936 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
937 vsync_polarity = CHA_VSYNC_POLARITY;
938
939 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
940 mode->hdisplay);
941 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
942 mode->vdisplay);
943 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
944 (mode->hsync_end - mode->hsync_start) & 0xFF);
945 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
946 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
947 hsync_polarity);
948 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
949 (mode->vsync_end - mode->vsync_start) & 0xFF);
950 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
951 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
952 vsync_polarity);
953
954 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
955 (mode->htotal - mode->hsync_end) & 0xFF);
956 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
957 (mode->vtotal - mode->vsync_end) & 0xFF);
958
959 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
960 (mode->hsync_start - mode->hdisplay) & 0xFF);
961 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
962 (mode->vsync_start - mode->vdisplay) & 0xFF);
963
964 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
965 }
966
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)967 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
968 {
969 u8 data;
970 int ret;
971
972 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
973 if (ret != 1) {
974 DRM_DEV_ERROR(pdata->dev,
975 "Can't read lane count (%d); assuming 4\n", ret);
976 return 4;
977 }
978
979 return data & DP_LANE_COUNT_MASK;
980 }
981
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)982 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
983 const char **last_err_str)
984 {
985 unsigned int val;
986 int ret;
987 int i;
988
989 /* set dp clk frequency value */
990 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
991 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
992
993 /* enable DP PLL */
994 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
995
996 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
997 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
998 50 * 1000);
999 if (ret) {
1000 *last_err_str = "DP_PLL_LOCK polling failed";
1001 goto exit;
1002 }
1003
1004 /*
1005 * We'll try to link train several times. As part of link training
1006 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1007 * the panel isn't ready quite it might respond NAK here which means
1008 * we need to try again.
1009 */
1010 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1011 /* Semi auto link training mode */
1012 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1013 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1014 val == ML_TX_MAIN_LINK_OFF ||
1015 val == ML_TX_NORMAL_MODE, 1000,
1016 500 * 1000);
1017 if (ret) {
1018 *last_err_str = "Training complete polling failed";
1019 } else if (val == ML_TX_MAIN_LINK_OFF) {
1020 *last_err_str = "Link training failed, link is off";
1021 ret = -EIO;
1022 continue;
1023 }
1024
1025 break;
1026 }
1027
1028 /* If we saw quite a few retries, add a note about it */
1029 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1030 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1031
1032 exit:
1033 /* Disable the PLL if we failed */
1034 if (ret)
1035 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1036
1037 return ret;
1038 }
1039
ti_sn_bridge_enable(struct drm_bridge * bridge)1040 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
1041 {
1042 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1043 const char *last_err_str = "No supported DP rate";
1044 unsigned int valid_rates;
1045 int dp_rate_idx;
1046 unsigned int val;
1047 int ret = -EINVAL;
1048 int max_dp_lanes;
1049
1050 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1051 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1052
1053 /* DSI_A lane config */
1054 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1055 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1056 CHA_DSI_LANES_MASK, val);
1057
1058 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1059 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1060 pdata->ln_polrs << LN_POLRS_OFFSET);
1061
1062 /* set dsi clk frequency value */
1063 ti_sn_bridge_set_dsi_rate(pdata);
1064
1065 /*
1066 * The SN65DSI86 only supports ASSR Display Authentication method and
1067 * this method is enabled by default. An eDP panel must support this
1068 * authentication method. We need to enable this method in the eDP panel
1069 * at DisplayPort address 0x0010A prior to link training.
1070 */
1071 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1072 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1073
1074 /* Set the DP output format (18 bpp or 24 bpp) */
1075 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
1076 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1077
1078 /* DP lane config */
1079 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1080 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1081 val);
1082
1083 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1084
1085 /* Train until we run out of rates */
1086 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
1087 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1088 dp_rate_idx++) {
1089 if (!(valid_rates & BIT(dp_rate_idx)))
1090 continue;
1091
1092 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1093 if (!ret)
1094 break;
1095 }
1096 if (ret) {
1097 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1098 return;
1099 }
1100
1101 /* config video parameters */
1102 ti_sn_bridge_set_video_timings(pdata);
1103
1104 /* enable video stream */
1105 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1106 VSTREAM_ENABLE);
1107 }
1108
ti_sn_bridge_pre_enable(struct drm_bridge * bridge)1109 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
1110 {
1111 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1112
1113 pm_runtime_get_sync(pdata->dev);
1114
1115 if (!pdata->refclk)
1116 ti_sn65dsi86_enable_comms(pdata);
1117
1118 /* td7: min 100 us after enable before DSI data */
1119 usleep_range(100, 110);
1120 }
1121
ti_sn_bridge_post_disable(struct drm_bridge * bridge)1122 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
1123 {
1124 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1125
1126 /* semi auto link training mode OFF */
1127 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1128 /* Num lanes to 0 as per power sequencing in data sheet */
1129 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1130 /* disable DP PLL */
1131 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1132
1133 if (!pdata->refclk)
1134 ti_sn65dsi86_disable_comms(pdata);
1135
1136 pm_runtime_put_sync(pdata->dev);
1137 }
1138
1139 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1140 .attach = ti_sn_bridge_attach,
1141 .detach = ti_sn_bridge_detach,
1142 .pre_enable = ti_sn_bridge_pre_enable,
1143 .enable = ti_sn_bridge_enable,
1144 .disable = ti_sn_bridge_disable,
1145 .post_disable = ti_sn_bridge_post_disable,
1146 };
1147
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1148 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1149 struct device_node *np)
1150 {
1151 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1152 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1153 struct device_node *endpoint;
1154 u8 ln_assign = 0;
1155 u8 ln_polrs = 0;
1156 int dp_lanes;
1157 int i;
1158
1159 /*
1160 * Read config from the device tree about lane remapping and lane
1161 * polarities. These are optional and we assume identity map and
1162 * normal polarity if nothing is specified. It's OK to specify just
1163 * data-lanes but not lane-polarities but not vice versa.
1164 *
1165 * Error checking is light (we just make sure we don't crash or
1166 * buffer overrun) and we assume dts is well formed and specifying
1167 * mappings that the hardware supports.
1168 */
1169 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1170 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1171 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1172 of_property_read_u32_array(endpoint, "data-lanes",
1173 lane_assignments, dp_lanes);
1174 of_property_read_u32_array(endpoint, "lane-polarities",
1175 lane_polarities, dp_lanes);
1176 } else {
1177 dp_lanes = SN_MAX_DP_LANES;
1178 }
1179 of_node_put(endpoint);
1180
1181 /*
1182 * Convert into register format. Loop over all lanes even if
1183 * data-lanes had fewer elements so that we nicely initialize
1184 * the LN_ASSIGN register.
1185 */
1186 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1187 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1188 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1189 }
1190
1191 /* Stash in our struct for when we power on */
1192 pdata->dp_lanes = dp_lanes;
1193 pdata->ln_assign = ln_assign;
1194 pdata->ln_polrs = ln_polrs;
1195 }
1196
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1197 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1198 {
1199 struct device_node *np = pdata->dev->of_node;
1200
1201 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1202
1203 if (!pdata->host_node) {
1204 DRM_ERROR("remote dsi host node not found\n");
1205 return -ENODEV;
1206 }
1207
1208 return 0;
1209 }
1210
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1211 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1212 const struct auxiliary_device_id *id)
1213 {
1214 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1215 struct device_node *np = pdata->dev->of_node;
1216 struct drm_panel *panel;
1217 int ret;
1218
1219 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
1220 if (ret)
1221 return dev_err_probe(&adev->dev, ret,
1222 "could not find any panel node\n");
1223
1224 pdata->next_bridge = devm_drm_panel_bridge_add(pdata->dev, panel);
1225 if (IS_ERR(pdata->next_bridge)) {
1226 DRM_ERROR("failed to create panel bridge\n");
1227 return PTR_ERR(pdata->next_bridge);
1228 }
1229
1230 ti_sn_bridge_parse_lanes(pdata, np);
1231
1232 ret = ti_sn_bridge_parse_dsi_host(pdata);
1233 if (ret)
1234 return ret;
1235
1236 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1237 pdata->bridge.of_node = np;
1238
1239 drm_bridge_add(&pdata->bridge);
1240
1241 return 0;
1242 }
1243
ti_sn_bridge_remove(struct auxiliary_device * adev)1244 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1245 {
1246 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1247
1248 if (!pdata)
1249 return;
1250
1251 if (pdata->dsi) {
1252 mipi_dsi_detach(pdata->dsi);
1253 mipi_dsi_device_unregister(pdata->dsi);
1254 }
1255
1256 drm_bridge_remove(&pdata->bridge);
1257
1258 of_node_put(pdata->host_node);
1259 }
1260
1261 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1262 { .name = "ti_sn65dsi86.bridge", },
1263 {},
1264 };
1265
1266 static struct auxiliary_driver ti_sn_bridge_driver = {
1267 .name = "bridge",
1268 .probe = ti_sn_bridge_probe,
1269 .remove = ti_sn_bridge_remove,
1270 .id_table = ti_sn_bridge_id_table,
1271 };
1272
1273 /* -----------------------------------------------------------------------------
1274 * GPIO Controller
1275 */
1276
1277 #if defined(CONFIG_OF_GPIO)
1278
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1279 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1280 const struct of_phandle_args *gpiospec,
1281 u32 *flags)
1282 {
1283 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1284 return -EINVAL;
1285
1286 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1287 return -EINVAL;
1288
1289 if (flags)
1290 *flags = gpiospec->args[1];
1291
1292 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1293 }
1294
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1295 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1296 unsigned int offset)
1297 {
1298 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1299
1300 /*
1301 * We already have to keep track of the direction because we use
1302 * that to figure out whether we've powered the device. We can
1303 * just return that rather than (maybe) powering up the device
1304 * to ask its direction.
1305 */
1306 return test_bit(offset, pdata->gchip_output) ?
1307 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1308 }
1309
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1310 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1311 {
1312 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1313 unsigned int val;
1314 int ret;
1315
1316 /*
1317 * When the pin is an input we don't forcibly keep the bridge
1318 * powered--we just power it on to read the pin. NOTE: part of
1319 * the reason this works is that the bridge defaults (when
1320 * powered back on) to all 4 GPIOs being configured as GPIO input.
1321 * Also note that if something else is keeping the chip powered the
1322 * pm_runtime functions are lightweight increments of a refcount.
1323 */
1324 pm_runtime_get_sync(pdata->dev);
1325 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1326 pm_runtime_put_autosuspend(pdata->dev);
1327
1328 if (ret)
1329 return ret;
1330
1331 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1332 }
1333
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1334 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1335 int val)
1336 {
1337 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1338 int ret;
1339
1340 if (!test_bit(offset, pdata->gchip_output)) {
1341 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1342 return;
1343 }
1344
1345 val &= 1;
1346 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1347 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1348 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1349 if (ret)
1350 dev_warn(pdata->dev,
1351 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1352 }
1353
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1354 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1355 unsigned int offset)
1356 {
1357 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1358 int shift = offset * 2;
1359 int ret;
1360
1361 if (!test_and_clear_bit(offset, pdata->gchip_output))
1362 return 0;
1363
1364 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1365 SN_GPIO_MUX_MASK << shift,
1366 SN_GPIO_MUX_INPUT << shift);
1367 if (ret) {
1368 set_bit(offset, pdata->gchip_output);
1369 return ret;
1370 }
1371
1372 /*
1373 * NOTE: if nobody else is powering the device this may fully power
1374 * it off and when it comes back it will have lost all state, but
1375 * that's OK because the default is input and we're now an input.
1376 */
1377 pm_runtime_put_autosuspend(pdata->dev);
1378
1379 return 0;
1380 }
1381
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1382 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1383 unsigned int offset, int val)
1384 {
1385 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1386 int shift = offset * 2;
1387 int ret;
1388
1389 if (test_and_set_bit(offset, pdata->gchip_output))
1390 return 0;
1391
1392 pm_runtime_get_sync(pdata->dev);
1393
1394 /* Set value first to avoid glitching */
1395 ti_sn_bridge_gpio_set(chip, offset, val);
1396
1397 /* Set direction */
1398 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1399 SN_GPIO_MUX_MASK << shift,
1400 SN_GPIO_MUX_OUTPUT << shift);
1401 if (ret) {
1402 clear_bit(offset, pdata->gchip_output);
1403 pm_runtime_put_autosuspend(pdata->dev);
1404 }
1405
1406 return ret;
1407 }
1408
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1409 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1410 {
1411 /* We won't keep pm_runtime if we're input, so switch there on free */
1412 ti_sn_bridge_gpio_direction_input(chip, offset);
1413 }
1414
1415 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1416 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1417 };
1418
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1419 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1420 const struct auxiliary_device_id *id)
1421 {
1422 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1423 int ret;
1424
1425 /* Only init if someone is going to use us as a GPIO controller */
1426 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1427 return 0;
1428
1429 pdata->gchip.label = dev_name(pdata->dev);
1430 pdata->gchip.parent = pdata->dev;
1431 pdata->gchip.owner = THIS_MODULE;
1432 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1433 pdata->gchip.of_gpio_n_cells = 2;
1434 pdata->gchip.free = ti_sn_bridge_gpio_free;
1435 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1436 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1437 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1438 pdata->gchip.get = ti_sn_bridge_gpio_get;
1439 pdata->gchip.set = ti_sn_bridge_gpio_set;
1440 pdata->gchip.can_sleep = true;
1441 pdata->gchip.names = ti_sn_bridge_gpio_names;
1442 pdata->gchip.ngpio = SN_NUM_GPIOS;
1443 pdata->gchip.base = -1;
1444 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1445 if (ret)
1446 dev_err(pdata->dev, "can't add gpio chip\n");
1447
1448 return ret;
1449 }
1450
1451 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1452 { .name = "ti_sn65dsi86.gpio", },
1453 {},
1454 };
1455
1456 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1457
1458 static struct auxiliary_driver ti_sn_gpio_driver = {
1459 .name = "gpio",
1460 .probe = ti_sn_gpio_probe,
1461 .id_table = ti_sn_gpio_id_table,
1462 };
1463
ti_sn_gpio_register(void)1464 static int __init ti_sn_gpio_register(void)
1465 {
1466 return auxiliary_driver_register(&ti_sn_gpio_driver);
1467 }
1468
ti_sn_gpio_unregister(void)1469 static void ti_sn_gpio_unregister(void)
1470 {
1471 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1472 }
1473
1474 #else
1475
ti_sn_gpio_register(void)1476 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1477 static inline void ti_sn_gpio_unregister(void) {}
1478
1479 #endif
1480
1481 /* -----------------------------------------------------------------------------
1482 * Probe & Remove
1483 */
1484
ti_sn65dsi86_runtime_disable(void * data)1485 static void ti_sn65dsi86_runtime_disable(void *data)
1486 {
1487 pm_runtime_dont_use_autosuspend(data);
1488 pm_runtime_disable(data);
1489 }
1490
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1491 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1492 {
1493 unsigned int i;
1494 const char * const ti_sn_bridge_supply_names[] = {
1495 "vcca", "vcc", "vccio", "vpll",
1496 };
1497
1498 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1499 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1500
1501 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1502 pdata->supplies);
1503 }
1504
ti_sn65dsi86_probe(struct i2c_client * client,const struct i2c_device_id * id)1505 static int ti_sn65dsi86_probe(struct i2c_client *client,
1506 const struct i2c_device_id *id)
1507 {
1508 struct device *dev = &client->dev;
1509 struct ti_sn65dsi86 *pdata;
1510 int ret;
1511
1512 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1513 DRM_ERROR("device doesn't support I2C\n");
1514 return -ENODEV;
1515 }
1516
1517 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1518 if (!pdata)
1519 return -ENOMEM;
1520 dev_set_drvdata(dev, pdata);
1521 pdata->dev = dev;
1522
1523 mutex_init(&pdata->comms_mutex);
1524
1525 pdata->regmap = devm_regmap_init_i2c(client,
1526 &ti_sn65dsi86_regmap_config);
1527 if (IS_ERR(pdata->regmap))
1528 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1529 "regmap i2c init failed\n");
1530
1531 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1532 GPIOD_OUT_LOW);
1533 if (IS_ERR(pdata->enable_gpio))
1534 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1535 "failed to get enable gpio from DT\n");
1536
1537 ret = ti_sn65dsi86_parse_regulators(pdata);
1538 if (ret)
1539 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1540
1541 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1542 if (IS_ERR(pdata->refclk))
1543 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1544 "failed to get reference clock\n");
1545
1546 pm_runtime_enable(dev);
1547 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1548 pm_runtime_use_autosuspend(pdata->dev);
1549 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1550 if (ret)
1551 return ret;
1552
1553 ti_sn65dsi86_debugfs_init(pdata);
1554
1555 /*
1556 * Break ourselves up into a collection of aux devices. The only real
1557 * motiviation here is to solve the chicken-and-egg problem of probe
1558 * ordering. The bridge wants the panel to be there when it probes.
1559 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1560 * when it probes. The panel and maybe backlight might want the DDC
1561 * bus. Soon the PWM provided by the bridge chip will have the same
1562 * problem. Having sub-devices allows the some sub devices to finish
1563 * probing even if others return -EPROBE_DEFER and gets us around the
1564 * problems.
1565 */
1566
1567 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1568 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1569 if (ret)
1570 return ret;
1571 }
1572
1573 /*
1574 * NOTE: At the end of the AUX channel probe we'll add the aux device
1575 * for the bridge. This is because the bridge can't be used until the
1576 * AUX channel is there and this is a very simple solution to the
1577 * dependency problem.
1578 */
1579 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1580 }
1581
1582 static struct i2c_device_id ti_sn65dsi86_id[] = {
1583 { "ti,sn65dsi86", 0},
1584 {},
1585 };
1586 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1587
1588 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1589 {.compatible = "ti,sn65dsi86"},
1590 {},
1591 };
1592 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1593
1594 static struct i2c_driver ti_sn65dsi86_driver = {
1595 .driver = {
1596 .name = "ti_sn65dsi86",
1597 .of_match_table = ti_sn65dsi86_match_table,
1598 .pm = &ti_sn65dsi86_pm_ops,
1599 },
1600 .probe = ti_sn65dsi86_probe,
1601 .id_table = ti_sn65dsi86_id,
1602 };
1603
ti_sn65dsi86_init(void)1604 static int __init ti_sn65dsi86_init(void)
1605 {
1606 int ret;
1607
1608 ret = i2c_add_driver(&ti_sn65dsi86_driver);
1609 if (ret)
1610 return ret;
1611
1612 ret = ti_sn_gpio_register();
1613 if (ret)
1614 goto err_main_was_registered;
1615
1616 ret = auxiliary_driver_register(&ti_sn_aux_driver);
1617 if (ret)
1618 goto err_gpio_was_registered;
1619
1620 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1621 if (ret)
1622 goto err_aux_was_registered;
1623
1624 return 0;
1625
1626 err_aux_was_registered:
1627 auxiliary_driver_unregister(&ti_sn_aux_driver);
1628 err_gpio_was_registered:
1629 ti_sn_gpio_unregister();
1630 err_main_was_registered:
1631 i2c_del_driver(&ti_sn65dsi86_driver);
1632
1633 return ret;
1634 }
1635 module_init(ti_sn65dsi86_init);
1636
ti_sn65dsi86_exit(void)1637 static void __exit ti_sn65dsi86_exit(void)
1638 {
1639 auxiliary_driver_unregister(&ti_sn_bridge_driver);
1640 auxiliary_driver_unregister(&ti_sn_aux_driver);
1641 ti_sn_gpio_unregister();
1642 i2c_del_driver(&ti_sn65dsi86_driver);
1643 }
1644 module_exit(ti_sn65dsi86_exit);
1645
1646 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1647 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1648 MODULE_LICENSE("GPL v2");
1649