1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/eq.h>
44 #include <linux/debugfs.h>
45
46 #include "mlx5_core.h"
47 #include "lib/eq.h"
48
49 enum {
50 CMD_IF_REV = 5,
51 };
52
53 enum {
54 CMD_MODE_POLLING,
55 CMD_MODE_EVENTS
56 };
57
58 enum {
59 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70 };
71
72 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)73 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
74 struct mlx5_cmd_msg *out, void *uout, int uout_size,
75 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
76 {
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
79
80 ent = kzalloc(sizeof(*ent), alloc_flags);
81 if (!ent)
82 return ERR_PTR(-ENOMEM);
83
84 ent->idx = -EINVAL;
85 ent->in = in;
86 ent->out = out;
87 ent->uout = uout;
88 ent->uout_size = uout_size;
89 ent->callback = cbk;
90 ent->context = context;
91 ent->cmd = cmd;
92 ent->page_queue = page_queue;
93 refcount_set(&ent->refcnt, 1);
94
95 return ent;
96 }
97
cmd_free_ent(struct mlx5_cmd_work_ent * ent)98 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
99 {
100 kfree(ent);
101 }
102
alloc_token(struct mlx5_cmd * cmd)103 static u8 alloc_token(struct mlx5_cmd *cmd)
104 {
105 u8 token;
106
107 spin_lock(&cmd->token_lock);
108 cmd->token++;
109 if (cmd->token == 0)
110 cmd->token++;
111 token = cmd->token;
112 spin_unlock(&cmd->token_lock);
113
114 return token;
115 }
116
cmd_alloc_index(struct mlx5_cmd * cmd)117 static int cmd_alloc_index(struct mlx5_cmd *cmd)
118 {
119 unsigned long flags;
120 int ret;
121
122 spin_lock_irqsave(&cmd->alloc_lock, flags);
123 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
124 if (ret < cmd->max_reg_cmds)
125 clear_bit(ret, &cmd->bitmask);
126 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
127
128 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
129 }
130
cmd_free_index(struct mlx5_cmd * cmd,int idx)131 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
132 {
133 lockdep_assert_held(&cmd->alloc_lock);
134 set_bit(idx, &cmd->bitmask);
135 }
136
cmd_ent_get(struct mlx5_cmd_work_ent * ent)137 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
138 {
139 refcount_inc(&ent->refcnt);
140 }
141
cmd_ent_put(struct mlx5_cmd_work_ent * ent)142 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
143 {
144 struct mlx5_cmd *cmd = ent->cmd;
145 unsigned long flags;
146
147 spin_lock_irqsave(&cmd->alloc_lock, flags);
148 if (!refcount_dec_and_test(&ent->refcnt))
149 goto out;
150
151 if (ent->idx >= 0) {
152 cmd_free_index(cmd, ent->idx);
153 up(ent->page_queue ? &cmd->pages_sem : &cmd->sem);
154 }
155
156 cmd_free_ent(ent);
157 out:
158 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
159 }
160
get_inst(struct mlx5_cmd * cmd,int idx)161 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
162 {
163 return cmd->cmd_buf + (idx << cmd->log_stride);
164 }
165
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)166 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
167 {
168 int size = msg->len;
169 int blen = size - min_t(int, sizeof(msg->first.data), size);
170
171 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
172 }
173
xor8_buf(void * buf,size_t offset,int len)174 static u8 xor8_buf(void *buf, size_t offset, int len)
175 {
176 u8 *ptr = buf;
177 u8 sum = 0;
178 int i;
179 int end = len + offset;
180
181 for (i = offset; i < end; i++)
182 sum ^= ptr[i];
183
184 return sum;
185 }
186
verify_block_sig(struct mlx5_cmd_prot_block * block)187 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
188 {
189 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
190 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
191
192 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
193 return -EINVAL;
194
195 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
196 return -EINVAL;
197
198 return 0;
199 }
200
calc_block_sig(struct mlx5_cmd_prot_block * block)201 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
202 {
203 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
204 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
205
206 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
207 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
208 }
209
calc_chain_sig(struct mlx5_cmd_msg * msg)210 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
211 {
212 struct mlx5_cmd_mailbox *next = msg->next;
213 int n = mlx5_calc_cmd_blocks(msg);
214 int i = 0;
215
216 for (i = 0; i < n && next; i++) {
217 calc_block_sig(next->buf);
218 next = next->next;
219 }
220 }
221
set_signature(struct mlx5_cmd_work_ent * ent,int csum)222 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
223 {
224 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
225 if (csum) {
226 calc_chain_sig(ent->in);
227 calc_chain_sig(ent->out);
228 }
229 }
230
poll_timeout(struct mlx5_cmd_work_ent * ent)231 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
232 {
233 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
234 u8 own;
235
236 do {
237 own = READ_ONCE(ent->lay->status_own);
238 if (!(own & CMD_OWNER_HW)) {
239 ent->ret = 0;
240 return;
241 }
242 cond_resched();
243 } while (time_before(jiffies, poll_end));
244
245 ent->ret = -ETIMEDOUT;
246 }
247
verify_signature(struct mlx5_cmd_work_ent * ent)248 static int verify_signature(struct mlx5_cmd_work_ent *ent)
249 {
250 struct mlx5_cmd_mailbox *next = ent->out->next;
251 int n = mlx5_calc_cmd_blocks(ent->out);
252 int err;
253 u8 sig;
254 int i = 0;
255
256 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
257 if (sig != 0xff)
258 return -EINVAL;
259
260 for (i = 0; i < n && next; i++) {
261 err = verify_block_sig(next->buf);
262 if (err)
263 return err;
264
265 next = next->next;
266 }
267
268 return 0;
269 }
270
dump_buf(void * buf,int size,int data_only,int offset,int idx)271 static void dump_buf(void *buf, int size, int data_only, int offset, int idx)
272 {
273 __be32 *p = buf;
274 int i;
275
276 for (i = 0; i < size; i += 16) {
277 pr_debug("cmd[%d]: %03x: %08x %08x %08x %08x\n", idx, offset,
278 be32_to_cpu(p[0]), be32_to_cpu(p[1]),
279 be32_to_cpu(p[2]), be32_to_cpu(p[3]));
280 p += 4;
281 offset += 16;
282 }
283 if (!data_only)
284 pr_debug("\n");
285 }
286
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)287 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
288 u32 *synd, u8 *status)
289 {
290 *synd = 0;
291 *status = 0;
292
293 switch (op) {
294 case MLX5_CMD_OP_TEARDOWN_HCA:
295 case MLX5_CMD_OP_DISABLE_HCA:
296 case MLX5_CMD_OP_MANAGE_PAGES:
297 case MLX5_CMD_OP_DESTROY_MKEY:
298 case MLX5_CMD_OP_DESTROY_EQ:
299 case MLX5_CMD_OP_DESTROY_CQ:
300 case MLX5_CMD_OP_DESTROY_QP:
301 case MLX5_CMD_OP_DESTROY_PSV:
302 case MLX5_CMD_OP_DESTROY_SRQ:
303 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
304 case MLX5_CMD_OP_DESTROY_XRQ:
305 case MLX5_CMD_OP_DESTROY_DCT:
306 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
307 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
308 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
309 case MLX5_CMD_OP_DEALLOC_PD:
310 case MLX5_CMD_OP_DEALLOC_UAR:
311 case MLX5_CMD_OP_DETACH_FROM_MCG:
312 case MLX5_CMD_OP_DEALLOC_XRCD:
313 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
314 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
315 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
316 case MLX5_CMD_OP_DESTROY_LAG:
317 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
318 case MLX5_CMD_OP_DESTROY_TIR:
319 case MLX5_CMD_OP_DESTROY_SQ:
320 case MLX5_CMD_OP_DESTROY_RQ:
321 case MLX5_CMD_OP_DESTROY_RMP:
322 case MLX5_CMD_OP_DESTROY_TIS:
323 case MLX5_CMD_OP_DESTROY_RQT:
324 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
325 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
326 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
327 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
328 case MLX5_CMD_OP_2ERR_QP:
329 case MLX5_CMD_OP_2RST_QP:
330 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
331 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
332 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
333 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
334 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
335 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
336 case MLX5_CMD_OP_FPGA_DESTROY_QP:
337 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
338 case MLX5_CMD_OP_DEALLOC_MEMIC:
339 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
340 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
341 case MLX5_CMD_OP_DEALLOC_SF:
342 case MLX5_CMD_OP_DESTROY_UCTX:
343 case MLX5_CMD_OP_DESTROY_UMEM:
344 case MLX5_CMD_OP_MODIFY_RQT:
345 return MLX5_CMD_STAT_OK;
346
347 case MLX5_CMD_OP_QUERY_HCA_CAP:
348 case MLX5_CMD_OP_QUERY_ADAPTER:
349 case MLX5_CMD_OP_INIT_HCA:
350 case MLX5_CMD_OP_ENABLE_HCA:
351 case MLX5_CMD_OP_QUERY_PAGES:
352 case MLX5_CMD_OP_SET_HCA_CAP:
353 case MLX5_CMD_OP_QUERY_ISSI:
354 case MLX5_CMD_OP_SET_ISSI:
355 case MLX5_CMD_OP_CREATE_MKEY:
356 case MLX5_CMD_OP_QUERY_MKEY:
357 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
358 case MLX5_CMD_OP_CREATE_EQ:
359 case MLX5_CMD_OP_QUERY_EQ:
360 case MLX5_CMD_OP_GEN_EQE:
361 case MLX5_CMD_OP_CREATE_CQ:
362 case MLX5_CMD_OP_QUERY_CQ:
363 case MLX5_CMD_OP_MODIFY_CQ:
364 case MLX5_CMD_OP_CREATE_QP:
365 case MLX5_CMD_OP_RST2INIT_QP:
366 case MLX5_CMD_OP_INIT2RTR_QP:
367 case MLX5_CMD_OP_RTR2RTS_QP:
368 case MLX5_CMD_OP_RTS2RTS_QP:
369 case MLX5_CMD_OP_SQERR2RTS_QP:
370 case MLX5_CMD_OP_QUERY_QP:
371 case MLX5_CMD_OP_SQD_RTS_QP:
372 case MLX5_CMD_OP_INIT2INIT_QP:
373 case MLX5_CMD_OP_CREATE_PSV:
374 case MLX5_CMD_OP_CREATE_SRQ:
375 case MLX5_CMD_OP_QUERY_SRQ:
376 case MLX5_CMD_OP_ARM_RQ:
377 case MLX5_CMD_OP_CREATE_XRC_SRQ:
378 case MLX5_CMD_OP_QUERY_XRC_SRQ:
379 case MLX5_CMD_OP_ARM_XRC_SRQ:
380 case MLX5_CMD_OP_CREATE_XRQ:
381 case MLX5_CMD_OP_QUERY_XRQ:
382 case MLX5_CMD_OP_ARM_XRQ:
383 case MLX5_CMD_OP_CREATE_DCT:
384 case MLX5_CMD_OP_DRAIN_DCT:
385 case MLX5_CMD_OP_QUERY_DCT:
386 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
387 case MLX5_CMD_OP_QUERY_VPORT_STATE:
388 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
389 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
390 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
391 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
392 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
393 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
394 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
395 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
396 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
397 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
398 case MLX5_CMD_OP_QUERY_VNIC_ENV:
399 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
400 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
401 case MLX5_CMD_OP_QUERY_Q_COUNTER:
402 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
403 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
404 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
405 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
406 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
407 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
408 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
409 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
410 case MLX5_CMD_OP_ALLOC_PD:
411 case MLX5_CMD_OP_ALLOC_UAR:
412 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
413 case MLX5_CMD_OP_ACCESS_REG:
414 case MLX5_CMD_OP_ATTACH_TO_MCG:
415 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
416 case MLX5_CMD_OP_MAD_IFC:
417 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
418 case MLX5_CMD_OP_SET_MAD_DEMUX:
419 case MLX5_CMD_OP_NOP:
420 case MLX5_CMD_OP_ALLOC_XRCD:
421 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
422 case MLX5_CMD_OP_QUERY_CONG_STATUS:
423 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
424 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
425 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
426 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
427 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
428 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
429 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
430 case MLX5_CMD_OP_CREATE_LAG:
431 case MLX5_CMD_OP_MODIFY_LAG:
432 case MLX5_CMD_OP_QUERY_LAG:
433 case MLX5_CMD_OP_CREATE_VPORT_LAG:
434 case MLX5_CMD_OP_CREATE_TIR:
435 case MLX5_CMD_OP_MODIFY_TIR:
436 case MLX5_CMD_OP_QUERY_TIR:
437 case MLX5_CMD_OP_CREATE_SQ:
438 case MLX5_CMD_OP_MODIFY_SQ:
439 case MLX5_CMD_OP_QUERY_SQ:
440 case MLX5_CMD_OP_CREATE_RQ:
441 case MLX5_CMD_OP_MODIFY_RQ:
442 case MLX5_CMD_OP_QUERY_RQ:
443 case MLX5_CMD_OP_CREATE_RMP:
444 case MLX5_CMD_OP_MODIFY_RMP:
445 case MLX5_CMD_OP_QUERY_RMP:
446 case MLX5_CMD_OP_CREATE_TIS:
447 case MLX5_CMD_OP_MODIFY_TIS:
448 case MLX5_CMD_OP_QUERY_TIS:
449 case MLX5_CMD_OP_CREATE_RQT:
450 case MLX5_CMD_OP_QUERY_RQT:
451
452 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
453 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
454 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
455 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
456 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
457 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
458 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
459 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
460 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
461 case MLX5_CMD_OP_FPGA_CREATE_QP:
462 case MLX5_CMD_OP_FPGA_MODIFY_QP:
463 case MLX5_CMD_OP_FPGA_QUERY_QP:
464 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
465 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
466 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
467 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
468 case MLX5_CMD_OP_CREATE_UCTX:
469 case MLX5_CMD_OP_CREATE_UMEM:
470 case MLX5_CMD_OP_ALLOC_MEMIC:
471 case MLX5_CMD_OP_MODIFY_XRQ:
472 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
473 case MLX5_CMD_OP_QUERY_VHCA_STATE:
474 case MLX5_CMD_OP_MODIFY_VHCA_STATE:
475 case MLX5_CMD_OP_ALLOC_SF:
476 *status = MLX5_DRIVER_STATUS_ABORTED;
477 *synd = MLX5_DRIVER_SYND;
478 return -EIO;
479 default:
480 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
481 return -EINVAL;
482 }
483 }
484
mlx5_command_str(int command)485 const char *mlx5_command_str(int command)
486 {
487 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
488
489 switch (command) {
490 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
491 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
492 MLX5_COMMAND_STR_CASE(INIT_HCA);
493 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
494 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
495 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
496 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
497 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
498 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
499 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
500 MLX5_COMMAND_STR_CASE(SET_ISSI);
501 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
502 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
503 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
504 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
505 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
506 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
507 MLX5_COMMAND_STR_CASE(CREATE_EQ);
508 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
509 MLX5_COMMAND_STR_CASE(QUERY_EQ);
510 MLX5_COMMAND_STR_CASE(GEN_EQE);
511 MLX5_COMMAND_STR_CASE(CREATE_CQ);
512 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
513 MLX5_COMMAND_STR_CASE(QUERY_CQ);
514 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
515 MLX5_COMMAND_STR_CASE(CREATE_QP);
516 MLX5_COMMAND_STR_CASE(DESTROY_QP);
517 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
518 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
519 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
520 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
521 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
522 MLX5_COMMAND_STR_CASE(2ERR_QP);
523 MLX5_COMMAND_STR_CASE(2RST_QP);
524 MLX5_COMMAND_STR_CASE(QUERY_QP);
525 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
526 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
527 MLX5_COMMAND_STR_CASE(CREATE_PSV);
528 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
529 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
530 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
531 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
532 MLX5_COMMAND_STR_CASE(ARM_RQ);
533 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
534 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
535 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
536 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
537 MLX5_COMMAND_STR_CASE(CREATE_DCT);
538 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
539 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
540 MLX5_COMMAND_STR_CASE(QUERY_DCT);
541 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
542 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
543 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
544 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
545 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
546 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
547 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
548 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
549 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
550 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
551 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
552 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
553 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
554 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
555 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
556 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
557 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
558 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
559 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
560 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
561 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
562 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
563 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
564 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
565 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
566 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
567 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
568 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
569 MLX5_COMMAND_STR_CASE(ALLOC_PD);
570 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
571 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
572 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
573 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
574 MLX5_COMMAND_STR_CASE(ACCESS_REG);
575 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
576 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
577 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
578 MLX5_COMMAND_STR_CASE(MAD_IFC);
579 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
580 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
581 MLX5_COMMAND_STR_CASE(NOP);
582 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
583 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
584 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
585 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
586 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
587 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
588 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
589 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
590 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
591 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
592 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
593 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
594 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
595 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
596 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
597 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
598 MLX5_COMMAND_STR_CASE(CREATE_LAG);
599 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
600 MLX5_COMMAND_STR_CASE(QUERY_LAG);
601 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
602 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
603 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
604 MLX5_COMMAND_STR_CASE(CREATE_TIR);
605 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
606 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
607 MLX5_COMMAND_STR_CASE(QUERY_TIR);
608 MLX5_COMMAND_STR_CASE(CREATE_SQ);
609 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
610 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
611 MLX5_COMMAND_STR_CASE(QUERY_SQ);
612 MLX5_COMMAND_STR_CASE(CREATE_RQ);
613 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
614 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
615 MLX5_COMMAND_STR_CASE(QUERY_RQ);
616 MLX5_COMMAND_STR_CASE(CREATE_RMP);
617 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
618 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
619 MLX5_COMMAND_STR_CASE(QUERY_RMP);
620 MLX5_COMMAND_STR_CASE(CREATE_TIS);
621 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
622 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
623 MLX5_COMMAND_STR_CASE(QUERY_TIS);
624 MLX5_COMMAND_STR_CASE(CREATE_RQT);
625 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
626 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
627 MLX5_COMMAND_STR_CASE(QUERY_RQT);
628 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
629 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
630 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
631 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
632 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
633 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
634 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
635 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
636 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
637 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
638 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
639 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
640 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
641 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
642 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
643 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
644 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
645 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
646 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
647 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
648 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
649 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
650 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
651 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
652 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
653 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
654 MLX5_COMMAND_STR_CASE(ARM_XRQ);
655 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
656 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
657 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
658 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
659 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
660 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
661 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
662 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
663 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
664 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
665 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
666 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
667 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
668 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
669 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE);
670 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE);
671 MLX5_COMMAND_STR_CASE(ALLOC_SF);
672 MLX5_COMMAND_STR_CASE(DEALLOC_SF);
673 default: return "unknown command opcode";
674 }
675 }
676
cmd_status_str(u8 status)677 static const char *cmd_status_str(u8 status)
678 {
679 switch (status) {
680 case MLX5_CMD_STAT_OK:
681 return "OK";
682 case MLX5_CMD_STAT_INT_ERR:
683 return "internal error";
684 case MLX5_CMD_STAT_BAD_OP_ERR:
685 return "bad operation";
686 case MLX5_CMD_STAT_BAD_PARAM_ERR:
687 return "bad parameter";
688 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
689 return "bad system state";
690 case MLX5_CMD_STAT_BAD_RES_ERR:
691 return "bad resource";
692 case MLX5_CMD_STAT_RES_BUSY:
693 return "resource busy";
694 case MLX5_CMD_STAT_LIM_ERR:
695 return "limits exceeded";
696 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
697 return "bad resource state";
698 case MLX5_CMD_STAT_IX_ERR:
699 return "bad index";
700 case MLX5_CMD_STAT_NO_RES_ERR:
701 return "no resources";
702 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
703 return "bad input length";
704 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
705 return "bad output length";
706 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
707 return "bad QP state";
708 case MLX5_CMD_STAT_BAD_PKT_ERR:
709 return "bad packet (discarded)";
710 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
711 return "bad size too many outstanding CQEs";
712 default:
713 return "unknown status";
714 }
715 }
716
cmd_status_to_err(u8 status)717 static int cmd_status_to_err(u8 status)
718 {
719 switch (status) {
720 case MLX5_CMD_STAT_OK: return 0;
721 case MLX5_CMD_STAT_INT_ERR: return -EIO;
722 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
723 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
724 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
725 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
726 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
727 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
728 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
729 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
730 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
731 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
732 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
733 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
734 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
735 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
736 default: return -EIO;
737 }
738 }
739
740 struct mlx5_ifc_mbox_out_bits {
741 u8 status[0x8];
742 u8 reserved_at_8[0x18];
743
744 u8 syndrome[0x20];
745
746 u8 reserved_at_40[0x40];
747 };
748
749 struct mlx5_ifc_mbox_in_bits {
750 u8 opcode[0x10];
751 u8 uid[0x10];
752
753 u8 reserved_at_20[0x10];
754 u8 op_mod[0x10];
755
756 u8 reserved_at_40[0x40];
757 };
758
mlx5_cmd_mbox_status(void * out,u8 * status,u32 * syndrome)759 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
760 {
761 *status = MLX5_GET(mbox_out, out, status);
762 *syndrome = MLX5_GET(mbox_out, out, syndrome);
763 }
764
mlx5_cmd_check(struct mlx5_core_dev * dev,void * in,void * out)765 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
766 {
767 u32 syndrome;
768 u8 status;
769 u16 opcode;
770 u16 op_mod;
771 u16 uid;
772
773 mlx5_cmd_mbox_status(out, &status, &syndrome);
774 if (!status)
775 return 0;
776
777 opcode = MLX5_GET(mbox_in, in, opcode);
778 op_mod = MLX5_GET(mbox_in, in, op_mod);
779 uid = MLX5_GET(mbox_in, in, uid);
780
781 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
782 mlx5_core_err_rl(dev,
783 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
784 mlx5_command_str(opcode), opcode, op_mod,
785 cmd_status_str(status), status, syndrome);
786 else
787 mlx5_core_dbg(dev,
788 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
789 mlx5_command_str(opcode),
790 opcode, op_mod,
791 cmd_status_str(status),
792 status,
793 syndrome);
794
795 return cmd_status_to_err(status);
796 }
797
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)798 static void dump_command(struct mlx5_core_dev *dev,
799 struct mlx5_cmd_work_ent *ent, int input)
800 {
801 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
802 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
803 struct mlx5_cmd_mailbox *next = msg->next;
804 int n = mlx5_calc_cmd_blocks(msg);
805 int data_only;
806 u32 offset = 0;
807 int dump_len;
808 int i;
809
810 mlx5_core_dbg(dev, "cmd[%d]: start dump\n", ent->idx);
811 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
812
813 if (data_only)
814 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
815 "cmd[%d]: dump command data %s(0x%x) %s\n",
816 ent->idx, mlx5_command_str(op), op,
817 input ? "INPUT" : "OUTPUT");
818 else
819 mlx5_core_dbg(dev, "cmd[%d]: dump command %s(0x%x) %s\n",
820 ent->idx, mlx5_command_str(op), op,
821 input ? "INPUT" : "OUTPUT");
822
823 if (data_only) {
824 if (input) {
825 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset, ent->idx);
826 offset += sizeof(ent->lay->in);
827 } else {
828 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset, ent->idx);
829 offset += sizeof(ent->lay->out);
830 }
831 } else {
832 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset, ent->idx);
833 offset += sizeof(*ent->lay);
834 }
835
836 for (i = 0; i < n && next; i++) {
837 if (data_only) {
838 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
839 dump_buf(next->buf, dump_len, 1, offset, ent->idx);
840 offset += MLX5_CMD_DATA_BLOCK_SIZE;
841 } else {
842 mlx5_core_dbg(dev, "cmd[%d]: command block:\n", ent->idx);
843 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset,
844 ent->idx);
845 offset += sizeof(struct mlx5_cmd_prot_block);
846 }
847 next = next->next;
848 }
849
850 if (data_only)
851 pr_debug("\n");
852
853 mlx5_core_dbg(dev, "cmd[%d]: end dump\n", ent->idx);
854 }
855
msg_to_opcode(struct mlx5_cmd_msg * in)856 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
857 {
858 return MLX5_GET(mbox_in, in->first.data, opcode);
859 }
860
861 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
862
cb_timeout_handler(struct work_struct * work)863 static void cb_timeout_handler(struct work_struct *work)
864 {
865 struct delayed_work *dwork = container_of(work, struct delayed_work,
866 work);
867 struct mlx5_cmd_work_ent *ent = container_of(dwork,
868 struct mlx5_cmd_work_ent,
869 cb_timeout_work);
870 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
871 cmd);
872
873 mlx5_cmd_eq_recover(dev);
874
875 /* Maybe got handled by eq recover ? */
876 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
877 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
878 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
879 goto out; /* phew, already handled */
880 }
881
882 ent->ret = -ETIMEDOUT;
883 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
884 ent->idx, mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
885 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
886
887 out:
888 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
889 }
890
891 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
892 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
893 struct mlx5_cmd_msg *msg);
894
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)895 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
896 {
897 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
898 return true;
899
900 return cmd->allowed_opcode == opcode;
901 }
902
mlx5_cmd_is_down(struct mlx5_core_dev * dev)903 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
904 {
905 return pci_channel_offline(dev->pdev) ||
906 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
907 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
908 }
909
cmd_work_handler(struct work_struct * work)910 static void cmd_work_handler(struct work_struct *work)
911 {
912 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
913 struct mlx5_cmd *cmd = ent->cmd;
914 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
915 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
916 struct mlx5_cmd_layout *lay;
917 struct semaphore *sem;
918 unsigned long flags;
919 bool poll_cmd = ent->polling;
920 int alloc_ret;
921 int cmd_mode;
922
923 complete(&ent->handling);
924 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
925 down(sem);
926 if (!ent->page_queue) {
927 alloc_ret = cmd_alloc_index(cmd);
928 if (alloc_ret < 0) {
929 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
930 if (ent->callback) {
931 ent->callback(-EAGAIN, ent->context);
932 mlx5_free_cmd_msg(dev, ent->out);
933 free_msg(dev, ent->in);
934 cmd_ent_put(ent);
935 } else {
936 ent->ret = -EAGAIN;
937 complete(&ent->done);
938 }
939 up(sem);
940 return;
941 }
942 ent->idx = alloc_ret;
943 } else {
944 ent->idx = cmd->max_reg_cmds;
945 spin_lock_irqsave(&cmd->alloc_lock, flags);
946 clear_bit(ent->idx, &cmd->bitmask);
947 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
948 }
949
950 cmd->ent_arr[ent->idx] = ent;
951 lay = get_inst(cmd, ent->idx);
952 ent->lay = lay;
953 memset(lay, 0, sizeof(*lay));
954 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
955 ent->op = be32_to_cpu(lay->in[0]) >> 16;
956 if (ent->in->next)
957 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
958 lay->inlen = cpu_to_be32(ent->in->len);
959 if (ent->out->next)
960 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
961 lay->outlen = cpu_to_be32(ent->out->len);
962 lay->type = MLX5_PCI_CMD_XPORT;
963 lay->token = ent->token;
964 lay->status_own = CMD_OWNER_HW;
965 set_signature(ent, !cmd->checksum_disabled);
966 dump_command(dev, ent, 1);
967 ent->ts1 = ktime_get_ns();
968 cmd_mode = cmd->mode;
969
970 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, cb_timeout))
971 cmd_ent_get(ent);
972 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
973
974 cmd_ent_get(ent); /* for the _real_ FW event on completion */
975 /* Skip sending command to fw if internal error */
976 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
977 u8 status = 0;
978 u32 drv_synd;
979
980 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
981 MLX5_SET(mbox_out, ent->out, status, status);
982 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
983
984 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
985 return;
986 }
987
988 /* ring doorbell after the descriptor is valid */
989 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
990 wmb();
991 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
992 /* if not in polling don't use ent after this point */
993 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
994 poll_timeout(ent);
995 /* make sure we read the descriptor after ownership is SW */
996 rmb();
997 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
998 }
999 }
1000
deliv_status_to_str(u8 status)1001 static const char *deliv_status_to_str(u8 status)
1002 {
1003 switch (status) {
1004 case MLX5_CMD_DELIVERY_STAT_OK:
1005 return "no errors";
1006 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1007 return "signature error";
1008 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1009 return "token error";
1010 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1011 return "bad block number";
1012 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1013 return "output pointer not aligned to block size";
1014 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1015 return "input pointer not aligned to block size";
1016 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1017 return "firmware internal error";
1018 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1019 return "command input length error";
1020 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1021 return "command output length error";
1022 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1023 return "reserved fields not cleared";
1024 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1025 return "bad command descriptor type";
1026 default:
1027 return "unknown status code";
1028 }
1029 }
1030
1031 enum {
1032 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1033 };
1034
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1035 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1036 struct mlx5_cmd_work_ent *ent)
1037 {
1038 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1039
1040 mlx5_cmd_eq_recover(dev);
1041
1042 /* Re-wait on the ent->done after executing the recovery flow. If the
1043 * recovery flow (or any other recovery flow running simultaneously)
1044 * has recovered an EQE, it should cause the entry to be completed by
1045 * the command interface.
1046 */
1047 if (wait_for_completion_timeout(&ent->done, timeout)) {
1048 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1049 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1050 return;
1051 }
1052
1053 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1054 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1055
1056 ent->ret = -ETIMEDOUT;
1057 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1058 }
1059
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1060 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1061 {
1062 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
1063 struct mlx5_cmd *cmd = &dev->cmd;
1064 int err;
1065
1066 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1067 cancel_work_sync(&ent->work)) {
1068 ent->ret = -ECANCELED;
1069 goto out_err;
1070 }
1071 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1072 wait_for_completion(&ent->done);
1073 else if (!wait_for_completion_timeout(&ent->done, timeout))
1074 wait_func_handle_exec_timeout(dev, ent);
1075
1076 out_err:
1077 err = ent->ret;
1078
1079 if (err == -ETIMEDOUT) {
1080 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1081 mlx5_command_str(msg_to_opcode(ent->in)),
1082 msg_to_opcode(ent->in));
1083 } else if (err == -ECANCELED) {
1084 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1085 mlx5_command_str(msg_to_opcode(ent->in)),
1086 msg_to_opcode(ent->in));
1087 }
1088 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1089 err, deliv_status_to_str(ent->status), ent->status);
1090
1091 return err;
1092 }
1093
1094 /* Notes:
1095 * 1. Callback functions may not sleep
1096 * 2. page queue commands do not support asynchrous completion
1097 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 * status,u8 token,bool force_polling)1098 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1099 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1100 mlx5_cmd_cbk_t callback,
1101 void *context, int page_queue, u8 *status,
1102 u8 token, bool force_polling)
1103 {
1104 struct mlx5_cmd *cmd = &dev->cmd;
1105 struct mlx5_cmd_work_ent *ent;
1106 struct mlx5_cmd_stats *stats;
1107 int err = 0;
1108 s64 ds;
1109 u16 op;
1110
1111 if (callback && page_queue)
1112 return -EINVAL;
1113
1114 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1115 callback, context, page_queue);
1116 if (IS_ERR(ent))
1117 return PTR_ERR(ent);
1118
1119 /* put for this ent is when consumed, depending on the use case
1120 * 1) (!callback) blocking flow: by caller after wait_func completes
1121 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1122 */
1123
1124 ent->token = token;
1125 ent->polling = force_polling;
1126
1127 init_completion(&ent->handling);
1128 if (!callback)
1129 init_completion(&ent->done);
1130
1131 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1132 INIT_WORK(&ent->work, cmd_work_handler);
1133 if (page_queue) {
1134 cmd_work_handler(&ent->work);
1135 } else if (!queue_work(cmd->wq, &ent->work)) {
1136 mlx5_core_warn(dev, "failed to queue work\n");
1137 err = -ENOMEM;
1138 goto out_free;
1139 }
1140
1141 if (callback)
1142 goto out; /* mlx5_cmd_comp_handler() will put(ent) */
1143
1144 err = wait_func(dev, ent);
1145 if (err == -ETIMEDOUT || err == -ECANCELED)
1146 goto out_free;
1147
1148 ds = ent->ts2 - ent->ts1;
1149 op = MLX5_GET(mbox_in, in->first.data, opcode);
1150 if (op < MLX5_CMD_OP_MAX) {
1151 stats = &cmd->stats[op];
1152 spin_lock_irq(&stats->lock);
1153 stats->sum += ds;
1154 ++stats->n;
1155 spin_unlock_irq(&stats->lock);
1156 }
1157 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1158 "fw exec time for %s is %lld nsec\n",
1159 mlx5_command_str(op), ds);
1160 *status = ent->status;
1161
1162 out_free:
1163 cmd_ent_put(ent);
1164 out:
1165 return err;
1166 }
1167
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1168 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1169 size_t count, loff_t *pos)
1170 {
1171 struct mlx5_core_dev *dev = filp->private_data;
1172 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1173 char lbuf[3];
1174 int err;
1175
1176 if (!dbg->in_msg || !dbg->out_msg)
1177 return -ENOMEM;
1178
1179 if (count < sizeof(lbuf) - 1)
1180 return -EINVAL;
1181
1182 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1183 return -EFAULT;
1184
1185 lbuf[sizeof(lbuf) - 1] = 0;
1186
1187 if (strcmp(lbuf, "go"))
1188 return -EINVAL;
1189
1190 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1191
1192 return err ? err : count;
1193 }
1194
1195 static const struct file_operations fops = {
1196 .owner = THIS_MODULE,
1197 .open = simple_open,
1198 .write = dbg_write,
1199 };
1200
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1201 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1202 u8 token)
1203 {
1204 struct mlx5_cmd_prot_block *block;
1205 struct mlx5_cmd_mailbox *next;
1206 int copy;
1207
1208 if (!to || !from)
1209 return -ENOMEM;
1210
1211 copy = min_t(int, size, sizeof(to->first.data));
1212 memcpy(to->first.data, from, copy);
1213 size -= copy;
1214 from += copy;
1215
1216 next = to->next;
1217 while (size) {
1218 if (!next) {
1219 /* this is a BUG */
1220 return -ENOMEM;
1221 }
1222
1223 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1224 block = next->buf;
1225 memcpy(block->data, from, copy);
1226 from += copy;
1227 size -= copy;
1228 block->token = token;
1229 next = next->next;
1230 }
1231
1232 return 0;
1233 }
1234
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1235 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1236 {
1237 struct mlx5_cmd_prot_block *block;
1238 struct mlx5_cmd_mailbox *next;
1239 int copy;
1240
1241 if (!to || !from)
1242 return -ENOMEM;
1243
1244 copy = min_t(int, size, sizeof(from->first.data));
1245 memcpy(to, from->first.data, copy);
1246 size -= copy;
1247 to += copy;
1248
1249 next = from->next;
1250 while (size) {
1251 if (!next) {
1252 /* this is a BUG */
1253 return -ENOMEM;
1254 }
1255
1256 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1257 block = next->buf;
1258
1259 memcpy(to, block->data, copy);
1260 to += copy;
1261 size -= copy;
1262 next = next->next;
1263 }
1264
1265 return 0;
1266 }
1267
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1268 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1269 gfp_t flags)
1270 {
1271 struct mlx5_cmd_mailbox *mailbox;
1272
1273 mailbox = kmalloc(sizeof(*mailbox), flags);
1274 if (!mailbox)
1275 return ERR_PTR(-ENOMEM);
1276
1277 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1278 &mailbox->dma);
1279 if (!mailbox->buf) {
1280 mlx5_core_dbg(dev, "failed allocation\n");
1281 kfree(mailbox);
1282 return ERR_PTR(-ENOMEM);
1283 }
1284 mailbox->next = NULL;
1285
1286 return mailbox;
1287 }
1288
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1289 static void free_cmd_box(struct mlx5_core_dev *dev,
1290 struct mlx5_cmd_mailbox *mailbox)
1291 {
1292 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1293 kfree(mailbox);
1294 }
1295
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1296 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1297 gfp_t flags, int size,
1298 u8 token)
1299 {
1300 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1301 struct mlx5_cmd_prot_block *block;
1302 struct mlx5_cmd_msg *msg;
1303 int err;
1304 int n;
1305 int i;
1306
1307 msg = kzalloc(sizeof(*msg), flags);
1308 if (!msg)
1309 return ERR_PTR(-ENOMEM);
1310
1311 msg->len = size;
1312 n = mlx5_calc_cmd_blocks(msg);
1313
1314 for (i = 0; i < n; i++) {
1315 tmp = alloc_cmd_box(dev, flags);
1316 if (IS_ERR(tmp)) {
1317 mlx5_core_warn(dev, "failed allocating block\n");
1318 err = PTR_ERR(tmp);
1319 goto err_alloc;
1320 }
1321
1322 block = tmp->buf;
1323 tmp->next = head;
1324 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1325 block->block_num = cpu_to_be32(n - i - 1);
1326 block->token = token;
1327 head = tmp;
1328 }
1329 msg->next = head;
1330 return msg;
1331
1332 err_alloc:
1333 while (head) {
1334 tmp = head->next;
1335 free_cmd_box(dev, head);
1336 head = tmp;
1337 }
1338 kfree(msg);
1339
1340 return ERR_PTR(err);
1341 }
1342
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1343 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1344 struct mlx5_cmd_msg *msg)
1345 {
1346 struct mlx5_cmd_mailbox *head = msg->next;
1347 struct mlx5_cmd_mailbox *next;
1348
1349 while (head) {
1350 next = head->next;
1351 free_cmd_box(dev, head);
1352 head = next;
1353 }
1354 kfree(msg);
1355 }
1356
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1357 static ssize_t data_write(struct file *filp, const char __user *buf,
1358 size_t count, loff_t *pos)
1359 {
1360 struct mlx5_core_dev *dev = filp->private_data;
1361 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1362 void *ptr;
1363
1364 if (*pos != 0)
1365 return -EINVAL;
1366
1367 kfree(dbg->in_msg);
1368 dbg->in_msg = NULL;
1369 dbg->inlen = 0;
1370 ptr = memdup_user(buf, count);
1371 if (IS_ERR(ptr))
1372 return PTR_ERR(ptr);
1373 dbg->in_msg = ptr;
1374 dbg->inlen = count;
1375
1376 *pos = count;
1377
1378 return count;
1379 }
1380
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1381 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1382 loff_t *pos)
1383 {
1384 struct mlx5_core_dev *dev = filp->private_data;
1385 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1386
1387 if (!dbg->out_msg)
1388 return -ENOMEM;
1389
1390 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1391 dbg->outlen);
1392 }
1393
1394 static const struct file_operations dfops = {
1395 .owner = THIS_MODULE,
1396 .open = simple_open,
1397 .write = data_write,
1398 .read = data_read,
1399 };
1400
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1401 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1402 loff_t *pos)
1403 {
1404 struct mlx5_core_dev *dev = filp->private_data;
1405 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1406 char outlen[8];
1407 int err;
1408
1409 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1410 if (err < 0)
1411 return err;
1412
1413 return simple_read_from_buffer(buf, count, pos, outlen, err);
1414 }
1415
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1416 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1417 size_t count, loff_t *pos)
1418 {
1419 struct mlx5_core_dev *dev = filp->private_data;
1420 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1421 char outlen_str[8] = {0};
1422 int outlen;
1423 void *ptr;
1424 int err;
1425
1426 if (*pos != 0 || count > 6)
1427 return -EINVAL;
1428
1429 kfree(dbg->out_msg);
1430 dbg->out_msg = NULL;
1431 dbg->outlen = 0;
1432
1433 if (copy_from_user(outlen_str, buf, count))
1434 return -EFAULT;
1435
1436 err = sscanf(outlen_str, "%d", &outlen);
1437 if (err != 1)
1438 return -EINVAL;
1439
1440 ptr = kzalloc(outlen, GFP_KERNEL);
1441 if (!ptr)
1442 return -ENOMEM;
1443
1444 dbg->out_msg = ptr;
1445 dbg->outlen = outlen;
1446
1447 *pos = count;
1448
1449 return count;
1450 }
1451
1452 static const struct file_operations olfops = {
1453 .owner = THIS_MODULE,
1454 .open = simple_open,
1455 .write = outlen_write,
1456 .read = outlen_read,
1457 };
1458
set_wqname(struct mlx5_core_dev * dev)1459 static void set_wqname(struct mlx5_core_dev *dev)
1460 {
1461 struct mlx5_cmd *cmd = &dev->cmd;
1462
1463 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1464 dev_name(dev->device));
1465 }
1466
clean_debug_files(struct mlx5_core_dev * dev)1467 static void clean_debug_files(struct mlx5_core_dev *dev)
1468 {
1469 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1470
1471 if (!mlx5_debugfs_root)
1472 return;
1473
1474 mlx5_cmdif_debugfs_cleanup(dev);
1475 debugfs_remove_recursive(dbg->dbg_root);
1476 }
1477
create_debugfs_files(struct mlx5_core_dev * dev)1478 static void create_debugfs_files(struct mlx5_core_dev *dev)
1479 {
1480 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1481
1482 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1483
1484 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1485 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1486 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1487 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1488 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1489
1490 mlx5_cmdif_debugfs_init(dev);
1491 }
1492
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1493 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1494 {
1495 struct mlx5_cmd *cmd = &dev->cmd;
1496 int i;
1497
1498 for (i = 0; i < cmd->max_reg_cmds; i++)
1499 down(&cmd->sem);
1500 down(&cmd->pages_sem);
1501
1502 cmd->allowed_opcode = opcode;
1503
1504 up(&cmd->pages_sem);
1505 for (i = 0; i < cmd->max_reg_cmds; i++)
1506 up(&cmd->sem);
1507 }
1508
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1509 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1510 {
1511 struct mlx5_cmd *cmd = &dev->cmd;
1512 int i;
1513
1514 for (i = 0; i < cmd->max_reg_cmds; i++)
1515 down(&cmd->sem);
1516 down(&cmd->pages_sem);
1517
1518 cmd->mode = mode;
1519
1520 up(&cmd->pages_sem);
1521 for (i = 0; i < cmd->max_reg_cmds; i++)
1522 up(&cmd->sem);
1523 }
1524
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1525 static int cmd_comp_notifier(struct notifier_block *nb,
1526 unsigned long type, void *data)
1527 {
1528 struct mlx5_core_dev *dev;
1529 struct mlx5_cmd *cmd;
1530 struct mlx5_eqe *eqe;
1531
1532 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1533 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1534 eqe = data;
1535
1536 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1537
1538 return NOTIFY_OK;
1539 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1540 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1541 {
1542 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1543 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1544 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1545 }
1546
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1547 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1548 {
1549 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1550 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1551 }
1552
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1553 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1554 {
1555 unsigned long flags;
1556
1557 if (msg->parent) {
1558 spin_lock_irqsave(&msg->parent->lock, flags);
1559 list_add_tail(&msg->list, &msg->parent->head);
1560 spin_unlock_irqrestore(&msg->parent->lock, flags);
1561 } else {
1562 mlx5_free_cmd_msg(dev, msg);
1563 }
1564 }
1565
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1566 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1567 {
1568 struct mlx5_cmd *cmd = &dev->cmd;
1569 struct mlx5_cmd_work_ent *ent;
1570 mlx5_cmd_cbk_t callback;
1571 void *context;
1572 int err;
1573 int i;
1574 s64 ds;
1575 struct mlx5_cmd_stats *stats;
1576 unsigned long flags;
1577 unsigned long vector;
1578
1579 /* there can be at most 32 command queues */
1580 vector = vec & 0xffffffff;
1581 for (i = 0; i < (1 << cmd->log_sz); i++) {
1582 if (test_bit(i, &vector)) {
1583 ent = cmd->ent_arr[i];
1584
1585 /* if we already completed the command, ignore it */
1586 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1587 &ent->state)) {
1588 /* only real completion can free the cmd slot */
1589 if (!forced) {
1590 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1591 ent->idx);
1592 cmd_ent_put(ent);
1593 }
1594 continue;
1595 }
1596
1597 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1598 cmd_ent_put(ent); /* timeout work was canceled */
1599
1600 if (!forced || /* Real FW completion */
1601 mlx5_cmd_is_down(dev) || /* No real FW completion is expected */
1602 !opcode_allowed(cmd, ent->op))
1603 cmd_ent_put(ent);
1604
1605 ent->ts2 = ktime_get_ns();
1606 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1607 dump_command(dev, ent, 0);
1608 if (!ent->ret) {
1609 if (!cmd->checksum_disabled)
1610 ent->ret = verify_signature(ent);
1611 else
1612 ent->ret = 0;
1613 if (vec & MLX5_TRIGGERED_CMD_COMP)
1614 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1615 else
1616 ent->status = ent->lay->status_own >> 1;
1617
1618 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1619 ent->ret, deliv_status_to_str(ent->status), ent->status);
1620 }
1621
1622 if (ent->callback) {
1623 ds = ent->ts2 - ent->ts1;
1624 if (ent->op < MLX5_CMD_OP_MAX) {
1625 stats = &cmd->stats[ent->op];
1626 spin_lock_irqsave(&stats->lock, flags);
1627 stats->sum += ds;
1628 ++stats->n;
1629 spin_unlock_irqrestore(&stats->lock, flags);
1630 }
1631
1632 callback = ent->callback;
1633 context = ent->context;
1634 err = ent->ret;
1635 if (!err) {
1636 err = mlx5_copy_from_msg(ent->uout,
1637 ent->out,
1638 ent->uout_size);
1639
1640 err = err ? err : mlx5_cmd_check(dev,
1641 ent->in->first.data,
1642 ent->uout);
1643 }
1644
1645 mlx5_free_cmd_msg(dev, ent->out);
1646 free_msg(dev, ent->in);
1647
1648 err = err ? err : ent->status;
1649 /* final consumer is done, release ent */
1650 cmd_ent_put(ent);
1651 callback(err, context);
1652 } else {
1653 /* release wait_func() so mlx5_cmd_invoke()
1654 * can make the final ent_put()
1655 */
1656 complete(&ent->done);
1657 }
1658 }
1659 }
1660 }
1661
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1662 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1663 {
1664 struct mlx5_cmd *cmd = &dev->cmd;
1665 unsigned long bitmask;
1666 unsigned long flags;
1667 u64 vector;
1668 int i;
1669
1670 /* wait for pending handlers to complete */
1671 mlx5_eq_synchronize_cmd_irq(dev);
1672 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1673 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1674 if (!vector)
1675 goto no_trig;
1676
1677 bitmask = vector;
1678 /* we must increment the allocated entries refcount before triggering the completions
1679 * to guarantee pending commands will not get freed in the meanwhile.
1680 * For that reason, it also has to be done inside the alloc_lock.
1681 */
1682 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1683 cmd_ent_get(cmd->ent_arr[i]);
1684 vector |= MLX5_TRIGGERED_CMD_COMP;
1685 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1686
1687 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1688 mlx5_cmd_comp_handler(dev, vector, true);
1689 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1690 cmd_ent_put(cmd->ent_arr[i]);
1691 return;
1692
1693 no_trig:
1694 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1695 }
1696
mlx5_cmd_flush(struct mlx5_core_dev * dev)1697 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1698 {
1699 struct mlx5_cmd *cmd = &dev->cmd;
1700 int i;
1701
1702 for (i = 0; i < cmd->max_reg_cmds; i++) {
1703 while (down_trylock(&cmd->sem)) {
1704 mlx5_cmd_trigger_completions(dev);
1705 cond_resched();
1706 }
1707 }
1708
1709 while (down_trylock(&cmd->pages_sem)) {
1710 mlx5_cmd_trigger_completions(dev);
1711 cond_resched();
1712 }
1713
1714 /* Unlock cmdif */
1715 up(&cmd->pages_sem);
1716 for (i = 0; i < cmd->max_reg_cmds; i++)
1717 up(&cmd->sem);
1718 }
1719
status_to_err(u8 status)1720 static int status_to_err(u8 status)
1721 {
1722 switch (status) {
1723 case MLX5_CMD_DELIVERY_STAT_OK:
1724 case MLX5_DRIVER_STATUS_ABORTED:
1725 return 0;
1726 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1727 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1728 return -EBADR;
1729 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1730 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1731 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1732 return -EFAULT; /* Bad address */
1733 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1734 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1735 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1736 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1737 return -ENOMSG;
1738 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1739 return -EIO;
1740 default:
1741 return -EINVAL;
1742 }
1743 }
1744
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1745 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1746 gfp_t gfp)
1747 {
1748 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1749 struct cmd_msg_cache *ch = NULL;
1750 struct mlx5_cmd *cmd = &dev->cmd;
1751 int i;
1752
1753 if (in_size <= 16)
1754 goto cache_miss;
1755
1756 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1757 ch = &cmd->cache[i];
1758 if (in_size > ch->max_inbox_size)
1759 continue;
1760 spin_lock_irq(&ch->lock);
1761 if (list_empty(&ch->head)) {
1762 spin_unlock_irq(&ch->lock);
1763 continue;
1764 }
1765 msg = list_entry(ch->head.next, typeof(*msg), list);
1766 /* For cached lists, we must explicitly state what is
1767 * the real size
1768 */
1769 msg->len = in_size;
1770 list_del(&msg->list);
1771 spin_unlock_irq(&ch->lock);
1772 break;
1773 }
1774
1775 if (!IS_ERR(msg))
1776 return msg;
1777
1778 cache_miss:
1779 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1780 return msg;
1781 }
1782
is_manage_pages(void * in)1783 static int is_manage_pages(void *in)
1784 {
1785 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1786 }
1787
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1788 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1789 int out_size, mlx5_cmd_cbk_t callback, void *context,
1790 bool force_polling)
1791 {
1792 struct mlx5_cmd_msg *inb;
1793 struct mlx5_cmd_msg *outb;
1794 int pages_queue;
1795 gfp_t gfp;
1796 int err;
1797 u8 status = 0;
1798 u32 drv_synd;
1799 u16 opcode;
1800 u8 token;
1801
1802 opcode = MLX5_GET(mbox_in, in, opcode);
1803 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode)) {
1804 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1805 MLX5_SET(mbox_out, out, status, status);
1806 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1807 return err;
1808 }
1809
1810 pages_queue = is_manage_pages(in);
1811 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1812
1813 inb = alloc_msg(dev, in_size, gfp);
1814 if (IS_ERR(inb)) {
1815 err = PTR_ERR(inb);
1816 return err;
1817 }
1818
1819 token = alloc_token(&dev->cmd);
1820
1821 err = mlx5_copy_to_msg(inb, in, in_size, token);
1822 if (err) {
1823 mlx5_core_warn(dev, "err %d\n", err);
1824 goto out_in;
1825 }
1826
1827 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1828 if (IS_ERR(outb)) {
1829 err = PTR_ERR(outb);
1830 goto out_in;
1831 }
1832
1833 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1834 pages_queue, &status, token, force_polling);
1835 if (err)
1836 goto out_out;
1837
1838 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1839 if (status) {
1840 err = status_to_err(status);
1841 goto out_out;
1842 }
1843
1844 if (!callback)
1845 err = mlx5_copy_from_msg(out, outb, out_size);
1846
1847 out_out:
1848 if (!callback)
1849 mlx5_free_cmd_msg(dev, outb);
1850
1851 out_in:
1852 if (!callback)
1853 free_msg(dev, inb);
1854 return err;
1855 }
1856
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1857 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1858 int out_size)
1859 {
1860 int err;
1861
1862 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1863 return err ? : mlx5_cmd_check(dev, in, out);
1864 }
1865 EXPORT_SYMBOL(mlx5_cmd_exec);
1866
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)1867 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1868 struct mlx5_async_ctx *ctx)
1869 {
1870 ctx->dev = dev;
1871 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1872 atomic_set(&ctx->num_inflight, 1);
1873 init_completion(&ctx->inflight_done);
1874 }
1875 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1876
1877 /**
1878 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1879 * @ctx: The ctx to clean
1880 *
1881 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1882 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1883 * the call mlx5_cleanup_async_ctx().
1884 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)1885 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1886 {
1887 if (!atomic_dec_and_test(&ctx->num_inflight))
1888 wait_for_completion(&ctx->inflight_done);
1889 }
1890 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1891
mlx5_cmd_exec_cb_handler(int status,void * _work)1892 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1893 {
1894 struct mlx5_async_work *work = _work;
1895 struct mlx5_async_ctx *ctx = work->ctx;
1896
1897 work->user_callback(status, work);
1898 if (atomic_dec_and_test(&ctx->num_inflight))
1899 complete(&ctx->inflight_done);
1900 }
1901
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)1902 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1903 void *out, int out_size, mlx5_async_cbk_t callback,
1904 struct mlx5_async_work *work)
1905 {
1906 int ret;
1907
1908 work->ctx = ctx;
1909 work->user_callback = callback;
1910 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1911 return -EIO;
1912 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1913 mlx5_cmd_exec_cb_handler, work, false);
1914 if (ret && atomic_dec_and_test(&ctx->num_inflight))
1915 complete(&ctx->inflight_done);
1916
1917 return ret;
1918 }
1919 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1920
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1921 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1922 void *out, int out_size)
1923 {
1924 int err;
1925
1926 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1927
1928 return err ? : mlx5_cmd_check(dev, in, out);
1929 }
1930 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1931
destroy_msg_cache(struct mlx5_core_dev * dev)1932 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1933 {
1934 struct cmd_msg_cache *ch;
1935 struct mlx5_cmd_msg *msg;
1936 struct mlx5_cmd_msg *n;
1937 int i;
1938
1939 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1940 ch = &dev->cmd.cache[i];
1941 list_for_each_entry_safe(msg, n, &ch->head, list) {
1942 list_del(&msg->list);
1943 mlx5_free_cmd_msg(dev, msg);
1944 }
1945 }
1946 }
1947
1948 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1949 512, 32, 16, 8, 2
1950 };
1951
1952 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1953 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1954 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1955 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1956 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1957 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1958 };
1959
create_msg_cache(struct mlx5_core_dev * dev)1960 static void create_msg_cache(struct mlx5_core_dev *dev)
1961 {
1962 struct mlx5_cmd *cmd = &dev->cmd;
1963 struct cmd_msg_cache *ch;
1964 struct mlx5_cmd_msg *msg;
1965 int i;
1966 int k;
1967
1968 /* Initialize and fill the caches with initial entries */
1969 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1970 ch = &cmd->cache[k];
1971 spin_lock_init(&ch->lock);
1972 INIT_LIST_HEAD(&ch->head);
1973 ch->num_ent = cmd_cache_num_ent[k];
1974 ch->max_inbox_size = cmd_cache_ent_size[k];
1975 for (i = 0; i < ch->num_ent; i++) {
1976 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1977 ch->max_inbox_size, 0);
1978 if (IS_ERR(msg))
1979 break;
1980 msg->parent = ch;
1981 list_add_tail(&msg->list, &ch->head);
1982 }
1983 }
1984 }
1985
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1986 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1987 {
1988 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
1989 &cmd->alloc_dma, GFP_KERNEL);
1990 if (!cmd->cmd_alloc_buf)
1991 return -ENOMEM;
1992
1993 /* make sure it is aligned to 4K */
1994 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1995 cmd->cmd_buf = cmd->cmd_alloc_buf;
1996 cmd->dma = cmd->alloc_dma;
1997 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1998 return 0;
1999 }
2000
2001 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
2002 cmd->alloc_dma);
2003 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
2004 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
2005 &cmd->alloc_dma, GFP_KERNEL);
2006 if (!cmd->cmd_alloc_buf)
2007 return -ENOMEM;
2008
2009 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
2010 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
2011 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2012 return 0;
2013 }
2014
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2015 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2016 {
2017 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2018 cmd->alloc_dma);
2019 }
2020
cmdif_rev(struct mlx5_core_dev * dev)2021 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2022 {
2023 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2024 }
2025
mlx5_cmd_init(struct mlx5_core_dev * dev)2026 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2027 {
2028 int size = sizeof(struct mlx5_cmd_prot_block);
2029 int align = roundup_pow_of_two(size);
2030 struct mlx5_cmd *cmd = &dev->cmd;
2031 u32 cmd_h, cmd_l;
2032 u16 cmd_if_rev;
2033 int err;
2034 int i;
2035
2036 memset(cmd, 0, sizeof(*cmd));
2037 cmd_if_rev = cmdif_rev(dev);
2038 if (cmd_if_rev != CMD_IF_REV) {
2039 mlx5_core_err(dev,
2040 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2041 CMD_IF_REV, cmd_if_rev);
2042 return -EINVAL;
2043 }
2044
2045 cmd->stats = kvzalloc(MLX5_CMD_OP_MAX * sizeof(*cmd->stats), GFP_KERNEL);
2046 if (!cmd->stats)
2047 return -ENOMEM;
2048
2049 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2050 if (!cmd->pool) {
2051 err = -ENOMEM;
2052 goto dma_pool_err;
2053 }
2054
2055 err = alloc_cmd_page(dev, cmd);
2056 if (err)
2057 goto err_free_pool;
2058
2059 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2060 cmd->log_sz = cmd_l >> 4 & 0xf;
2061 cmd->log_stride = cmd_l & 0xf;
2062 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
2063 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2064 1 << cmd->log_sz);
2065 err = -EINVAL;
2066 goto err_free_page;
2067 }
2068
2069 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2070 mlx5_core_err(dev, "command queue size overflow\n");
2071 err = -EINVAL;
2072 goto err_free_page;
2073 }
2074
2075 cmd->state = MLX5_CMDIF_STATE_DOWN;
2076 cmd->checksum_disabled = 1;
2077 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
2078 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
2079
2080 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2081 if (cmd->cmdif_rev > CMD_IF_REV) {
2082 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n",
2083 CMD_IF_REV, cmd->cmdif_rev);
2084 err = -EOPNOTSUPP;
2085 goto err_free_page;
2086 }
2087
2088 spin_lock_init(&cmd->alloc_lock);
2089 spin_lock_init(&cmd->token_lock);
2090 for (i = 0; i < MLX5_CMD_OP_MAX; i++)
2091 spin_lock_init(&cmd->stats[i].lock);
2092
2093 sema_init(&cmd->sem, cmd->max_reg_cmds);
2094 sema_init(&cmd->pages_sem, 1);
2095
2096 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2097 cmd_l = (u32)(cmd->dma);
2098 if (cmd_l & 0xfff) {
2099 mlx5_core_err(dev, "invalid command queue address\n");
2100 err = -ENOMEM;
2101 goto err_free_page;
2102 }
2103
2104 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2105 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2106
2107 /* Make sure firmware sees the complete address before we proceed */
2108 wmb();
2109
2110 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2111
2112 cmd->mode = CMD_MODE_POLLING;
2113 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2114
2115 create_msg_cache(dev);
2116
2117 set_wqname(dev);
2118 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2119 if (!cmd->wq) {
2120 mlx5_core_err(dev, "failed to create command workqueue\n");
2121 err = -ENOMEM;
2122 goto err_cache;
2123 }
2124
2125 create_debugfs_files(dev);
2126
2127 return 0;
2128
2129 err_cache:
2130 destroy_msg_cache(dev);
2131
2132 err_free_page:
2133 free_cmd_page(dev, cmd);
2134
2135 err_free_pool:
2136 dma_pool_destroy(cmd->pool);
2137 dma_pool_err:
2138 kvfree(cmd->stats);
2139 return err;
2140 }
2141
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2142 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2143 {
2144 struct mlx5_cmd *cmd = &dev->cmd;
2145
2146 clean_debug_files(dev);
2147 destroy_workqueue(cmd->wq);
2148 destroy_msg_cache(dev);
2149 free_cmd_page(dev, cmd);
2150 dma_pool_destroy(cmd->pool);
2151 kvfree(cmd->stats);
2152 }
2153
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2154 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2155 enum mlx5_cmdif_state cmdif_state)
2156 {
2157 dev->cmd.state = cmdif_state;
2158 }
2159