1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
73 #include "ecpf.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
76 #include "sf/vhca_event.h"
77 #include "sf/dev/dev.h"
78 #include "sf/sf.h"
79 #include "mlx5_irq.h"
80
81 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
82 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 unsigned int mlx5_core_debug_mask;
86 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
87 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
88
89 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
90 module_param_named(prof_sel, prof_sel, uint, 0444);
91 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
92
93 static u32 sw_owner_id[4];
94
95 enum {
96 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
97 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
98 };
99
100 #define LOG_MAX_SUPPORTED_QPS 0xff
101
102 static struct mlx5_profile profile[] = {
103 [0] = {
104 .mask = 0,
105 },
106 [1] = {
107 .mask = MLX5_PROF_MASK_QP_SIZE,
108 .log_max_qp = 12,
109 },
110 [2] = {
111 .mask = MLX5_PROF_MASK_QP_SIZE |
112 MLX5_PROF_MASK_MR_CACHE,
113 .log_max_qp = LOG_MAX_SUPPORTED_QPS,
114 .mr_cache[0] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[1] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[2] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[3] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[4] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[5] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[6] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[7] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[8] = {
147 .size = 500,
148 .limit = 250
149 },
150 .mr_cache[9] = {
151 .size = 500,
152 .limit = 250
153 },
154 .mr_cache[10] = {
155 .size = 500,
156 .limit = 250
157 },
158 .mr_cache[11] = {
159 .size = 500,
160 .limit = 250
161 },
162 .mr_cache[12] = {
163 .size = 64,
164 .limit = 32
165 },
166 .mr_cache[13] = {
167 .size = 32,
168 .limit = 16
169 },
170 .mr_cache[14] = {
171 .size = 16,
172 .limit = 8
173 },
174 .mr_cache[15] = {
175 .size = 8,
176 .limit = 4
177 },
178 },
179 };
180
181 #define FW_INIT_TIMEOUT_MILI 2000
182 #define FW_INIT_WAIT_MS 2
183 #define FW_PRE_INIT_TIMEOUT_MILI 120000
184 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
185
fw_initializing(struct mlx5_core_dev * dev)186 static int fw_initializing(struct mlx5_core_dev *dev)
187 {
188 return ioread32be(&dev->iseg->initializing) >> 31;
189 }
190
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)191 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
192 u32 warn_time_mili)
193 {
194 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
195 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
196 int err = 0;
197
198 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
199
200 while (fw_initializing(dev)) {
201 if (time_after(jiffies, end)) {
202 err = -EBUSY;
203 break;
204 }
205 if (warn_time_mili && time_after(jiffies, warn)) {
206 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
207 jiffies_to_msecs(end - warn) / 1000);
208 warn = jiffies + msecs_to_jiffies(warn_time_mili);
209 }
210 msleep(FW_INIT_WAIT_MS);
211 }
212
213 return err;
214 }
215
mlx5_set_driver_version(struct mlx5_core_dev * dev)216 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
217 {
218 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
219 driver_version);
220 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
221 int remaining_size = driver_ver_sz;
222 char *string;
223
224 if (!MLX5_CAP_GEN(dev, driver_version))
225 return;
226
227 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
228
229 strncpy(string, "Linux", remaining_size);
230
231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
232 strncat(string, ",", remaining_size);
233
234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
235 strncat(string, KBUILD_MODNAME, remaining_size);
236
237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
238 strncat(string, ",", remaining_size);
239
240 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
241
242 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
243 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
244 LINUX_VERSION_SUBLEVEL);
245
246 /*Send the command*/
247 MLX5_SET(set_driver_version_in, in, opcode,
248 MLX5_CMD_OP_SET_DRIVER_VERSION);
249
250 mlx5_cmd_exec_in(dev, set_driver_version, in);
251 }
252
set_dma_caps(struct pci_dev * pdev)253 static int set_dma_caps(struct pci_dev *pdev)
254 {
255 int err;
256
257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
258 if (err) {
259 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
261 if (err) {
262 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
263 return err;
264 }
265 }
266
267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
268 return err;
269 }
270
mlx5_pci_enable_device(struct mlx5_core_dev * dev)271 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
272 {
273 struct pci_dev *pdev = dev->pdev;
274 int err = 0;
275
276 mutex_lock(&dev->pci_status_mutex);
277 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
278 err = pci_enable_device(pdev);
279 if (!err)
280 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
281 }
282 mutex_unlock(&dev->pci_status_mutex);
283
284 return err;
285 }
286
mlx5_pci_disable_device(struct mlx5_core_dev * dev)287 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
288 {
289 struct pci_dev *pdev = dev->pdev;
290
291 mutex_lock(&dev->pci_status_mutex);
292 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
293 pci_disable_device(pdev);
294 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
295 }
296 mutex_unlock(&dev->pci_status_mutex);
297 }
298
request_bar(struct pci_dev * pdev)299 static int request_bar(struct pci_dev *pdev)
300 {
301 int err = 0;
302
303 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
304 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
305 return -ENODEV;
306 }
307
308 err = pci_request_regions(pdev, KBUILD_MODNAME);
309 if (err)
310 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
311
312 return err;
313 }
314
release_bar(struct pci_dev * pdev)315 static void release_bar(struct pci_dev *pdev)
316 {
317 pci_release_regions(pdev);
318 }
319
320 struct mlx5_reg_host_endianness {
321 u8 he;
322 u8 rsvd[15];
323 };
324
325 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
326
327 enum {
328 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
329 MLX5_DEV_CAP_FLAG_DCT,
330 };
331
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)332 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
333 {
334 switch (size) {
335 case 128:
336 return 0;
337 case 256:
338 return 1;
339 case 512:
340 return 2;
341 case 1024:
342 return 3;
343 case 2048:
344 return 4;
345 case 4096:
346 return 5;
347 default:
348 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
349 return 0;
350 }
351 }
352
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)353 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
354 enum mlx5_cap_type cap_type,
355 enum mlx5_cap_mode cap_mode)
356 {
357 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
358 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
359 void *out, *hca_caps;
360 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
361 int err;
362
363 memset(in, 0, sizeof(in));
364 out = kzalloc(out_sz, GFP_KERNEL);
365 if (!out)
366 return -ENOMEM;
367
368 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
369 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
370 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
371 if (err) {
372 mlx5_core_warn(dev,
373 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
374 cap_type, cap_mode, err);
375 goto query_ex;
376 }
377
378 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
379
380 switch (cap_mode) {
381 case HCA_CAP_OPMOD_GET_MAX:
382 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
383 MLX5_UN_SZ_BYTES(hca_cap_union));
384 break;
385 case HCA_CAP_OPMOD_GET_CUR:
386 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
387 MLX5_UN_SZ_BYTES(hca_cap_union));
388 break;
389 default:
390 mlx5_core_warn(dev,
391 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
392 cap_type, cap_mode);
393 err = -EINVAL;
394 break;
395 }
396 query_ex:
397 kfree(out);
398 return err;
399 }
400
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)401 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
402 {
403 int ret;
404
405 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
406 if (ret)
407 return ret;
408 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
409 }
410
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)411 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
412 {
413 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
414 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
415 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
416 }
417
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)418 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
419 {
420 void *set_hca_cap;
421 int req_endianness;
422 int err;
423
424 if (!MLX5_CAP_GEN(dev, atomic))
425 return 0;
426
427 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
428 if (err)
429 return err;
430
431 req_endianness =
432 MLX5_CAP_ATOMIC(dev,
433 supported_atomic_req_8B_endianness_mode_1);
434
435 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
436 return 0;
437
438 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
439
440 /* Set requestor to host endianness */
441 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
442 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
443
444 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
445 }
446
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)447 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
448 {
449 void *set_hca_cap;
450 bool do_set = false;
451 int err;
452
453 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
454 !MLX5_CAP_GEN(dev, pg))
455 return 0;
456
457 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
458 if (err)
459 return err;
460
461 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
462 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
463 MLX5_ST_SZ_BYTES(odp_cap));
464
465 #define ODP_CAP_SET_MAX(dev, field) \
466 do { \
467 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
468 if (_res) { \
469 do_set = true; \
470 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
471 } \
472 } while (0)
473
474 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
475 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
476 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
477 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
478 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
479 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
480 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
481 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
482 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
483 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
484 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
485 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
486 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
487 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
488
489 if (!do_set)
490 return 0;
491
492 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
493 }
494
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)495 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
496 {
497 struct mlx5_profile *prof = &dev->profile;
498 void *set_hca_cap;
499 int err;
500
501 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
502 if (err)
503 return err;
504
505 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
506 capability);
507 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
508 MLX5_ST_SZ_BYTES(cmd_hca_cap));
509
510 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
511 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
512 128);
513 /* we limit the size of the pkey table to 128 entries for now */
514 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
515 to_fw_pkey_sz(dev, 128));
516
517 /* Check log_max_qp from HCA caps to set in current profile */
518 if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) {
519 prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp));
520 } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
521 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
522 prof->log_max_qp,
523 MLX5_CAP_GEN_MAX(dev, log_max_qp));
524 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
525 }
526 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
527 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
528 prof->log_max_qp);
529
530 /* disable cmdif checksum */
531 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
532
533 /* Enable 4K UAR only when HCA supports it and page size is bigger
534 * than 4K.
535 */
536 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
538
539 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
540
541 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
542 MLX5_SET(cmd_hca_cap,
543 set_hca_cap,
544 cache_line_128byte,
545 cache_line_size() >= 128 ? 1 : 0);
546
547 if (MLX5_CAP_GEN_MAX(dev, dct))
548 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
549
550 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
551 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
552
553 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
554 MLX5_SET(cmd_hca_cap,
555 set_hca_cap,
556 num_vhca_ports,
557 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
558
559 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
560 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
561
562 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
563 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
564
565 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
566
567 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
568 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
569 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
570
571 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
572 }
573
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)574 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
575 {
576 void *set_hca_cap;
577 int err;
578
579 if (!MLX5_CAP_GEN(dev, roce))
580 return 0;
581
582 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
583 if (err)
584 return err;
585
586 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
587 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
588 return 0;
589
590 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
591 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
592 MLX5_ST_SZ_BYTES(roce_cap));
593 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
594
595 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
596 return err;
597 }
598
set_hca_cap(struct mlx5_core_dev * dev)599 static int set_hca_cap(struct mlx5_core_dev *dev)
600 {
601 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
602 void *set_ctx;
603 int err;
604
605 set_ctx = kzalloc(set_sz, GFP_KERNEL);
606 if (!set_ctx)
607 return -ENOMEM;
608
609 err = handle_hca_cap(dev, set_ctx);
610 if (err) {
611 mlx5_core_err(dev, "handle_hca_cap failed\n");
612 goto out;
613 }
614
615 memset(set_ctx, 0, set_sz);
616 err = handle_hca_cap_atomic(dev, set_ctx);
617 if (err) {
618 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
619 goto out;
620 }
621
622 memset(set_ctx, 0, set_sz);
623 err = handle_hca_cap_odp(dev, set_ctx);
624 if (err) {
625 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
626 goto out;
627 }
628
629 memset(set_ctx, 0, set_sz);
630 err = handle_hca_cap_roce(dev, set_ctx);
631 if (err) {
632 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
633 goto out;
634 }
635
636 out:
637 kfree(set_ctx);
638 return err;
639 }
640
set_hca_ctrl(struct mlx5_core_dev * dev)641 static int set_hca_ctrl(struct mlx5_core_dev *dev)
642 {
643 struct mlx5_reg_host_endianness he_in;
644 struct mlx5_reg_host_endianness he_out;
645 int err;
646
647 if (!mlx5_core_is_pf(dev))
648 return 0;
649
650 memset(&he_in, 0, sizeof(he_in));
651 he_in.he = MLX5_SET_HOST_ENDIANNESS;
652 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
653 &he_out, sizeof(he_out),
654 MLX5_REG_HOST_ENDIANNESS, 0, 1);
655 return err;
656 }
657
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)658 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
659 {
660 int ret = 0;
661
662 /* Disable local_lb by default */
663 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
664 ret = mlx5_nic_vport_update_local_lb(dev, false);
665
666 return ret;
667 }
668
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)669 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
670 {
671 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
672
673 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
674 MLX5_SET(enable_hca_in, in, function_id, func_id);
675 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
676 dev->caps.embedded_cpu);
677 return mlx5_cmd_exec_in(dev, enable_hca, in);
678 }
679
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)680 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
681 {
682 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
683
684 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
685 MLX5_SET(disable_hca_in, in, function_id, func_id);
686 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
687 dev->caps.embedded_cpu);
688 return mlx5_cmd_exec_in(dev, disable_hca, in);
689 }
690
mlx5_core_set_issi(struct mlx5_core_dev * dev)691 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
692 {
693 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
694 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
695 u32 sup_issi;
696 int err;
697
698 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
699 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
700 if (err) {
701 u32 syndrome;
702 u8 status;
703
704 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
705 if (!status || syndrome == MLX5_DRIVER_SYND) {
706 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
707 err, status, syndrome);
708 return err;
709 }
710
711 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
712 dev->issi = 0;
713 return 0;
714 }
715
716 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
717
718 if (sup_issi & (1 << 1)) {
719 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
720
721 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
722 MLX5_SET(set_issi_in, set_in, current_issi, 1);
723 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
724 if (err) {
725 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
726 err);
727 return err;
728 }
729
730 dev->issi = 1;
731
732 return 0;
733 } else if (sup_issi & (1 << 0) || !sup_issi) {
734 return 0;
735 }
736
737 return -EOPNOTSUPP;
738 }
739
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)740 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
741 const struct pci_device_id *id)
742 {
743 int err = 0;
744
745 mutex_init(&dev->pci_status_mutex);
746 pci_set_drvdata(dev->pdev, dev);
747
748 dev->bar_addr = pci_resource_start(pdev, 0);
749
750 err = mlx5_pci_enable_device(dev);
751 if (err) {
752 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
753 return err;
754 }
755
756 err = request_bar(pdev);
757 if (err) {
758 mlx5_core_err(dev, "error requesting BARs, aborting\n");
759 goto err_disable;
760 }
761
762 pci_set_master(pdev);
763
764 err = set_dma_caps(pdev);
765 if (err) {
766 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
767 goto err_clr_master;
768 }
769
770 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
771 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
773 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
774
775 dev->iseg_base = dev->bar_addr;
776 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
777 if (!dev->iseg) {
778 err = -ENOMEM;
779 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
780 goto err_clr_master;
781 }
782
783 mlx5_pci_vsc_init(dev);
784 return 0;
785
786 err_clr_master:
787 pci_clear_master(dev->pdev);
788 release_bar(dev->pdev);
789 err_disable:
790 mlx5_pci_disable_device(dev);
791 return err;
792 }
793
mlx5_pci_close(struct mlx5_core_dev * dev)794 static void mlx5_pci_close(struct mlx5_core_dev *dev)
795 {
796 /* health work might still be active, and it needs pci bar in
797 * order to know the NIC state. Therefore, drain the health WQ
798 * before removing the pci bars
799 */
800 mlx5_drain_health_wq(dev);
801 iounmap(dev->iseg);
802 pci_clear_master(dev->pdev);
803 release_bar(dev->pdev);
804 mlx5_pci_disable_device(dev);
805 }
806
mlx5_init_once(struct mlx5_core_dev * dev)807 static int mlx5_init_once(struct mlx5_core_dev *dev)
808 {
809 int err;
810
811 dev->priv.devcom = mlx5_devcom_register_device(dev);
812 if (IS_ERR(dev->priv.devcom))
813 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
814 dev->priv.devcom);
815
816 err = mlx5_query_board_id(dev);
817 if (err) {
818 mlx5_core_err(dev, "query board id failed\n");
819 goto err_devcom;
820 }
821
822 err = mlx5_irq_table_init(dev);
823 if (err) {
824 mlx5_core_err(dev, "failed to initialize irq table\n");
825 goto err_devcom;
826 }
827
828 err = mlx5_eq_table_init(dev);
829 if (err) {
830 mlx5_core_err(dev, "failed to initialize eq\n");
831 goto err_irq_cleanup;
832 }
833
834 err = mlx5_events_init(dev);
835 if (err) {
836 mlx5_core_err(dev, "failed to initialize events\n");
837 goto err_eq_cleanup;
838 }
839
840 err = mlx5_fw_reset_init(dev);
841 if (err) {
842 mlx5_core_err(dev, "failed to initialize fw reset events\n");
843 goto err_events_cleanup;
844 }
845
846 mlx5_cq_debugfs_init(dev);
847
848 mlx5_init_reserved_gids(dev);
849
850 mlx5_init_clock(dev);
851
852 dev->vxlan = mlx5_vxlan_create(dev);
853 dev->geneve = mlx5_geneve_create(dev);
854
855 err = mlx5_init_rl_table(dev);
856 if (err) {
857 mlx5_core_err(dev, "Failed to init rate limiting\n");
858 goto err_tables_cleanup;
859 }
860
861 err = mlx5_mpfs_init(dev);
862 if (err) {
863 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
864 goto err_rl_cleanup;
865 }
866
867 err = mlx5_sriov_init(dev);
868 if (err) {
869 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
870 goto err_mpfs_cleanup;
871 }
872
873 err = mlx5_eswitch_init(dev);
874 if (err) {
875 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
876 goto err_sriov_cleanup;
877 }
878
879 err = mlx5_fpga_init(dev);
880 if (err) {
881 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
882 goto err_eswitch_cleanup;
883 }
884
885 err = mlx5_vhca_event_init(dev);
886 if (err) {
887 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
888 goto err_fpga_cleanup;
889 }
890
891 err = mlx5_sf_hw_table_init(dev);
892 if (err) {
893 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
894 goto err_sf_hw_table_cleanup;
895 }
896
897 err = mlx5_sf_table_init(dev);
898 if (err) {
899 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
900 goto err_sf_table_cleanup;
901 }
902
903 dev->dm = mlx5_dm_create(dev);
904 if (IS_ERR(dev->dm))
905 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
906
907 dev->tracer = mlx5_fw_tracer_create(dev);
908 dev->hv_vhca = mlx5_hv_vhca_create(dev);
909 dev->rsc_dump = mlx5_rsc_dump_create(dev);
910
911 return 0;
912
913 err_sf_table_cleanup:
914 mlx5_sf_hw_table_cleanup(dev);
915 err_sf_hw_table_cleanup:
916 mlx5_vhca_event_cleanup(dev);
917 err_fpga_cleanup:
918 mlx5_fpga_cleanup(dev);
919 err_eswitch_cleanup:
920 mlx5_eswitch_cleanup(dev->priv.eswitch);
921 err_sriov_cleanup:
922 mlx5_sriov_cleanup(dev);
923 err_mpfs_cleanup:
924 mlx5_mpfs_cleanup(dev);
925 err_rl_cleanup:
926 mlx5_cleanup_rl_table(dev);
927 err_tables_cleanup:
928 mlx5_geneve_destroy(dev->geneve);
929 mlx5_vxlan_destroy(dev->vxlan);
930 mlx5_cleanup_clock(dev);
931 mlx5_cleanup_reserved_gids(dev);
932 mlx5_cq_debugfs_cleanup(dev);
933 mlx5_fw_reset_cleanup(dev);
934 err_events_cleanup:
935 mlx5_events_cleanup(dev);
936 err_eq_cleanup:
937 mlx5_eq_table_cleanup(dev);
938 err_irq_cleanup:
939 mlx5_irq_table_cleanup(dev);
940 err_devcom:
941 mlx5_devcom_unregister_device(dev->priv.devcom);
942
943 return err;
944 }
945
mlx5_cleanup_once(struct mlx5_core_dev * dev)946 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
947 {
948 mlx5_rsc_dump_destroy(dev);
949 mlx5_hv_vhca_destroy(dev->hv_vhca);
950 mlx5_fw_tracer_destroy(dev->tracer);
951 mlx5_dm_cleanup(dev);
952 mlx5_sf_table_cleanup(dev);
953 mlx5_sf_hw_table_cleanup(dev);
954 mlx5_vhca_event_cleanup(dev);
955 mlx5_fpga_cleanup(dev);
956 mlx5_eswitch_cleanup(dev->priv.eswitch);
957 mlx5_sriov_cleanup(dev);
958 mlx5_mpfs_cleanup(dev);
959 mlx5_cleanup_rl_table(dev);
960 mlx5_geneve_destroy(dev->geneve);
961 mlx5_vxlan_destroy(dev->vxlan);
962 mlx5_cleanup_clock(dev);
963 mlx5_cleanup_reserved_gids(dev);
964 mlx5_cq_debugfs_cleanup(dev);
965 mlx5_fw_reset_cleanup(dev);
966 mlx5_events_cleanup(dev);
967 mlx5_eq_table_cleanup(dev);
968 mlx5_irq_table_cleanup(dev);
969 mlx5_devcom_unregister_device(dev->priv.devcom);
970 }
971
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)972 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
973 {
974 int err;
975
976 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
977 fw_rev_min(dev), fw_rev_sub(dev));
978
979 /* Only PFs hold the relevant PCIe information for this query */
980 if (mlx5_core_is_pf(dev))
981 pcie_print_link_status(dev->pdev);
982
983 /* wait for firmware to accept initialization segments configurations
984 */
985 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
986 if (err) {
987 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
988 FW_PRE_INIT_TIMEOUT_MILI);
989 return err;
990 }
991
992 err = mlx5_cmd_init(dev);
993 if (err) {
994 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
995 return err;
996 }
997
998 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
999 if (err) {
1000 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
1001 FW_INIT_TIMEOUT_MILI);
1002 goto err_cmd_cleanup;
1003 }
1004
1005 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
1006 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1007
1008 err = mlx5_core_enable_hca(dev, 0);
1009 if (err) {
1010 mlx5_core_err(dev, "enable hca failed\n");
1011 goto err_cmd_cleanup;
1012 }
1013
1014 err = mlx5_core_set_issi(dev);
1015 if (err) {
1016 mlx5_core_err(dev, "failed to set issi\n");
1017 goto err_disable_hca;
1018 }
1019
1020 err = mlx5_satisfy_startup_pages(dev, 1);
1021 if (err) {
1022 mlx5_core_err(dev, "failed to allocate boot pages\n");
1023 goto err_disable_hca;
1024 }
1025
1026 err = set_hca_ctrl(dev);
1027 if (err) {
1028 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1029 goto reclaim_boot_pages;
1030 }
1031
1032 err = set_hca_cap(dev);
1033 if (err) {
1034 mlx5_core_err(dev, "set_hca_cap failed\n");
1035 goto reclaim_boot_pages;
1036 }
1037
1038 err = mlx5_satisfy_startup_pages(dev, 0);
1039 if (err) {
1040 mlx5_core_err(dev, "failed to allocate init pages\n");
1041 goto reclaim_boot_pages;
1042 }
1043
1044 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1045 if (err) {
1046 mlx5_core_err(dev, "init hca failed\n");
1047 goto reclaim_boot_pages;
1048 }
1049
1050 mlx5_set_driver_version(dev);
1051
1052 mlx5_start_health_poll(dev);
1053
1054 err = mlx5_query_hca_caps(dev);
1055 if (err) {
1056 mlx5_core_err(dev, "query hca failed\n");
1057 goto stop_health;
1058 }
1059
1060 return 0;
1061
1062 stop_health:
1063 mlx5_stop_health_poll(dev, boot);
1064 reclaim_boot_pages:
1065 mlx5_reclaim_startup_pages(dev);
1066 err_disable_hca:
1067 mlx5_core_disable_hca(dev, 0);
1068 err_cmd_cleanup:
1069 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1070 mlx5_cmd_cleanup(dev);
1071
1072 return err;
1073 }
1074
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1075 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1076 {
1077 int err;
1078
1079 mlx5_stop_health_poll(dev, boot);
1080 err = mlx5_cmd_teardown_hca(dev);
1081 if (err) {
1082 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1083 return err;
1084 }
1085 mlx5_reclaim_startup_pages(dev);
1086 mlx5_core_disable_hca(dev, 0);
1087 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1088 mlx5_cmd_cleanup(dev);
1089
1090 return 0;
1091 }
1092
mlx5_load(struct mlx5_core_dev * dev)1093 static int mlx5_load(struct mlx5_core_dev *dev)
1094 {
1095 int err;
1096
1097 dev->priv.uar = mlx5_get_uars_page(dev);
1098 if (IS_ERR(dev->priv.uar)) {
1099 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1100 err = PTR_ERR(dev->priv.uar);
1101 return err;
1102 }
1103
1104 mlx5_events_start(dev);
1105 mlx5_pagealloc_start(dev);
1106
1107 err = mlx5_irq_table_create(dev);
1108 if (err) {
1109 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1110 goto err_irq_table;
1111 }
1112
1113 err = mlx5_eq_table_create(dev);
1114 if (err) {
1115 mlx5_core_err(dev, "Failed to create EQs\n");
1116 goto err_eq_table;
1117 }
1118
1119 err = mlx5_fw_tracer_init(dev->tracer);
1120 if (err) {
1121 mlx5_core_err(dev, "Failed to init FW tracer\n");
1122 goto err_fw_tracer;
1123 }
1124
1125 mlx5_fw_reset_events_start(dev);
1126 mlx5_hv_vhca_init(dev->hv_vhca);
1127
1128 err = mlx5_rsc_dump_init(dev);
1129 if (err) {
1130 mlx5_core_err(dev, "Failed to init Resource dump\n");
1131 goto err_rsc_dump;
1132 }
1133
1134 err = mlx5_fpga_device_start(dev);
1135 if (err) {
1136 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1137 goto err_fpga_start;
1138 }
1139
1140 mlx5_accel_ipsec_init(dev);
1141
1142 err = mlx5_accel_tls_init(dev);
1143 if (err) {
1144 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1145 goto err_tls_start;
1146 }
1147
1148 err = mlx5_init_fs(dev);
1149 if (err) {
1150 mlx5_core_err(dev, "Failed to init flow steering\n");
1151 goto err_fs;
1152 }
1153
1154 err = mlx5_core_set_hca_defaults(dev);
1155 if (err) {
1156 mlx5_core_err(dev, "Failed to set hca defaults\n");
1157 goto err_set_hca;
1158 }
1159
1160 mlx5_vhca_event_start(dev);
1161
1162 err = mlx5_sf_hw_table_create(dev);
1163 if (err) {
1164 mlx5_core_err(dev, "sf table create failed %d\n", err);
1165 goto err_vhca;
1166 }
1167
1168 err = mlx5_ec_init(dev);
1169 if (err) {
1170 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1171 goto err_ec;
1172 }
1173
1174 mlx5_lag_add_mdev(dev);
1175 err = mlx5_sriov_attach(dev);
1176 if (err) {
1177 mlx5_core_err(dev, "sriov init failed %d\n", err);
1178 goto err_sriov;
1179 }
1180
1181 mlx5_sf_dev_table_create(dev);
1182
1183 return 0;
1184
1185 err_sriov:
1186 mlx5_lag_remove_mdev(dev);
1187 mlx5_ec_cleanup(dev);
1188 err_ec:
1189 mlx5_sf_hw_table_destroy(dev);
1190 err_vhca:
1191 mlx5_vhca_event_stop(dev);
1192 err_set_hca:
1193 mlx5_cleanup_fs(dev);
1194 err_fs:
1195 mlx5_accel_tls_cleanup(dev);
1196 err_tls_start:
1197 mlx5_accel_ipsec_cleanup(dev);
1198 mlx5_fpga_device_stop(dev);
1199 err_fpga_start:
1200 mlx5_rsc_dump_cleanup(dev);
1201 err_rsc_dump:
1202 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1203 mlx5_fw_reset_events_stop(dev);
1204 mlx5_fw_tracer_cleanup(dev->tracer);
1205 err_fw_tracer:
1206 mlx5_eq_table_destroy(dev);
1207 err_eq_table:
1208 mlx5_irq_table_destroy(dev);
1209 err_irq_table:
1210 mlx5_pagealloc_stop(dev);
1211 mlx5_events_stop(dev);
1212 mlx5_put_uars_page(dev, dev->priv.uar);
1213 return err;
1214 }
1215
mlx5_unload(struct mlx5_core_dev * dev)1216 static void mlx5_unload(struct mlx5_core_dev *dev)
1217 {
1218 mlx5_sf_dev_table_destroy(dev);
1219 mlx5_sriov_detach(dev);
1220 mlx5_lag_remove_mdev(dev);
1221 mlx5_ec_cleanup(dev);
1222 mlx5_sf_hw_table_destroy(dev);
1223 mlx5_vhca_event_stop(dev);
1224 mlx5_cleanup_fs(dev);
1225 mlx5_accel_ipsec_cleanup(dev);
1226 mlx5_accel_tls_cleanup(dev);
1227 mlx5_fpga_device_stop(dev);
1228 mlx5_rsc_dump_cleanup(dev);
1229 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1230 mlx5_fw_reset_events_stop(dev);
1231 mlx5_fw_tracer_cleanup(dev->tracer);
1232 mlx5_eq_table_destroy(dev);
1233 mlx5_irq_table_destroy(dev);
1234 mlx5_pagealloc_stop(dev);
1235 mlx5_events_stop(dev);
1236 mlx5_put_uars_page(dev, dev->priv.uar);
1237 }
1238
mlx5_init_one(struct mlx5_core_dev * dev)1239 int mlx5_init_one(struct mlx5_core_dev *dev)
1240 {
1241 int err = 0;
1242
1243 mutex_lock(&dev->intf_state_mutex);
1244 dev->state = MLX5_DEVICE_STATE_UP;
1245
1246 err = mlx5_function_setup(dev, true);
1247 if (err)
1248 goto err_function;
1249
1250 err = mlx5_init_once(dev);
1251 if (err) {
1252 mlx5_core_err(dev, "sw objs init failed\n");
1253 goto function_teardown;
1254 }
1255
1256 err = mlx5_load(dev);
1257 if (err)
1258 goto err_load;
1259
1260 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1261
1262 err = mlx5_devlink_register(priv_to_devlink(dev));
1263 if (err)
1264 goto err_devlink_reg;
1265
1266 err = mlx5_register_device(dev);
1267 if (err)
1268 goto err_register;
1269
1270 mutex_unlock(&dev->intf_state_mutex);
1271 return 0;
1272
1273 err_register:
1274 mlx5_devlink_unregister(priv_to_devlink(dev));
1275 err_devlink_reg:
1276 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1277 mlx5_unload(dev);
1278 err_load:
1279 mlx5_cleanup_once(dev);
1280 function_teardown:
1281 mlx5_function_teardown(dev, true);
1282 err_function:
1283 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1284 mutex_unlock(&dev->intf_state_mutex);
1285 return err;
1286 }
1287
mlx5_uninit_one(struct mlx5_core_dev * dev)1288 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1289 {
1290 mutex_lock(&dev->intf_state_mutex);
1291
1292 mlx5_unregister_device(dev);
1293 mlx5_devlink_unregister(priv_to_devlink(dev));
1294
1295 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1296 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1297 __func__);
1298 mlx5_cleanup_once(dev);
1299 goto out;
1300 }
1301
1302 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1303 mlx5_unload(dev);
1304 mlx5_cleanup_once(dev);
1305 mlx5_function_teardown(dev, true);
1306 out:
1307 mutex_unlock(&dev->intf_state_mutex);
1308 }
1309
mlx5_load_one(struct mlx5_core_dev * dev)1310 int mlx5_load_one(struct mlx5_core_dev *dev)
1311 {
1312 int err = 0;
1313
1314 mutex_lock(&dev->intf_state_mutex);
1315 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1316 mlx5_core_warn(dev, "interface is up, NOP\n");
1317 goto out;
1318 }
1319 /* remove any previous indication of internal error */
1320 dev->state = MLX5_DEVICE_STATE_UP;
1321
1322 err = mlx5_function_setup(dev, false);
1323 if (err)
1324 goto err_function;
1325
1326 err = mlx5_load(dev);
1327 if (err)
1328 goto err_load;
1329
1330 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1331
1332 err = mlx5_attach_device(dev);
1333 if (err)
1334 goto err_attach;
1335
1336 mutex_unlock(&dev->intf_state_mutex);
1337 return 0;
1338
1339 err_attach:
1340 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1341 mlx5_unload(dev);
1342 err_load:
1343 mlx5_function_teardown(dev, false);
1344 err_function:
1345 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1346 out:
1347 mutex_unlock(&dev->intf_state_mutex);
1348 return err;
1349 }
1350
mlx5_unload_one(struct mlx5_core_dev * dev)1351 void mlx5_unload_one(struct mlx5_core_dev *dev)
1352 {
1353 mutex_lock(&dev->intf_state_mutex);
1354
1355 mlx5_detach_device(dev);
1356
1357 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1358 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1359 __func__);
1360 goto out;
1361 }
1362
1363 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1364 mlx5_unload(dev);
1365 mlx5_function_teardown(dev, false);
1366 out:
1367 mutex_unlock(&dev->intf_state_mutex);
1368 }
1369
1370 static const int types[] = {
1371 MLX5_CAP_GENERAL,
1372 MLX5_CAP_GENERAL_2,
1373 MLX5_CAP_ETHERNET_OFFLOADS,
1374 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1375 MLX5_CAP_ODP,
1376 MLX5_CAP_ATOMIC,
1377 MLX5_CAP_ROCE,
1378 MLX5_CAP_IPOIB_OFFLOADS,
1379 MLX5_CAP_FLOW_TABLE,
1380 MLX5_CAP_ESWITCH_FLOW_TABLE,
1381 MLX5_CAP_ESWITCH,
1382 MLX5_CAP_VECTOR_CALC,
1383 MLX5_CAP_QOS,
1384 MLX5_CAP_DEBUG,
1385 MLX5_CAP_DEV_MEM,
1386 MLX5_CAP_DEV_EVENT,
1387 MLX5_CAP_TLS,
1388 MLX5_CAP_VDPA_EMULATION,
1389 MLX5_CAP_IPSEC,
1390 };
1391
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1392 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1393 {
1394 int type;
1395 int i;
1396
1397 for (i = 0; i < ARRAY_SIZE(types); i++) {
1398 type = types[i];
1399 kfree(dev->caps.hca[type]);
1400 }
1401 }
1402
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1403 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1404 {
1405 struct mlx5_hca_cap *cap;
1406 int type;
1407 int i;
1408
1409 for (i = 0; i < ARRAY_SIZE(types); i++) {
1410 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1411 if (!cap)
1412 goto err;
1413 type = types[i];
1414 dev->caps.hca[type] = cap;
1415 }
1416
1417 return 0;
1418
1419 err:
1420 mlx5_hca_caps_free(dev);
1421 return -ENOMEM;
1422 }
1423
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1424 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1425 {
1426 struct mlx5_priv *priv = &dev->priv;
1427 int err;
1428
1429 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1430 INIT_LIST_HEAD(&priv->ctx_list);
1431 spin_lock_init(&priv->ctx_lock);
1432 lockdep_register_key(&dev->lock_key);
1433 mutex_init(&dev->intf_state_mutex);
1434 lockdep_set_class(&dev->intf_state_mutex, &dev->lock_key);
1435
1436 mutex_init(&priv->bfregs.reg_head.lock);
1437 mutex_init(&priv->bfregs.wc_head.lock);
1438 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1439 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1440
1441 mutex_init(&priv->alloc_mutex);
1442 mutex_init(&priv->pgdir_mutex);
1443 INIT_LIST_HEAD(&priv->pgdir_list);
1444
1445 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1446 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1447 mlx5_debugfs_root);
1448 INIT_LIST_HEAD(&priv->traps);
1449
1450 err = mlx5_health_init(dev);
1451 if (err)
1452 goto err_health_init;
1453
1454 err = mlx5_pagealloc_init(dev);
1455 if (err)
1456 goto err_pagealloc_init;
1457
1458 err = mlx5_adev_init(dev);
1459 if (err)
1460 goto err_adev_init;
1461
1462 err = mlx5_hca_caps_alloc(dev);
1463 if (err)
1464 goto err_hca_caps;
1465
1466 return 0;
1467
1468 err_hca_caps:
1469 mlx5_adev_cleanup(dev);
1470 err_adev_init:
1471 mlx5_pagealloc_cleanup(dev);
1472 err_pagealloc_init:
1473 mlx5_health_cleanup(dev);
1474 err_health_init:
1475 debugfs_remove(dev->priv.dbg_root);
1476 mutex_destroy(&priv->pgdir_mutex);
1477 mutex_destroy(&priv->alloc_mutex);
1478 mutex_destroy(&priv->bfregs.wc_head.lock);
1479 mutex_destroy(&priv->bfregs.reg_head.lock);
1480 mutex_destroy(&dev->intf_state_mutex);
1481 lockdep_unregister_key(&dev->lock_key);
1482 return err;
1483 }
1484
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1485 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1486 {
1487 struct mlx5_priv *priv = &dev->priv;
1488
1489 mlx5_hca_caps_free(dev);
1490 mlx5_adev_cleanup(dev);
1491 mlx5_pagealloc_cleanup(dev);
1492 mlx5_health_cleanup(dev);
1493 debugfs_remove_recursive(dev->priv.dbg_root);
1494 mutex_destroy(&priv->pgdir_mutex);
1495 mutex_destroy(&priv->alloc_mutex);
1496 mutex_destroy(&priv->bfregs.wc_head.lock);
1497 mutex_destroy(&priv->bfregs.reg_head.lock);
1498 mutex_destroy(&dev->intf_state_mutex);
1499 lockdep_unregister_key(&dev->lock_key);
1500 }
1501
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1502 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1503 {
1504 struct mlx5_core_dev *dev;
1505 struct devlink *devlink;
1506 int err;
1507
1508 devlink = mlx5_devlink_alloc(&pdev->dev);
1509 if (!devlink) {
1510 dev_err(&pdev->dev, "devlink alloc failed\n");
1511 return -ENOMEM;
1512 }
1513
1514 dev = devlink_priv(devlink);
1515 dev->device = &pdev->dev;
1516 dev->pdev = pdev;
1517
1518 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1519 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1520
1521 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1522 if (dev->priv.adev_idx < 0) {
1523 err = dev->priv.adev_idx;
1524 goto adev_init_err;
1525 }
1526
1527 err = mlx5_mdev_init(dev, prof_sel);
1528 if (err)
1529 goto mdev_init_err;
1530
1531 err = mlx5_pci_init(dev, pdev, id);
1532 if (err) {
1533 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1534 err);
1535 goto pci_init_err;
1536 }
1537
1538 err = mlx5_init_one(dev);
1539 if (err) {
1540 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1541 err);
1542 goto err_init_one;
1543 }
1544
1545 err = mlx5_crdump_enable(dev);
1546 if (err)
1547 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1548
1549 pci_save_state(pdev);
1550 if (!mlx5_core_is_mp_slave(dev))
1551 devlink_reload_enable(devlink);
1552 return 0;
1553
1554 err_init_one:
1555 mlx5_pci_close(dev);
1556 pci_init_err:
1557 mlx5_mdev_uninit(dev);
1558 mdev_init_err:
1559 mlx5_adev_idx_free(dev->priv.adev_idx);
1560 adev_init_err:
1561 mlx5_devlink_free(devlink);
1562
1563 return err;
1564 }
1565
remove_one(struct pci_dev * pdev)1566 static void remove_one(struct pci_dev *pdev)
1567 {
1568 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1569 struct devlink *devlink = priv_to_devlink(dev);
1570
1571 devlink_reload_disable(devlink);
1572 mlx5_crdump_disable(dev);
1573 mlx5_drain_health_wq(dev);
1574 mlx5_uninit_one(dev);
1575 mlx5_pci_close(dev);
1576 mlx5_mdev_uninit(dev);
1577 mlx5_adev_idx_free(dev->priv.adev_idx);
1578 mlx5_devlink_free(devlink);
1579 }
1580
1581 #define mlx5_pci_trace(dev, fmt, ...) ({ \
1582 struct mlx5_core_dev *__dev = (dev); \
1583 mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \
1584 __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \
1585 __dev->pci_status, ##__VA_ARGS__); \
1586 })
1587
result2str(enum pci_ers_result result)1588 static const char *result2str(enum pci_ers_result result)
1589 {
1590 return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" :
1591 result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" :
1592 result == PCI_ERS_RESULT_RECOVERED ? "recovered" :
1593 "unknown";
1594 }
1595
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1596 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1597 pci_channel_state_t state)
1598 {
1599 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1600 enum pci_ers_result res;
1601
1602 mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state);
1603
1604 mlx5_enter_error_state(dev, false);
1605 mlx5_error_sw_reset(dev);
1606 mlx5_unload_one(dev);
1607 mlx5_drain_health_wq(dev);
1608 mlx5_pci_disable_device(dev);
1609
1610 res = state == pci_channel_io_perm_failure ?
1611 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1612
1613 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, result = %d, %s\n",
1614 __func__, dev->state, dev->pci_status, res, result2str(res));
1615 return res;
1616 }
1617
1618 /* wait for the device to show vital signs by waiting
1619 * for the health counter to start counting.
1620 */
wait_vital(struct pci_dev * pdev)1621 static int wait_vital(struct pci_dev *pdev)
1622 {
1623 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1624 struct mlx5_core_health *health = &dev->priv.health;
1625 const int niter = 100;
1626 u32 last_count = 0;
1627 u32 count;
1628 int i;
1629
1630 for (i = 0; i < niter; i++) {
1631 count = ioread32be(health->health_counter);
1632 if (count && count != 0xffffffff) {
1633 if (last_count && last_count != count) {
1634 mlx5_core_info(dev,
1635 "wait vital counter value 0x%x after %d iterations\n",
1636 count, i);
1637 return 0;
1638 }
1639 last_count = count;
1640 }
1641 msleep(50);
1642 }
1643
1644 return -ETIMEDOUT;
1645 }
1646
mlx5_pci_slot_reset(struct pci_dev * pdev)1647 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1648 {
1649 enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT;
1650 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1651 int err;
1652
1653 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Enter\n",
1654 __func__, dev->state, dev->pci_status);
1655
1656 err = mlx5_pci_enable_device(dev);
1657 if (err) {
1658 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1659 __func__, err);
1660 goto out;
1661 }
1662
1663 pci_set_master(pdev);
1664 pci_restore_state(pdev);
1665 pci_save_state(pdev);
1666
1667 err = wait_vital(pdev);
1668 if (err) {
1669 mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n",
1670 __func__, err);
1671 goto out;
1672 }
1673
1674 res = PCI_ERS_RESULT_RECOVERED;
1675 out:
1676 mlx5_core_info(dev, "%s Device state = %d pci_status: %d. Exit, err = %d, result = %d, %s\n",
1677 __func__, dev->state, dev->pci_status, err, res, result2str(res));
1678 return res;
1679 }
1680
mlx5_pci_resume(struct pci_dev * pdev)1681 static void mlx5_pci_resume(struct pci_dev *pdev)
1682 {
1683 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1684 int err;
1685
1686 mlx5_pci_trace(dev, "Enter, loading driver..\n");
1687
1688 err = mlx5_load_one(dev);
1689
1690 if (!err)
1691 devlink_health_reporter_state_update(dev->priv.health.fw_fatal_reporter,
1692 DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
1693
1694 mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err,
1695 !err ? "recovered" : "Failed");
1696 }
1697
1698 static const struct pci_error_handlers mlx5_err_handler = {
1699 .error_detected = mlx5_pci_err_detected,
1700 .slot_reset = mlx5_pci_slot_reset,
1701 .resume = mlx5_pci_resume
1702 };
1703
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1704 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1705 {
1706 bool fast_teardown = false, force_teardown = false;
1707 int ret = 1;
1708
1709 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1710 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1711
1712 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1713 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1714
1715 if (!fast_teardown && !force_teardown)
1716 return -EOPNOTSUPP;
1717
1718 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1719 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1720 return -EAGAIN;
1721 }
1722
1723 /* Panic tear down fw command will stop the PCI bus communication
1724 * with the HCA, so the health polll is no longer needed.
1725 */
1726 mlx5_drain_health_wq(dev);
1727 mlx5_stop_health_poll(dev, false);
1728
1729 ret = mlx5_cmd_fast_teardown_hca(dev);
1730 if (!ret)
1731 goto succeed;
1732
1733 ret = mlx5_cmd_force_teardown_hca(dev);
1734 if (!ret)
1735 goto succeed;
1736
1737 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1738 mlx5_start_health_poll(dev);
1739 return ret;
1740
1741 succeed:
1742 mlx5_enter_error_state(dev, true);
1743
1744 /* Some platforms requiring freeing the IRQ's in the shutdown
1745 * flow. If they aren't freed they can't be allocated after
1746 * kexec. There is no need to cleanup the mlx5_core software
1747 * contexts.
1748 */
1749 mlx5_core_eq_free_irqs(dev);
1750
1751 return 0;
1752 }
1753
shutdown(struct pci_dev * pdev)1754 static void shutdown(struct pci_dev *pdev)
1755 {
1756 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1757 int err;
1758
1759 mlx5_core_info(dev, "Shutdown was called\n");
1760 err = mlx5_try_fast_unload(dev);
1761 if (err)
1762 mlx5_unload_one(dev);
1763 mlx5_pci_disable_device(dev);
1764 }
1765
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1766 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1767 {
1768 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1769
1770 mlx5_unload_one(dev);
1771
1772 return 0;
1773 }
1774
mlx5_resume(struct pci_dev * pdev)1775 static int mlx5_resume(struct pci_dev *pdev)
1776 {
1777 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1778
1779 return mlx5_load_one(dev);
1780 }
1781
1782 static const struct pci_device_id mlx5_core_pci_table[] = {
1783 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1784 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1785 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1786 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1787 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1788 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1789 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1790 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1791 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1792 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1793 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1794 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1795 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1796 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1797 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1798 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1799 { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */
1800 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1801 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1802 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1803 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1804 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */
1805 { 0, }
1806 };
1807
1808 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1809
mlx5_disable_device(struct mlx5_core_dev * dev)1810 void mlx5_disable_device(struct mlx5_core_dev *dev)
1811 {
1812 mlx5_error_sw_reset(dev);
1813 mlx5_unload_one(dev);
1814 }
1815
mlx5_recover_device(struct mlx5_core_dev * dev)1816 int mlx5_recover_device(struct mlx5_core_dev *dev)
1817 {
1818 if (!mlx5_core_is_sf(dev)) {
1819 mlx5_pci_disable_device(dev);
1820 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1821 return -EIO;
1822 }
1823
1824 return mlx5_load_one(dev);
1825 }
1826
1827 static struct pci_driver mlx5_core_driver = {
1828 .name = KBUILD_MODNAME,
1829 .id_table = mlx5_core_pci_table,
1830 .probe = probe_one,
1831 .remove = remove_one,
1832 .suspend = mlx5_suspend,
1833 .resume = mlx5_resume,
1834 .shutdown = shutdown,
1835 .err_handler = &mlx5_err_handler,
1836 .sriov_configure = mlx5_core_sriov_configure,
1837 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1838 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1839 };
1840
mlx5_core_verify_params(void)1841 static void mlx5_core_verify_params(void)
1842 {
1843 if (prof_sel >= ARRAY_SIZE(profile)) {
1844 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1845 prof_sel,
1846 ARRAY_SIZE(profile) - 1,
1847 MLX5_DEFAULT_PROF);
1848 prof_sel = MLX5_DEFAULT_PROF;
1849 }
1850 }
1851
mlx5_init(void)1852 static int __init mlx5_init(void)
1853 {
1854 int err;
1855
1856 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1857 "mlx5_core name not in sync with kernel module name");
1858
1859 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1860
1861 mlx5_core_verify_params();
1862 mlx5_fpga_ipsec_build_fs_cmds();
1863 mlx5_register_debugfs();
1864
1865 err = mlx5e_init();
1866 if (err)
1867 goto err_debug;
1868
1869 err = mlx5_sf_driver_register();
1870 if (err)
1871 goto err_sf;
1872
1873 err = pci_register_driver(&mlx5_core_driver);
1874 if (err)
1875 goto err_pci;
1876
1877 return 0;
1878
1879 err_pci:
1880 mlx5_sf_driver_unregister();
1881 err_sf:
1882 mlx5e_cleanup();
1883 err_debug:
1884 mlx5_unregister_debugfs();
1885 return err;
1886 }
1887
mlx5_cleanup(void)1888 static void __exit mlx5_cleanup(void)
1889 {
1890 pci_unregister_driver(&mlx5_core_driver);
1891 mlx5_sf_driver_unregister();
1892 mlx5e_cleanup();
1893 mlx5_unregister_debugfs();
1894 }
1895
1896 module_init(mlx5_init);
1897 module_exit(mlx5_cleanup);
1898