1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn10_mpc.h"
28
29 #define REG(reg)\
30 mpc10->mpc_regs->reg
31
32 #define CTX \
33 mpc10->base.ctx
34
35 #undef FN
36 #define FN(reg_name, field_name) \
37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
38
39
mpc1_set_bg_color(struct mpc * mpc,struct tg_color * bg_color,int mpcc_id)40 void mpc1_set_bg_color(struct mpc *mpc,
41 struct tg_color *bg_color,
42 int mpcc_id)
43 {
44 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
46 uint32_t bg_r_cr, bg_g_y, bg_b_cb;
47
48 bottommost_mpcc->blnd_cfg.black_color = *bg_color;
49
50 /* find bottommost mpcc. */
51 while (bottommost_mpcc->mpcc_bot) {
52 bottommost_mpcc = bottommost_mpcc->mpcc_bot;
53 }
54
55 /* mpc color is 12 bit. tg_color is 10 bit */
56 /* todo: might want to use 16 bit to represent color and have each
57 * hw block translate to correct color depth.
58 */
59 bg_r_cr = bg_color->color_r_cr << 2;
60 bg_g_y = bg_color->color_g_y << 2;
61 bg_b_cb = bg_color->color_b_cb << 2;
62
63 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
64 MPCC_BG_R_CR, bg_r_cr);
65 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
66 MPCC_BG_G_Y, bg_g_y);
67 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
68 MPCC_BG_B_CB, bg_b_cb);
69 }
70
mpc1_update_blending(struct mpc * mpc,struct mpcc_blnd_cfg * blnd_cfg,int mpcc_id)71 static void mpc1_update_blending(
72 struct mpc *mpc,
73 struct mpcc_blnd_cfg *blnd_cfg,
74 int mpcc_id)
75 {
76 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
77 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
78
79 REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
80 MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
81 MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha,
82 MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only,
83 MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha,
84 MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
85
86 mpcc->blnd_cfg = *blnd_cfg;
87 }
88
mpc1_update_stereo_mix(struct mpc * mpc,struct mpcc_sm_cfg * sm_cfg,int mpcc_id)89 void mpc1_update_stereo_mix(
90 struct mpc *mpc,
91 struct mpcc_sm_cfg *sm_cfg,
92 int mpcc_id)
93 {
94 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
95
96 REG_UPDATE_6(MPCC_SM_CONTROL[mpcc_id],
97 MPCC_SM_EN, sm_cfg->enable,
98 MPCC_SM_MODE, sm_cfg->sm_mode,
99 MPCC_SM_FRAME_ALT, sm_cfg->frame_alt,
100 MPCC_SM_FIELD_ALT, sm_cfg->field_alt,
101 MPCC_SM_FORCE_NEXT_FRAME_POL, sm_cfg->force_next_frame_porlarity,
102 MPCC_SM_FORCE_NEXT_TOP_POL, sm_cfg->force_next_field_polarity);
103 }
mpc1_assert_idle_mpcc(struct mpc * mpc,int id)104 void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
105 {
106 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
107
108 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));
109 REG_WAIT(MPCC_STATUS[id],
110 MPCC_IDLE, 1,
111 1, 100000);
112 }
113
mpc1_get_mpcc(struct mpc * mpc,int mpcc_id)114 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
115 {
116 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
117
118 ASSERT(mpcc_id < mpc10->num_mpcc);
119 return &(mpc->mpcc_array[mpcc_id]);
120 }
121
mpc1_get_mpcc_for_dpp(struct mpc_tree * tree,int dpp_id)122 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
123 {
124 struct mpcc *tmp_mpcc = tree->opp_list;
125
126 while (tmp_mpcc != NULL) {
127 if (tmp_mpcc->dpp_id == dpp_id)
128 return tmp_mpcc;
129
130 /* avoid circular linked list */
131 ASSERT(tmp_mpcc != tmp_mpcc->mpcc_bot);
132 if (tmp_mpcc == tmp_mpcc->mpcc_bot)
133 break;
134
135 tmp_mpcc = tmp_mpcc->mpcc_bot;
136 }
137 return NULL;
138 }
139
mpc1_is_mpcc_idle(struct mpc * mpc,int mpcc_id)140 bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)
141 {
142 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
143 unsigned int top_sel;
144 unsigned int opp_id;
145 unsigned int idle;
146
147 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
148 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
149 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);
150 if (top_sel == 0xf && opp_id == 0xf && idle)
151 return true;
152 else
153 return false;
154 }
155
mpc1_assert_mpcc_idle_before_connect(struct mpc * mpc,int mpcc_id)156 void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
157 {
158 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
159 unsigned int top_sel, mpc_busy, mpc_idle;
160
161 REG_GET(MPCC_TOP_SEL[mpcc_id],
162 MPCC_TOP_SEL, &top_sel);
163
164 if (top_sel == 0xf) {
165 REG_GET_2(MPCC_STATUS[mpcc_id],
166 MPCC_BUSY, &mpc_busy,
167 MPCC_IDLE, &mpc_idle);
168
169 ASSERT(mpc_busy == 0);
170 ASSERT(mpc_idle == 1);
171 }
172 }
173
174 /*
175 * Insert DPP into MPC tree based on specified blending position.
176 * Only used for planes that are part of blending chain for OPP output
177 *
178 * Parameters:
179 * [in/out] mpc - MPC context.
180 * [in/out] tree - MPC tree structure that plane will be added to.
181 * [in] blnd_cfg - MPCC blending configuration for the new blending layer.
182 * [in] sm_cfg - MPCC stereo mix configuration for the new blending layer.
183 * stereo mix must disable for the very bottom layer of the tree config.
184 * [in] insert_above_mpcc - Insert new plane above this MPCC. If NULL, insert as bottom plane.
185 * [in] dpp_id - DPP instance for the plane to be added.
186 * [in] mpcc_id - The MPCC physical instance to use for blending.
187 *
188 * Return: struct mpcc* - MPCC that was added.
189 */
mpc1_insert_plane(struct mpc * mpc,struct mpc_tree * tree,struct mpcc_blnd_cfg * blnd_cfg,struct mpcc_sm_cfg * sm_cfg,struct mpcc * insert_above_mpcc,int dpp_id,int mpcc_id)190 struct mpcc *mpc1_insert_plane(
191 struct mpc *mpc,
192 struct mpc_tree *tree,
193 struct mpcc_blnd_cfg *blnd_cfg,
194 struct mpcc_sm_cfg *sm_cfg,
195 struct mpcc *insert_above_mpcc,
196 int dpp_id,
197 int mpcc_id)
198 {
199 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
200 struct mpcc *new_mpcc = NULL;
201
202 /* sanity check parameters */
203 ASSERT(mpcc_id < mpc10->num_mpcc);
204 ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));
205
206 if (insert_above_mpcc) {
207 /* check insert_above_mpcc exist in tree->opp_list */
208 struct mpcc *temp_mpcc = tree->opp_list;
209
210 if (temp_mpcc != insert_above_mpcc)
211 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
212 temp_mpcc = temp_mpcc->mpcc_bot;
213 if (temp_mpcc == NULL)
214 return NULL;
215 }
216
217 /* Get and update MPCC struct parameters */
218 new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
219 new_mpcc->dpp_id = dpp_id;
220
221 /* program mux and MPCC_MODE */
222 if (insert_above_mpcc) {
223 new_mpcc->mpcc_bot = insert_above_mpcc;
224 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
225 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
226 } else {
227 new_mpcc->mpcc_bot = NULL;
228 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
229 REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
230 }
231 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
232 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
233
234 /* Configure VUPDATE lock set for this MPCC to map to the OPP */
235 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);
236
237 /* update mpc tree mux setting */
238 if (tree->opp_list == insert_above_mpcc) {
239 /* insert the toppest mpcc */
240 tree->opp_list = new_mpcc;
241 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
242 } else {
243 /* find insert position */
244 struct mpcc *temp_mpcc = tree->opp_list;
245
246 while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc)
247 temp_mpcc = temp_mpcc->mpcc_bot;
248 if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) {
249 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
250 temp_mpcc->mpcc_bot = new_mpcc;
251 if (!insert_above_mpcc)
252 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
253 MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);
254 }
255 }
256
257 /* update the blending configuration */
258 mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
259
260 /* update the stereo mix settings, if provided */
261 if (sm_cfg != NULL) {
262 new_mpcc->sm_cfg = *sm_cfg;
263 mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
264 }
265
266 /* mark this mpcc as in use */
267 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
268
269 return new_mpcc;
270 }
271
272 /*
273 * Remove a specified MPCC from the MPC tree.
274 *
275 * Parameters:
276 * [in/out] mpc - MPC context.
277 * [in/out] tree - MPC tree structure that plane will be removed from.
278 * [in/out] mpcc - MPCC to be removed from tree.
279 *
280 * Return: void
281 */
mpc1_remove_mpcc(struct mpc * mpc,struct mpc_tree * tree,struct mpcc * mpcc_to_remove)282 void mpc1_remove_mpcc(
283 struct mpc *mpc,
284 struct mpc_tree *tree,
285 struct mpcc *mpcc_to_remove)
286 {
287 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
288 bool found = false;
289 int mpcc_id = mpcc_to_remove->mpcc_id;
290
291 if (tree->opp_list == mpcc_to_remove) {
292 found = true;
293 /* remove MPCC from top of tree */
294 if (mpcc_to_remove->mpcc_bot) {
295 /* set the next MPCC in list to be the top MPCC */
296 tree->opp_list = mpcc_to_remove->mpcc_bot;
297 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);
298 } else {
299 /* there are no other MPCC is list */
300 tree->opp_list = NULL;
301 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
302 }
303 } else {
304 /* find mpcc to remove MPCC list */
305 struct mpcc *temp_mpcc = tree->opp_list;
306
307 while (temp_mpcc && temp_mpcc->mpcc_bot != mpcc_to_remove)
308 temp_mpcc = temp_mpcc->mpcc_bot;
309
310 if (temp_mpcc && temp_mpcc->mpcc_bot == mpcc_to_remove) {
311 found = true;
312 temp_mpcc->mpcc_bot = mpcc_to_remove->mpcc_bot;
313 if (mpcc_to_remove->mpcc_bot) {
314 /* remove MPCC in middle of list */
315 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
316 MPCC_BOT_SEL, mpcc_to_remove->mpcc_bot->mpcc_id);
317 } else {
318 /* remove MPCC from bottom of list */
319 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
320 MPCC_BOT_SEL, 0xf);
321 REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],
322 MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
323 }
324 }
325 }
326
327 if (found) {
328 /* turn off MPCC mux registers */
329 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
330 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
331 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
332 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
333
334 /* mark this mpcc as not in use */
335 mpc10->mpcc_in_use_mask &= ~(1 << mpcc_id);
336 mpcc_to_remove->dpp_id = 0xf;
337 mpcc_to_remove->mpcc_bot = NULL;
338 } else {
339 /* In case of resume from S3/S4, remove mpcc from bios left over */
340 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
341 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
342 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
343 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
344 }
345 }
346
mpc1_init_mpcc(struct mpcc * mpcc,int mpcc_inst)347 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst)
348 {
349 mpcc->mpcc_id = mpcc_inst;
350 mpcc->dpp_id = 0xf;
351 mpcc->mpcc_bot = NULL;
352 mpcc->blnd_cfg.overlap_only = false;
353 mpcc->blnd_cfg.global_alpha = 0xff;
354 mpcc->blnd_cfg.global_gain = 0xff;
355 mpcc->sm_cfg.enable = false;
356 }
357
358 /*
359 * Reset the MPCC HW status by disconnecting all muxes.
360 *
361 * Parameters:
362 * [in/out] mpc - MPC context.
363 *
364 * Return: void
365 */
mpc1_mpc_init(struct mpc * mpc)366 void mpc1_mpc_init(struct mpc *mpc)
367 {
368 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
369 int mpcc_id;
370 int opp_id;
371
372 mpc10->mpcc_in_use_mask = 0;
373 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
374 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
375 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
376 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
377 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
378
379 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
380 }
381
382 for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
383 if (REG(MUX[opp_id]))
384 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
385 }
386 }
387
mpc1_mpc_init_single_inst(struct mpc * mpc,unsigned int mpcc_id)388 void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
389 {
390 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
391 int opp_id;
392
393 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
394
395 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
396 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
397 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);
398 REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);
399
400 mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
401
402 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
403 REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
404 }
405
406
mpc1_init_mpcc_list_from_hw(struct mpc * mpc,struct mpc_tree * tree)407 void mpc1_init_mpcc_list_from_hw(
408 struct mpc *mpc,
409 struct mpc_tree *tree)
410 {
411 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
412 unsigned int opp_id;
413 unsigned int top_sel;
414 unsigned int bot_sel;
415 unsigned int out_mux;
416 struct mpcc *mpcc;
417 int mpcc_id;
418 int bot_mpcc_id;
419
420 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);
421
422 if (out_mux != 0xf) {
423 for (mpcc_id = 0; mpcc_id < mpc10->num_mpcc; mpcc_id++) {
424 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
425 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);
426 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);
427
428 if (bot_sel == mpcc_id)
429 bot_sel = 0xf;
430
431 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
432 mpcc = mpc1_get_mpcc(mpc, mpcc_id);
433 mpcc->dpp_id = top_sel;
434 mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
435
436 if (out_mux == mpcc_id)
437 tree->opp_list = mpcc;
438 if (bot_sel != 0xf && bot_sel < mpc10->num_mpcc) {
439 bot_mpcc_id = bot_sel;
440 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);
441 REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);
442 if ((opp_id == tree->opp_id) && (top_sel != 0xf)) {
443 struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
444
445 mpcc->mpcc_bot = mpcc_bottom;
446 }
447 }
448 }
449 }
450 }
451 }
452
mpc1_read_mpcc_state(struct mpc * mpc,int mpcc_inst,struct mpcc_state * s)453 void mpc1_read_mpcc_state(
454 struct mpc *mpc,
455 int mpcc_inst,
456 struct mpcc_state *s)
457 {
458 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
459
460 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
461 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
462 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
463 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
464 MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
465 MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
466 MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
467 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
468 MPCC_BUSY, &s->busy);
469 }
470
mpc1_cursor_lock(struct mpc * mpc,int opp_id,bool lock)471 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
472 {
473 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
474
475 REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
476 }
477
mpc1_get_mpc_out_mux(struct mpc * mpc,int opp_id)478 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
479 {
480 struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
481 uint32_t val = 0xf;
482
483 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
484 REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
485
486 return val;
487 }
488
489 static const struct mpc_funcs dcn10_mpc_funcs = {
490 .read_mpcc_state = mpc1_read_mpcc_state,
491 .insert_plane = mpc1_insert_plane,
492 .remove_mpcc = mpc1_remove_mpcc,
493 .mpc_init = mpc1_mpc_init,
494 .mpc_init_single_inst = mpc1_mpc_init_single_inst,
495 .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
496 .wait_for_idle = mpc1_assert_idle_mpcc,
497 .assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
498 .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw,
499 .update_blending = mpc1_update_blending,
500 .cursor_lock = mpc1_cursor_lock,
501 .set_denorm = NULL,
502 .set_denorm_clamp = NULL,
503 .set_output_csc = NULL,
504 .set_output_gamma = NULL,
505 .get_mpc_out_mux = mpc1_get_mpc_out_mux,
506 .set_bg_color = mpc1_set_bg_color,
507 };
508
dcn10_mpc_construct(struct dcn10_mpc * mpc10,struct dc_context * ctx,const struct dcn_mpc_registers * mpc_regs,const struct dcn_mpc_shift * mpc_shift,const struct dcn_mpc_mask * mpc_mask,int num_mpcc)509 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
510 struct dc_context *ctx,
511 const struct dcn_mpc_registers *mpc_regs,
512 const struct dcn_mpc_shift *mpc_shift,
513 const struct dcn_mpc_mask *mpc_mask,
514 int num_mpcc)
515 {
516 int i;
517
518 mpc10->base.ctx = ctx;
519
520 mpc10->base.funcs = &dcn10_mpc_funcs;
521
522 mpc10->mpc_regs = mpc_regs;
523 mpc10->mpc_shift = mpc_shift;
524 mpc10->mpc_mask = mpc_mask;
525
526 mpc10->mpcc_in_use_mask = 0;
527 mpc10->num_mpcc = num_mpcc;
528
529 for (i = 0; i < MAX_MPCC; i++)
530 mpc1_init_mpcc(&mpc10->base.mpcc_array[i], i);
531 }
532
533