1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7 * Trevor Wu <trevor.wu@mediatek.com>
8 */
9
10 #include <linux/clk.h>
11
12 #include "mt8195-afe-common.h"
13 #include "mt8195-afe-clk.h"
14 #include "mt8195-reg.h"
15 #include "mt8195-audsys-clk.h"
16
17 static const char *aud_clks[MT8195_CLK_NUM] = {
18 /* xtal */
19 [MT8195_CLK_XTAL_26M] = "clk26m",
20 /* divider */
21 [MT8195_CLK_TOP_APLL1] = "apll1_ck",
22 [MT8195_CLK_TOP_APLL2] = "apll2_ck",
23 [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0",
24 [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1",
25 [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2",
26 [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3",
27 [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9",
28 /* mux */
29 [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel",
30 [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel",
31 [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel",
32 [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel",
33 [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel",
34 [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel",
35 [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel",
36 [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel",
37 [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel",
38 /* clock gate */
39 [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b",
40 [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp",
41 /* afe clock gate */
42 [MT8195_CLK_AUD_AFE] = "aud_afe",
43 [MT8195_CLK_AUD_APLL] = "aud_apll",
44 [MT8195_CLK_AUD_APLL2] = "aud_apll2",
45 [MT8195_CLK_AUD_DAC] = "aud_dac",
46 [MT8195_CLK_AUD_ADC] = "aud_adc",
47 [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
48 [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
49 [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
50 [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc",
51 [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires",
52 [MT8195_CLK_AUD_I2SIN] = "aud_i2sin",
53 [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in",
54 [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out",
55 [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out",
56 [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",
57 [MT8195_CLK_AUD_ASRC11] = "aud_asrc11",
58 [MT8195_CLK_AUD_ASRC12] = "aud_asrc12",
59 [MT8195_CLK_AUD_A1SYS] = "aud_a1sys",
60 [MT8195_CLK_AUD_A2SYS] = "aud_a2sys",
61 [MT8195_CLK_AUD_PCMIF] = "aud_pcmif",
62 [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",
63 [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",
64 [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",
65 [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",
66 [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",
67 [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",
68 [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",
69 [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",
70 [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",
71 [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",
72 [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",
73 [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",
74 [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",
75 [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",
76 [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",
77 [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",
78 };
79
mt8195_afe_get_mclk_source_clk_id(int sel)80 int mt8195_afe_get_mclk_source_clk_id(int sel)
81 {
82 switch (sel) {
83 case MT8195_MCK_SEL_26M:
84 return MT8195_CLK_XTAL_26M;
85 case MT8195_MCK_SEL_APLL1:
86 return MT8195_CLK_TOP_APLL1;
87 case MT8195_MCK_SEL_APLL2:
88 return MT8195_CLK_TOP_APLL2;
89 default:
90 return -EINVAL;
91 }
92 }
93
mt8195_afe_get_mclk_source_rate(struct mtk_base_afe * afe,int apll)94 int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)
95 {
96 struct mt8195_afe_private *afe_priv = afe->platform_priv;
97 int clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
98
99 if (clk_id < 0) {
100 dev_dbg(afe->dev, "invalid clk id\n");
101 return 0;
102 }
103
104 return clk_get_rate(afe_priv->clk[clk_id]);
105 }
106
mt8195_afe_get_default_mclk_source_by_rate(int rate)107 int mt8195_afe_get_default_mclk_source_by_rate(int rate)
108 {
109 return ((rate % 8000) == 0) ?
110 MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2;
111 }
112
mt8195_afe_init_clock(struct mtk_base_afe * afe)113 int mt8195_afe_init_clock(struct mtk_base_afe *afe)
114 {
115 struct mt8195_afe_private *afe_priv = afe->platform_priv;
116 int i;
117
118 mt8195_audsys_clk_register(afe);
119
120 afe_priv->clk =
121 devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk),
122 GFP_KERNEL);
123 if (!afe_priv->clk)
124 return -ENOMEM;
125
126 for (i = 0; i < MT8195_CLK_NUM; i++) {
127 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
128 if (IS_ERR(afe_priv->clk[i])) {
129 dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
130 __func__, aud_clks[i],
131 PTR_ERR(afe_priv->clk[i]));
132 return PTR_ERR(afe_priv->clk[i]);
133 }
134 }
135
136 return 0;
137 }
138
mt8195_afe_enable_clk(struct mtk_base_afe * afe,struct clk * clk)139 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)
140 {
141 int ret;
142
143 if (clk) {
144 ret = clk_prepare_enable(clk);
145 if (ret) {
146 dev_dbg(afe->dev, "%s(), failed to enable clk\n",
147 __func__);
148 return ret;
149 }
150 } else {
151 dev_dbg(afe->dev, "NULL clk\n");
152 }
153 return 0;
154 }
155 EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk);
156
mt8195_afe_disable_clk(struct mtk_base_afe * afe,struct clk * clk)157 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)
158 {
159 if (clk)
160 clk_disable_unprepare(clk);
161 else
162 dev_dbg(afe->dev, "NULL clk\n");
163 }
164 EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk);
165
mt8195_afe_prepare_clk(struct mtk_base_afe * afe,struct clk * clk)166 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk)
167 {
168 int ret;
169
170 if (clk) {
171 ret = clk_prepare(clk);
172 if (ret) {
173 dev_dbg(afe->dev, "%s(), failed to prepare clk\n",
174 __func__);
175 return ret;
176 }
177 } else {
178 dev_dbg(afe->dev, "NULL clk\n");
179 }
180 return 0;
181 }
182
mt8195_afe_unprepare_clk(struct mtk_base_afe * afe,struct clk * clk)183 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk)
184 {
185 if (clk)
186 clk_unprepare(clk);
187 else
188 dev_dbg(afe->dev, "NULL clk\n");
189 }
190
mt8195_afe_enable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)191 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
192 {
193 int ret;
194
195 if (clk) {
196 ret = clk_enable(clk);
197 if (ret) {
198 dev_dbg(afe->dev, "%s(), failed to clk enable\n",
199 __func__);
200 return ret;
201 }
202 } else {
203 dev_dbg(afe->dev, "NULL clk\n");
204 }
205 return 0;
206 }
207
mt8195_afe_disable_clk_atomic(struct mtk_base_afe * afe,struct clk * clk)208 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk)
209 {
210 if (clk)
211 clk_disable(clk);
212 else
213 dev_dbg(afe->dev, "NULL clk\n");
214 }
215
mt8195_afe_set_clk_rate(struct mtk_base_afe * afe,struct clk * clk,unsigned int rate)216 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
217 unsigned int rate)
218 {
219 int ret;
220
221 if (clk) {
222 ret = clk_set_rate(clk, rate);
223 if (ret) {
224 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",
225 __func__);
226 return ret;
227 }
228 }
229
230 return 0;
231 }
232
mt8195_afe_set_clk_parent(struct mtk_base_afe * afe,struct clk * clk,struct clk * parent)233 int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,
234 struct clk *parent)
235 {
236 int ret;
237
238 if (clk && parent) {
239 ret = clk_set_parent(clk, parent);
240 if (ret) {
241 dev_dbg(afe->dev, "%s(), failed to set clk parent\n",
242 __func__);
243 return ret;
244 }
245 }
246
247 return 0;
248 }
249
get_top_cg_reg(unsigned int cg_type)250 static unsigned int get_top_cg_reg(unsigned int cg_type)
251 {
252 switch (cg_type) {
253 case MT8195_TOP_CG_A1SYS_TIMING:
254 case MT8195_TOP_CG_A2SYS_TIMING:
255 case MT8195_TOP_CG_26M_TIMING:
256 return ASYS_TOP_CON;
257 default:
258 return 0;
259 }
260 }
261
get_top_cg_mask(unsigned int cg_type)262 static unsigned int get_top_cg_mask(unsigned int cg_type)
263 {
264 switch (cg_type) {
265 case MT8195_TOP_CG_A1SYS_TIMING:
266 return ASYS_TOP_CON_A1SYS_TIMING_ON;
267 case MT8195_TOP_CG_A2SYS_TIMING:
268 return ASYS_TOP_CON_A2SYS_TIMING_ON;
269 case MT8195_TOP_CG_26M_TIMING:
270 return ASYS_TOP_CON_26M_TIMING_ON;
271 default:
272 return 0;
273 }
274 }
275
get_top_cg_on_val(unsigned int cg_type)276 static unsigned int get_top_cg_on_val(unsigned int cg_type)
277 {
278 switch (cg_type) {
279 case MT8195_TOP_CG_A1SYS_TIMING:
280 case MT8195_TOP_CG_A2SYS_TIMING:
281 case MT8195_TOP_CG_26M_TIMING:
282 return get_top_cg_mask(cg_type);
283 default:
284 return 0;
285 }
286 }
287
get_top_cg_off_val(unsigned int cg_type)288 static unsigned int get_top_cg_off_val(unsigned int cg_type)
289 {
290 switch (cg_type) {
291 case MT8195_TOP_CG_A1SYS_TIMING:
292 case MT8195_TOP_CG_A2SYS_TIMING:
293 case MT8195_TOP_CG_26M_TIMING:
294 return 0;
295 default:
296 return get_top_cg_mask(cg_type);
297 }
298 }
299
mt8195_afe_enable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)300 static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
301 {
302 unsigned int reg = get_top_cg_reg(cg_type);
303 unsigned int mask = get_top_cg_mask(cg_type);
304 unsigned int val = get_top_cg_on_val(cg_type);
305
306 regmap_update_bits(afe->regmap, reg, mask, val);
307 return 0;
308 }
309
mt8195_afe_disable_top_cg(struct mtk_base_afe * afe,unsigned int cg_type)310 static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)
311 {
312 unsigned int reg = get_top_cg_reg(cg_type);
313 unsigned int mask = get_top_cg_mask(cg_type);
314 unsigned int val = get_top_cg_off_val(cg_type);
315
316 regmap_update_bits(afe->regmap, reg, mask, val);
317 return 0;
318 }
319
mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe * afe)320 int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)
321 {
322 struct mt8195_afe_private *afe_priv = afe->platform_priv;
323 int i;
324 unsigned int clk_array[] = {
325 MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */
326 MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */
327 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */
328 MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */
329 MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */
330 MT8195_CLK_AUD_AFE, /* AFE HW master switch */
331 MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/
332 MT8195_CLK_AUD_A1SYS, /* AFE HW clock */
333 };
334
335 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
336 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
337
338 return 0;
339 }
340
mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe * afe)341 int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)
342 {
343 struct mt8195_afe_private *afe_priv = afe->platform_priv;
344 int i;
345 unsigned int clk_array[] = {
346 MT8195_CLK_AUD_A1SYS,
347 MT8195_CLK_AUD_A1SYS_HP,
348 MT8195_CLK_AUD_AFE,
349 MT8195_CLK_INFRA_AO_AUDIO_26M_B,
350 MT8195_CLK_TOP_AUD_INTBUS_SEL,
351 MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL,
352 MT8195_CLK_TOP_AUDIO_H_SEL,
353 MT8195_CLK_SCP_ADSP_AUDIODSP,
354 };
355
356 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
357 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
358
359 return 0;
360 }
361
mt8195_afe_enable_afe_on(struct mtk_base_afe * afe)362 static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe)
363 {
364 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
365 return 0;
366 }
367
mt8195_afe_disable_afe_on(struct mtk_base_afe * afe)368 static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe)
369 {
370 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);
371 return 0;
372 }
373
mt8195_afe_enable_timing_sys(struct mtk_base_afe * afe)374 static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe)
375 {
376 struct mt8195_afe_private *afe_priv = afe->platform_priv;
377 int i;
378 unsigned int clk_array[] = {
379 MT8195_CLK_AUD_A1SYS,
380 MT8195_CLK_AUD_A2SYS,
381 };
382 unsigned int cg_array[] = {
383 MT8195_TOP_CG_A1SYS_TIMING,
384 MT8195_TOP_CG_A2SYS_TIMING,
385 MT8195_TOP_CG_26M_TIMING,
386 };
387
388 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
389 mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]);
390
391 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
392 mt8195_afe_enable_top_cg(afe, cg_array[i]);
393
394 return 0;
395 }
396
mt8195_afe_disable_timing_sys(struct mtk_base_afe * afe)397 static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe)
398 {
399 struct mt8195_afe_private *afe_priv = afe->platform_priv;
400 int i;
401 unsigned int clk_array[] = {
402 MT8195_CLK_AUD_A2SYS,
403 MT8195_CLK_AUD_A1SYS,
404 };
405 unsigned int cg_array[] = {
406 MT8195_TOP_CG_26M_TIMING,
407 MT8195_TOP_CG_A2SYS_TIMING,
408 MT8195_TOP_CG_A1SYS_TIMING,
409 };
410
411 for (i = 0; i < ARRAY_SIZE(cg_array); i++)
412 mt8195_afe_disable_top_cg(afe, cg_array[i]);
413
414 for (i = 0; i < ARRAY_SIZE(clk_array); i++)
415 mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]);
416
417 return 0;
418 }
419
mt8195_afe_enable_main_clock(struct mtk_base_afe * afe)420 int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe)
421 {
422 mt8195_afe_enable_timing_sys(afe);
423
424 mt8195_afe_enable_afe_on(afe);
425
426 return 0;
427 }
428
mt8195_afe_disable_main_clock(struct mtk_base_afe * afe)429 int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe)
430 {
431 mt8195_afe_disable_afe_on(afe);
432
433 mt8195_afe_disable_timing_sys(afe);
434
435 return 0;
436 }
437