1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20
21 /* PCI device IDs */
22 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
23 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
24
25 /* Subsystem Device ID */
26 #define PCI_SUBSYS_DEVID_98XX 0xB100
27 #define PCI_SUBSYS_DEVID_96XX 0xB200
28 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
29
30 /* PCI BAR nos */
31 #define PCI_AF_REG_BAR_NUM 0
32 #define PCI_PF_REG_BAR_NUM 2
33 #define PCI_MBOX_BAR_NUM 4
34
35 #define NAME_SIZE 32
36 #define MAX_NIX_BLKS 2
37 #define MAX_CPT_BLKS 2
38
39 /* PF_FUNC */
40 #define RVU_PFVF_PF_SHIFT 10
41 #define RVU_PFVF_PF_MASK 0x3F
42 #define RVU_PFVF_FUNC_SHIFT 0
43 #define RVU_PFVF_FUNC_MASK 0x3FF
44
45 #ifdef CONFIG_DEBUG_FS
46 struct dump_ctx {
47 int lf;
48 int id;
49 bool all;
50 };
51
52 struct cpt_ctx {
53 int blkaddr;
54 struct rvu *rvu;
55 };
56
57 struct rvu_debugfs {
58 struct dentry *root;
59 struct dentry *cgx_root;
60 struct dentry *cgx;
61 struct dentry *lmac;
62 struct dentry *npa;
63 struct dentry *nix;
64 struct dentry *npc;
65 struct dentry *cpt;
66 struct dump_ctx npa_aura_ctx;
67 struct dump_ctx npa_pool_ctx;
68 struct dump_ctx nix_cq_ctx;
69 struct dump_ctx nix_rq_ctx;
70 struct dump_ctx nix_sq_ctx;
71 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
72 int npa_qsize_id;
73 int nix_qsize_id;
74 };
75 #endif
76
77 struct rvu_work {
78 struct work_struct work;
79 struct rvu *rvu;
80 int num_msgs;
81 int up_num_msgs;
82 };
83
84 struct rsrc_bmap {
85 unsigned long *bmap; /* Pointer to resource bitmap */
86 u16 max; /* Max resource id or count */
87 };
88
89 struct rvu_block {
90 struct rsrc_bmap lf;
91 struct admin_queue *aq; /* NIX/NPA AQ */
92 u16 *fn_map; /* LF to pcifunc mapping */
93 bool multislot;
94 bool implemented;
95 u8 addr; /* RVU_BLOCK_ADDR_E */
96 u8 type; /* RVU_BLOCK_TYPE_E */
97 u8 lfshift;
98 u64 lookup_reg;
99 u64 pf_lfcnt_reg;
100 u64 vf_lfcnt_reg;
101 u64 lfcfg_reg;
102 u64 msixcfg_reg;
103 u64 lfreset_reg;
104 unsigned char name[NAME_SIZE];
105 };
106
107 struct nix_mcast {
108 struct qmem *mce_ctx;
109 struct qmem *mcast_buf;
110 int replay_pkind;
111 int next_free_mce;
112 struct mutex mce_lock; /* Serialize MCE updates */
113 };
114
115 struct nix_mce_list {
116 struct hlist_head head;
117 int count;
118 int max;
119 };
120
121 /* layer metadata to uniquely identify a packet header field */
122 struct npc_layer_mdata {
123 u8 lid;
124 u8 ltype;
125 u8 hdr;
126 u8 key;
127 u8 len;
128 };
129
130 /* Structure to represent a field present in the
131 * generated key. A key field may present anywhere and can
132 * be of any size in the generated key. Once this structure
133 * is populated for fields of interest then field's presence
134 * and location (if present) can be known.
135 */
136 struct npc_key_field {
137 /* Masks where all set bits indicate position
138 * of a field in the key
139 */
140 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
141 /* Number of words in the key a field spans. If a field is
142 * of 16 bytes and key offset is 4 then the field will use
143 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
144 * nr_kws will be 3(KW0, KW1 and KW2).
145 */
146 int nr_kws;
147 /* used by packet header fields */
148 struct npc_layer_mdata layer_mdata;
149 };
150
151 struct npc_mcam {
152 struct rsrc_bmap counters;
153 struct mutex lock; /* MCAM entries and counters update lock */
154 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
155 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
156 u16 bmap_entries; /* Number of unreserved MCAM entries */
157 u16 bmap_fcnt; /* MCAM entries free count */
158 u16 *entry2pfvf_map;
159 u16 *entry2cntr_map;
160 u16 *cntr2pfvf_map;
161 u16 *cntr_refcnt;
162 u16 *entry2target_pffunc;
163 u8 keysize; /* MCAM keysize 112/224/448 bits */
164 u8 banks; /* Number of MCAM banks */
165 u8 banks_per_entry;/* Number of keywords in key */
166 u16 banksize; /* Number of MCAM entries in each bank */
167 u16 total_entries; /* Total number of MCAM entries */
168 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
169 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
170 u16 lprio_count;
171 u16 lprio_start;
172 u16 hprio_count;
173 u16 hprio_end;
174 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
175 /* fields present in the generated key */
176 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
177 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
178 u64 tx_features;
179 u64 rx_features;
180 struct list_head mcam_rules;
181 };
182
183 /* Structure for per RVU func info ie PF/VF */
184 struct rvu_pfvf {
185 bool npalf; /* Only one NPALF per RVU_FUNC */
186 bool nixlf; /* Only one NIXLF per RVU_FUNC */
187 u16 sso;
188 u16 ssow;
189 u16 cptlfs;
190 u16 timlfs;
191 u16 cpt1_lfs;
192 u8 cgx_lmac;
193
194 /* Block LF's MSIX vector info */
195 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
196 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
197 u16 *msix_lfmap; /* Vector to block LF mapping */
198
199 /* NPA contexts */
200 struct qmem *aura_ctx;
201 struct qmem *pool_ctx;
202 struct qmem *npa_qints_ctx;
203 unsigned long *aura_bmap;
204 unsigned long *pool_bmap;
205
206 /* NIX contexts */
207 struct qmem *rq_ctx;
208 struct qmem *sq_ctx;
209 struct qmem *cq_ctx;
210 struct qmem *rss_ctx;
211 struct qmem *cq_ints_ctx;
212 struct qmem *nix_qints_ctx;
213 unsigned long *sq_bmap;
214 unsigned long *rq_bmap;
215 unsigned long *cq_bmap;
216
217 u16 rx_chan_base;
218 u16 tx_chan_base;
219 u8 rx_chan_cnt; /* total number of RX channels */
220 u8 tx_chan_cnt; /* total number of TX channels */
221 u16 maxlen;
222 u16 minlen;
223
224 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
225 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
226 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
227
228 /* Broadcast/Multicast/Promisc pkt replication info */
229 u16 bcast_mce_idx;
230 u16 mcast_mce_idx;
231 u16 promisc_mce_idx;
232 struct nix_mce_list bcast_mce_list;
233 struct nix_mce_list mcast_mce_list;
234 struct nix_mce_list promisc_mce_list;
235 bool use_mce_list;
236
237 struct rvu_npc_mcam_rule *def_ucast_rule;
238
239 bool cgx_in_use; /* this PF/VF using CGX? */
240 int cgx_users; /* number of cgx users - used only by PFs */
241
242 int intf_mode;
243 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
244 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
245 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
246 u8 lbkid; /* NIX0/1 lbk link ID */
247 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
248 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
249 unsigned long flags;
250 struct sdp_node_info *sdp_info;
251 };
252
253 enum rvu_pfvf_flags {
254 NIXLF_INITIALIZED = 0,
255 PF_SET_VF_MAC,
256 PF_SET_VF_CFG,
257 PF_SET_VF_TRUSTED,
258 };
259
260 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
261
262 struct nix_txsch {
263 struct rsrc_bmap schq;
264 u8 lvl;
265 #define NIX_TXSCHQ_FREE BIT_ULL(1)
266 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
267 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
268 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
269 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
270 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
271 u32 *pfvf_map;
272 };
273
274 struct nix_mark_format {
275 u8 total;
276 u8 in_use;
277 u32 *cfg;
278 };
279
280 struct npc_pkind {
281 struct rsrc_bmap rsrc;
282 u32 *pfchan_map;
283 };
284
285 struct nix_flowkey {
286 #define NIX_FLOW_KEY_ALG_MAX 32
287 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
288 int in_use;
289 };
290
291 struct nix_lso {
292 u8 total;
293 u8 in_use;
294 };
295
296 struct nix_txvlan {
297 #define NIX_TX_VTAG_DEF_MAX 0x400
298 struct rsrc_bmap rsrc;
299 u16 *entry2pfvf_map;
300 struct mutex rsrc_lock; /* Serialize resource alloc/free */
301 };
302
303 struct nix_ipolicer {
304 struct rsrc_bmap band_prof;
305 u16 *pfvf_map;
306 u16 *match_id;
307 u16 *ref_count;
308 };
309
310 struct nix_hw {
311 int blkaddr;
312 struct rvu *rvu;
313 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
314 struct nix_mcast mcast;
315 struct nix_flowkey flowkey;
316 struct nix_mark_format mark_format;
317 struct nix_lso lso;
318 struct nix_txvlan txvlan;
319 struct nix_ipolicer *ipolicer;
320 u64 *tx_credits;
321 };
322
323 /* RVU block's capabilities or functionality,
324 * which vary by silicon version/skew.
325 */
326 struct hw_cap {
327 /* Transmit side supported functionality */
328 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
329 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
330 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
331 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
332 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
333 bool nix_shaping; /* Is shaping and coloring supported */
334 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
335 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
336 bool nix_rx_multicast; /* Rx packet replication support */
337 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
338 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
339 bool programmable_chans; /* Channels programmable ? */
340 bool ipolicer;
341 };
342
343 struct rvu_hwinfo {
344 u8 total_pfs; /* MAX RVU PFs HW supports */
345 u16 total_vfs; /* Max RVU VFs HW supports */
346 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
347 u8 cgx;
348 u8 lmac_per_cgx;
349 u16 cgx_chan_base; /* CGX base channel number */
350 u16 lbk_chan_base; /* LBK base channel number */
351 u16 sdp_chan_base; /* SDP base channel number */
352 u16 cpt_chan_base; /* CPT base channel number */
353 u8 cgx_links;
354 u8 lbk_links;
355 u8 sdp_links;
356 u8 cpt_links; /* Number of CPT links */
357 u8 npc_kpus; /* No of parser units */
358 u8 npc_pkinds; /* No of port kinds */
359 u8 npc_intfs; /* No of interfaces */
360 u8 npc_kpu_entries; /* No of KPU entries */
361 u16 npc_counters; /* No of match stats counters */
362 u32 lbk_bufsize; /* FIFO size supported by LBK */
363 bool npc_ext_set; /* Extended register set */
364 u64 npc_stat_ena; /* Match stats enable bit */
365
366 struct hw_cap cap;
367 struct rvu_block block[BLK_COUNT]; /* Block info */
368 struct nix_hw *nix;
369 struct rvu *rvu;
370 struct npc_pkind pkind;
371 struct npc_mcam mcam;
372 };
373
374 struct mbox_wq_info {
375 struct otx2_mbox mbox;
376 struct rvu_work *mbox_wrk;
377
378 struct otx2_mbox mbox_up;
379 struct rvu_work *mbox_wrk_up;
380
381 struct workqueue_struct *mbox_wq;
382 };
383
384 struct rvu_fwdata {
385 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
386 #define RVU_FWDATA_VERSION 0x0001
387 u32 header_magic;
388 u32 version; /* version id */
389
390 /* MAC address */
391 #define PF_MACNUM_MAX 32
392 #define VF_MACNUM_MAX 256
393 u64 pf_macs[PF_MACNUM_MAX];
394 u64 vf_macs[VF_MACNUM_MAX];
395 u64 sclk;
396 u64 rclk;
397 u64 mcam_addr;
398 u64 mcam_sz;
399 u64 msixtr_base;
400 #define FWDATA_RESERVED_MEM 1023
401 u64 reserved[FWDATA_RESERVED_MEM];
402 #define CGX_MAX 5
403 #define CGX_LMACS_MAX 4
404 struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
405 /* Do not add new fields below this line */
406 };
407
408 struct ptp;
409
410 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
411 * source where it came from.
412 */
413 struct npc_kpu_profile_adapter {
414 const char *name;
415 u64 version;
416 const struct npc_lt_def_cfg *lt_def;
417 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
418 const struct npc_kpu_profile *kpu; /* array[kpus] */
419 struct npc_mcam_kex *mkex;
420 bool custom;
421 size_t pkinds;
422 size_t kpus;
423 };
424
425 #define RVU_SWITCH_LBK_CHAN 63
426
427 struct rvu_switch {
428 struct mutex switch_lock; /* Serialize flow installation */
429 u32 used_entries;
430 u16 *entry2pcifunc;
431 u16 mode;
432 u16 start_entry;
433 };
434
435 struct rvu {
436 void __iomem *afreg_base;
437 void __iomem *pfreg_base;
438 struct pci_dev *pdev;
439 struct device *dev;
440 struct rvu_hwinfo *hw;
441 struct rvu_pfvf *pf;
442 struct rvu_pfvf *hwvf;
443 struct mutex rsrc_lock; /* Serialize resource alloc/free */
444 int vfs; /* Number of VFs attached to RVU */
445 int nix_blkaddr[MAX_NIX_BLKS];
446
447 /* Mbox */
448 struct mbox_wq_info afpf_wq_info;
449 struct mbox_wq_info afvf_wq_info;
450
451 /* PF FLR */
452 struct rvu_work *flr_wrk;
453 struct workqueue_struct *flr_wq;
454 struct mutex flr_lock; /* Serialize FLRs */
455
456 /* MSI-X */
457 u16 num_vec;
458 char *irq_name;
459 bool *irq_allocated;
460 dma_addr_t msix_base_iova;
461 u64 msixtr_base_phy; /* Register reset value */
462
463 /* CGX */
464 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
465 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
466 u8 cgx_mapped_pfs;
467 u8 cgx_cnt_max; /* CGX port count max */
468 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
469 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
470 * every cgx lmac port
471 */
472 unsigned long pf_notify_bmap; /* Flags for PF notification */
473 void **cgx_idmap; /* cgx id to cgx data map table */
474 struct work_struct cgx_evh_work;
475 struct workqueue_struct *cgx_evh_wq;
476 spinlock_t cgx_evq_lock; /* cgx event queue lock */
477 struct list_head cgx_evq_head; /* cgx event queue head */
478 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
479
480 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
481 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
482
483 /* Firmware data */
484 struct rvu_fwdata *fwdata;
485 void *kpu_fwdata;
486 size_t kpu_fwdata_sz;
487 void __iomem *kpu_prfl_addr;
488
489 /* NPC KPU data */
490 struct npc_kpu_profile_adapter kpu;
491
492 struct ptp *ptp;
493
494 #ifdef CONFIG_DEBUG_FS
495 struct rvu_debugfs rvu_dbg;
496 #endif
497 struct rvu_devlink *rvu_dl;
498
499 /* RVU switch implementation over NPC with DMAC rules */
500 struct rvu_switch rswitch;
501 };
502
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)503 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
504 {
505 writeq(val, rvu->afreg_base + ((block << 28) | offset));
506 }
507
rvu_read64(struct rvu * rvu,u64 block,u64 offset)508 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
509 {
510 return readq(rvu->afreg_base + ((block << 28) | offset));
511 }
512
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)513 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
514 {
515 writeq(val, rvu->pfreg_base + offset);
516 }
517
rvupf_read64(struct rvu * rvu,u64 offset)518 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
519 {
520 return readq(rvu->pfreg_base + offset);
521 }
522
523 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)524 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
525 {
526 struct pci_dev *pdev = rvu->pdev;
527 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
528 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
529 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
530 (pdev->revision == 0x14));
531 }
532
is_rvu_96xx_A0(struct rvu * rvu)533 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
534 {
535 struct pci_dev *pdev = rvu->pdev;
536
537 return (pdev->revision == 0x00);
538 }
539
is_rvu_96xx_B0(struct rvu * rvu)540 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
541 {
542 struct pci_dev *pdev = rvu->pdev;
543
544 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
545 }
546
is_rvu_95xx_A0(struct rvu * rvu)547 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
548 {
549 struct pci_dev *pdev = rvu->pdev;
550
551 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
552 }
553
554 /* REVID for PCIe devices.
555 * Bits 0..1: minor pass, bit 3..2: major pass
556 * bits 7..4: midr id
557 */
558 #define PCI_REVISION_ID_96XX 0x00
559 #define PCI_REVISION_ID_95XX 0x10
560 #define PCI_REVISION_ID_95XXN 0x20
561 #define PCI_REVISION_ID_98XX 0x30
562 #define PCI_REVISION_ID_95XXMM 0x40
563 #define PCI_REVISION_ID_95XXO 0xE0
564
is_rvu_otx2(struct rvu * rvu)565 static inline bool is_rvu_otx2(struct rvu *rvu)
566 {
567 struct pci_dev *pdev = rvu->pdev;
568
569 u8 midr = pdev->revision & 0xF0;
570
571 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
572 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
573 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
574 }
575
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)576 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
577 u8 lmacid, u8 chan)
578 {
579 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
580 u16 cgx_chans = nix_const & 0xFFULL;
581 struct rvu_hwinfo *hw = rvu->hw;
582
583 if (!hw->cap.programmable_chans)
584 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
585
586 return rvu->hw->cgx_chan_base +
587 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
588 }
589
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)590 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
591 u8 chan)
592 {
593 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
594 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
595 struct rvu_hwinfo *hw = rvu->hw;
596
597 if (!hw->cap.programmable_chans)
598 return NIX_CHAN_LBK_CHX(lbkid, chan);
599
600 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
601 }
602
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)603 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
604 {
605 struct rvu_hwinfo *hw = rvu->hw;
606
607 if (!hw->cap.programmable_chans)
608 return NIX_CHAN_SDP_CHX(chan);
609
610 return hw->sdp_chan_base + chan;
611 }
612
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)613 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
614 {
615 return rvu->hw->cpt_chan_base + chan;
616 }
617
is_rvu_supports_nix1(struct rvu * rvu)618 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
619 {
620 struct pci_dev *pdev = rvu->pdev;
621
622 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
623 return true;
624
625 return false;
626 }
627
628 /* Function Prototypes
629 * RVU
630 */
is_afvf(u16 pcifunc)631 static inline bool is_afvf(u16 pcifunc)
632 {
633 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
634 }
635
is_vf(u16 pcifunc)636 static inline bool is_vf(u16 pcifunc)
637 {
638 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
639 }
640
641 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)642 static inline bool is_pffunc_af(u16 pcifunc)
643 {
644 return !pcifunc;
645 }
646
is_rvu_fwdata_valid(struct rvu * rvu)647 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
648 {
649 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
650 (rvu->fwdata->version == RVU_FWDATA_VERSION);
651 }
652
653 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
654 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
655 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
656 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
657 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
658 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
659 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
660 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
661 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
662 int rvu_get_pf(u16 pcifunc);
663 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
664 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
665 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
666 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
667 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
668 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
669 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
670 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
671 int rvu_get_num_lbk_chans(void);
672
673 /* RVU HW reg validation */
674 enum regmap_block {
675 TXSCHQ_HWREGMAP = 0,
676 MAX_HWREGMAP,
677 };
678
679 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
680
681 /* NPA/NIX AQ APIs */
682 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
683 int qsize, int inst_size, int res_size);
684 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
685
686 /* SDP APIs */
687 int rvu_sdp_init(struct rvu *rvu);
688 bool is_sdp_pfvf(u16 pcifunc);
689 bool is_sdp_pf(u16 pcifunc);
690 bool is_sdp_vf(u16 pcifunc);
691
692 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)693 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
694 {
695 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
696 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
697 }
698
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)699 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
700 {
701 *cgx_id = (map >> 4) & 0xF;
702 *lmac_id = (map & 0xF);
703 }
704
is_cgx_vf(struct rvu * rvu,u16 pcifunc)705 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
706 {
707 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
708 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
709 }
710
711 #define M(_name, _id, fn_name, req, rsp) \
712 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
713 MBOX_MESSAGES
714 #undef M
715
716 int rvu_cgx_init(struct rvu *rvu);
717 int rvu_cgx_exit(struct rvu *rvu);
718 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
719 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
720 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
721 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
722 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
723 int rxtxflag, u64 *stat);
724 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
725
726 /* NPA APIs */
727 int rvu_npa_init(struct rvu *rvu);
728 void rvu_npa_freemem(struct rvu *rvu);
729 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
730 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
731 struct npa_aq_enq_rsp *rsp);
732
733 /* NIX APIs */
734 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
735 int rvu_nix_init(struct rvu *rvu);
736 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
737 int blkaddr, u32 cfg);
738 void rvu_nix_freemem(struct rvu *rvu);
739 int rvu_get_nixlf_count(struct rvu *rvu);
740 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
741 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
742 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
743 struct nix_mce_list *mce_list,
744 int mce_idx, int mcam_index, bool add);
745 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
746 struct nix_mce_list **mce_list, int *mce_idx);
747 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
748 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
749 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
750 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
751 struct nix_hw **nix_hw, int *blkaddr);
752 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
753 u16 rq_idx, u16 match_id);
754 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
755 struct nix_cn10k_aq_enq_req *aq_req,
756 struct nix_cn10k_aq_enq_rsp *aq_rsp,
757 u16 pcifunc, u8 ctype, u32 qidx);
758 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
759 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
760 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
761
762 /* NPC APIs */
763 int rvu_npc_init(struct rvu *rvu);
764 void rvu_npc_freemem(struct rvu *rvu);
765 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
766 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
767 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
768 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
769 int nixlf, u64 chan, u8 *mac_addr);
770 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
771 int nixlf, u64 chan, u8 chan_cnt);
772 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
773 bool enable);
774 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
775 int nixlf, u64 chan);
776 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
777 bool enable);
778 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
779 u64 chan);
780 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
781 bool enable);
782 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
783 int nixlf, int type, bool enable);
784 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
785 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
786 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
787 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
788 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
789 int group, int alg_idx, int mcam_index);
790 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
791 int blkaddr, int *alloc_cnt,
792 int *enable_cnt);
793 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
794 int blkaddr, int *alloc_cnt,
795 int *enable_cnt);
796 bool is_npc_intf_tx(u8 intf);
797 bool is_npc_intf_rx(u8 intf);
798 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
799 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
800 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
801 const char *npc_get_field_name(u8 hdr);
802 int npc_get_bank(struct npc_mcam *mcam, int index);
803 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
804 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
805 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
806 int blkaddr, int index, bool enable);
807 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
808 int blkaddr, u16 src, struct mcam_entry *entry,
809 u8 *intf, u8 *ena);
810 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
811 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
812 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
813 void *rvu_first_cgx_pdata(struct rvu *rvu);
814 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
815 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
816 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
817 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
818 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
819 int type);
820 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
821 int index);
822
823 /* CPT APIs */
824 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot);
825
826 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
827 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
828
829 /* CN10K RVU */
830 int rvu_set_channels_base(struct rvu *rvu);
831 void rvu_program_channels(struct rvu *rvu);
832
833 /* CN10K RVU - LMT*/
834 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
835
836 #ifdef CONFIG_DEBUG_FS
837 void rvu_dbg_init(struct rvu *rvu);
838 void rvu_dbg_exit(struct rvu *rvu);
839 #else
rvu_dbg_init(struct rvu * rvu)840 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)841 static inline void rvu_dbg_exit(struct rvu *rvu) {}
842 #endif
843
844 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
845
846 /* RVU Switch */
847 void rvu_switch_enable(struct rvu *rvu);
848 void rvu_switch_disable(struct rvu *rvu);
849 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
850
851 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
852 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
853 u8 shift_dir);
854 #endif /* RVU_H */
855