1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_damage_helper.h>
10 #include <drm/drm_fourcc.h>
11 #include <drm/drm_gem_atomic_helper.h>
12 #include <drm/drm_print.h>
13
14 #include "mdp5_kms.h"
15
16 struct mdp5_plane {
17 struct drm_plane base;
18
19 uint32_t nformats;
20 uint32_t formats[32];
21 };
22 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
23
24 static int mdp5_plane_mode_set(struct drm_plane *plane,
25 struct drm_crtc *crtc, struct drm_framebuffer *fb,
26 struct drm_rect *src, struct drm_rect *dest);
27
get_kms(struct drm_plane * plane)28 static struct mdp5_kms *get_kms(struct drm_plane *plane)
29 {
30 struct msm_drm_private *priv = plane->dev->dev_private;
31 return to_mdp5_kms(to_mdp_kms(priv->kms));
32 }
33
plane_enabled(struct drm_plane_state * state)34 static bool plane_enabled(struct drm_plane_state *state)
35 {
36 return state->visible;
37 }
38
mdp5_plane_destroy(struct drm_plane * plane)39 static void mdp5_plane_destroy(struct drm_plane *plane)
40 {
41 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
42
43 drm_plane_cleanup(plane);
44
45 kfree(mdp5_plane);
46 }
47
48 /* helper to install properties which are common to planes and crtcs */
mdp5_plane_install_properties(struct drm_plane * plane,struct drm_mode_object * obj)49 static void mdp5_plane_install_properties(struct drm_plane *plane,
50 struct drm_mode_object *obj)
51 {
52 drm_plane_create_rotation_property(plane,
53 DRM_MODE_ROTATE_0,
54 DRM_MODE_ROTATE_0 |
55 DRM_MODE_ROTATE_180 |
56 DRM_MODE_REFLECT_X |
57 DRM_MODE_REFLECT_Y);
58 drm_plane_create_alpha_property(plane);
59 drm_plane_create_blend_mode_property(plane,
60 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
61 BIT(DRM_MODE_BLEND_PREMULTI) |
62 BIT(DRM_MODE_BLEND_COVERAGE));
63 drm_plane_create_zpos_property(plane, 1, 1, 255);
64 }
65
66 static void
mdp5_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)67 mdp5_plane_atomic_print_state(struct drm_printer *p,
68 const struct drm_plane_state *state)
69 {
70 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
71 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
72
73 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
74 pstate->hwpipe->name : "(null)");
75 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
76 drm_printf(p, "\tright-hwpipe=%s\n",
77 pstate->r_hwpipe ? pstate->r_hwpipe->name :
78 "(null)");
79 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode);
80 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos);
81 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos);
82 drm_printf(p, "\talpha=%u\n", pstate->base.alpha);
83 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
84 }
85
mdp5_plane_reset(struct drm_plane * plane)86 static void mdp5_plane_reset(struct drm_plane *plane)
87 {
88 struct mdp5_plane_state *mdp5_state;
89
90 if (plane->state)
91 __drm_atomic_helper_plane_destroy_state(plane->state);
92
93 kfree(to_mdp5_plane_state(plane->state));
94 plane->state = NULL;
95 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
96 if (!mdp5_state)
97 return;
98
99 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
100 mdp5_state->base.zpos = STAGE_BASE;
101 else
102 mdp5_state->base.zpos = STAGE0 + drm_plane_index(plane);
103 mdp5_state->base.normalized_zpos = mdp5_state->base.zpos;
104
105 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base);
106 }
107
108 static struct drm_plane_state *
mdp5_plane_duplicate_state(struct drm_plane * plane)109 mdp5_plane_duplicate_state(struct drm_plane *plane)
110 {
111 struct mdp5_plane_state *mdp5_state;
112
113 if (WARN_ON(!plane->state))
114 return NULL;
115
116 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
117 sizeof(*mdp5_state), GFP_KERNEL);
118 if (!mdp5_state)
119 return NULL;
120
121 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
122
123 return &mdp5_state->base;
124 }
125
mdp5_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)126 static void mdp5_plane_destroy_state(struct drm_plane *plane,
127 struct drm_plane_state *state)
128 {
129 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
130
131 __drm_atomic_helper_plane_destroy_state(state);
132
133 kfree(pstate);
134 }
135
136 static const struct drm_plane_funcs mdp5_plane_funcs = {
137 .update_plane = drm_atomic_helper_update_plane,
138 .disable_plane = drm_atomic_helper_disable_plane,
139 .destroy = mdp5_plane_destroy,
140 .reset = mdp5_plane_reset,
141 .atomic_duplicate_state = mdp5_plane_duplicate_state,
142 .atomic_destroy_state = mdp5_plane_destroy_state,
143 .atomic_print_state = mdp5_plane_atomic_print_state,
144 };
145
mdp5_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)146 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
147 struct drm_plane_state *new_state)
148 {
149 struct msm_drm_private *priv = plane->dev->dev_private;
150 struct msm_kms *kms = priv->kms;
151 bool needs_dirtyfb = to_mdp5_plane_state(new_state)->needs_dirtyfb;
152
153 if (!new_state->fb)
154 return 0;
155
156 drm_gem_plane_helper_prepare_fb(plane, new_state);
157
158 return msm_framebuffer_prepare(new_state->fb, kms->aspace, needs_dirtyfb);
159 }
160
mdp5_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)161 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
162 struct drm_plane_state *old_state)
163 {
164 struct mdp5_kms *mdp5_kms = get_kms(plane);
165 struct msm_kms *kms = &mdp5_kms->base.base;
166 struct drm_framebuffer *fb = old_state->fb;
167 bool needed_dirtyfb = to_mdp5_plane_state(old_state)->needs_dirtyfb;
168
169 if (!fb)
170 return;
171
172 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
173 msm_framebuffer_cleanup(fb, kms->aspace, needed_dirtyfb);
174 }
175
mdp5_plane_atomic_check_with_state(struct drm_crtc_state * crtc_state,struct drm_plane_state * state)176 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
177 struct drm_plane_state *state)
178 {
179 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
180 struct drm_plane *plane = state->plane;
181 struct drm_plane_state *old_state = plane->state;
182 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
183 bool new_hwpipe = false;
184 bool need_right_hwpipe = false;
185 uint32_t max_width, max_height;
186 bool out_of_bounds = false;
187 uint32_t caps = 0;
188 int min_scale, max_scale;
189 int ret;
190
191 DBG("%s: check (%d -> %d)", plane->name,
192 plane_enabled(old_state), plane_enabled(state));
193
194 max_width = config->hw->lm.max_width << 16;
195 max_height = config->hw->lm.max_height << 16;
196
197 /* Make sure source dimensions are within bounds. */
198 if (state->src_h > max_height)
199 out_of_bounds = true;
200
201 if (state->src_w > max_width) {
202 /* If source split is supported, we can go up to 2x
203 * the max LM width, but we'd need to stage another
204 * hwpipe to the right LM. So, the drm_plane would
205 * consist of 2 hwpipes.
206 */
207 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
208 (state->src_w <= 2 * max_width))
209 need_right_hwpipe = true;
210 else
211 out_of_bounds = true;
212 }
213
214 if (out_of_bounds) {
215 struct drm_rect src = drm_plane_state_src(state);
216 DBG("Invalid source size "DRM_RECT_FP_FMT,
217 DRM_RECT_FP_ARG(&src));
218 return -ERANGE;
219 }
220
221 min_scale = FRAC_16_16(1, 8);
222 max_scale = FRAC_16_16(8, 1);
223
224 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
225 min_scale, max_scale,
226 true, true);
227 if (ret)
228 return ret;
229
230 if (plane_enabled(state)) {
231 unsigned int rotation;
232 const struct mdp_format *format;
233 struct mdp5_kms *mdp5_kms = get_kms(plane);
234 uint32_t blkcfg = 0;
235
236 format = to_mdp_format(msm_framebuffer_format(state->fb));
237 if (MDP_FORMAT_IS_YUV(format))
238 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
239
240 if (((state->src_w >> 16) != state->crtc_w) ||
241 ((state->src_h >> 16) != state->crtc_h))
242 caps |= MDP_PIPE_CAP_SCALE;
243
244 rotation = drm_rotation_simplify(state->rotation,
245 DRM_MODE_ROTATE_0 |
246 DRM_MODE_REFLECT_X |
247 DRM_MODE_REFLECT_Y);
248
249 if (rotation & DRM_MODE_REFLECT_X)
250 caps |= MDP_PIPE_CAP_HFLIP;
251
252 if (rotation & DRM_MODE_REFLECT_Y)
253 caps |= MDP_PIPE_CAP_VFLIP;
254
255 if (plane->type == DRM_PLANE_TYPE_CURSOR)
256 caps |= MDP_PIPE_CAP_CURSOR;
257
258 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
259 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
260 new_hwpipe = true;
261
262 /*
263 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
264 * or we're switching from 2 hw pipes to 1 hw pipe because the
265 * new src_w can be supported by 1 hw pipe itself.
266 */
267 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
268 (!need_right_hwpipe && mdp5_state->r_hwpipe))
269 new_hwpipe = true;
270
271 if (mdp5_kms->smp) {
272 const struct mdp_format *format =
273 to_mdp_format(msm_framebuffer_format(state->fb));
274
275 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
276 state->src_w >> 16, false);
277
278 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
279 new_hwpipe = true;
280 }
281
282 /* (re)assign hwpipe if needed, otherwise keep old one: */
283 if (new_hwpipe) {
284 /* TODO maybe we want to re-assign hwpipe sometimes
285 * in cases when we no-longer need some caps to make
286 * it available for other planes?
287 */
288 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
289 struct mdp5_hw_pipe *old_right_hwpipe =
290 mdp5_state->r_hwpipe;
291 struct mdp5_hw_pipe *new_hwpipe = NULL;
292 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
293
294 ret = mdp5_pipe_assign(state->state, plane, caps,
295 blkcfg, &new_hwpipe,
296 need_right_hwpipe ?
297 &new_right_hwpipe : NULL);
298 if (ret) {
299 DBG("%s: failed to assign hwpipe(s)!",
300 plane->name);
301 return ret;
302 }
303
304 mdp5_state->hwpipe = new_hwpipe;
305 if (need_right_hwpipe)
306 mdp5_state->r_hwpipe = new_right_hwpipe;
307 else
308 /*
309 * set it to NULL so that the driver knows we
310 * don't have a right hwpipe when committing a
311 * new state
312 */
313 mdp5_state->r_hwpipe = NULL;
314
315
316 ret = mdp5_pipe_release(state->state, old_hwpipe);
317 if (ret)
318 return ret;
319
320 ret = mdp5_pipe_release(state->state, old_right_hwpipe);
321 if (ret)
322 return ret;
323
324 }
325 } else {
326 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe);
327 if (ret)
328 return ret;
329
330 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
331 if (ret)
332 return ret;
333
334 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
335 }
336
337 return 0;
338 }
339
mdp5_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)340 static int mdp5_plane_atomic_check(struct drm_plane *plane,
341 struct drm_atomic_state *state)
342 {
343 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
344 plane);
345 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
346 plane);
347 struct drm_crtc *crtc;
348 struct drm_crtc_state *crtc_state;
349
350 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc;
351 if (!crtc)
352 return 0;
353
354 crtc_state = drm_atomic_get_existing_crtc_state(state,
355 crtc);
356 if (WARN_ON(!crtc_state))
357 return -EINVAL;
358
359 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
360 }
361
mdp5_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)362 static void mdp5_plane_atomic_update(struct drm_plane *plane,
363 struct drm_atomic_state *state)
364 {
365 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
366 plane);
367
368 DBG("%s: update", plane->name);
369
370 if (plane_enabled(new_state)) {
371 int ret;
372
373 ret = mdp5_plane_mode_set(plane,
374 new_state->crtc, new_state->fb,
375 &new_state->src, &new_state->dst);
376 /* atomic_check should have ensured that this doesn't fail */
377 WARN_ON(ret < 0);
378 }
379 }
380
mdp5_plane_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state)381 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
382 struct drm_atomic_state *state)
383 {
384 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
385 plane);
386 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state);
387 struct drm_crtc_state *crtc_state;
388 int min_scale, max_scale;
389 int ret;
390
391 crtc_state = drm_atomic_get_existing_crtc_state(state,
392 new_plane_state->crtc);
393 if (WARN_ON(!crtc_state))
394 return -EINVAL;
395
396 if (!crtc_state->active)
397 return -EINVAL;
398
399 mdp5_state = to_mdp5_plane_state(new_plane_state);
400
401 /* don't use fast path if we don't have a hwpipe allocated yet */
402 if (!mdp5_state->hwpipe)
403 return -EINVAL;
404
405 /* only allow changing of position(crtc x/y or src x/y) in fast path */
406 if (plane->state->crtc != new_plane_state->crtc ||
407 plane->state->src_w != new_plane_state->src_w ||
408 plane->state->src_h != new_plane_state->src_h ||
409 plane->state->crtc_w != new_plane_state->crtc_w ||
410 plane->state->crtc_h != new_plane_state->crtc_h ||
411 !plane->state->fb ||
412 plane->state->fb != new_plane_state->fb)
413 return -EINVAL;
414
415 min_scale = FRAC_16_16(1, 8);
416 max_scale = FRAC_16_16(8, 1);
417
418 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
419 min_scale, max_scale,
420 true, true);
421 if (ret)
422 return ret;
423
424 /*
425 * if the visibility of the plane changes (i.e, if the cursor is
426 * clipped out completely, we can't take the async path because
427 * we need to stage/unstage the plane from the Layer Mixer(s). We
428 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
429 * taking the fast path for both these reasons.
430 */
431 if (new_plane_state->visible != plane->state->visible)
432 return -EINVAL;
433
434 return 0;
435 }
436
mdp5_plane_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)437 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
438 struct drm_atomic_state *state)
439 {
440 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
441 plane);
442 struct drm_framebuffer *old_fb = plane->state->fb;
443
444 plane->state->src_x = new_state->src_x;
445 plane->state->src_y = new_state->src_y;
446 plane->state->crtc_x = new_state->crtc_x;
447 plane->state->crtc_y = new_state->crtc_y;
448
449 if (plane_enabled(new_state)) {
450 struct mdp5_ctl *ctl;
451 struct mdp5_pipeline *pipeline =
452 mdp5_crtc_get_pipeline(new_state->crtc);
453 int ret;
454
455 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
456 &new_state->src, &new_state->dst);
457 WARN_ON(ret < 0);
458
459 ctl = mdp5_crtc_get_ctl(new_state->crtc);
460
461 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
462 }
463
464 *to_mdp5_plane_state(plane->state) =
465 *to_mdp5_plane_state(new_state);
466
467 new_state->fb = old_fb;
468 }
469
470 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
471 .prepare_fb = mdp5_plane_prepare_fb,
472 .cleanup_fb = mdp5_plane_cleanup_fb,
473 .atomic_check = mdp5_plane_atomic_check,
474 .atomic_update = mdp5_plane_atomic_update,
475 .atomic_async_check = mdp5_plane_atomic_async_check,
476 .atomic_async_update = mdp5_plane_atomic_async_update,
477 };
478
set_scanout_locked(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct drm_framebuffer * fb)479 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
480 enum mdp5_pipe pipe,
481 struct drm_framebuffer *fb)
482 {
483 struct msm_kms *kms = &mdp5_kms->base.base;
484
485 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
486 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
487 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
488
489 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
490 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
491 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
492
493 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
494 msm_framebuffer_iova(fb, kms->aspace, 0));
495 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
496 msm_framebuffer_iova(fb, kms->aspace, 1));
497 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
498 msm_framebuffer_iova(fb, kms->aspace, 2));
499 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
500 msm_framebuffer_iova(fb, kms->aspace, 3));
501 }
502
503 /* Note: mdp5_plane->pipe_lock must be locked */
csc_disable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe)504 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
505 {
506 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
507 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
508
509 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
510 }
511
512 /* Note: mdp5_plane->pipe_lock must be locked */
csc_enable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct csc_cfg * csc)513 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
514 struct csc_cfg *csc)
515 {
516 uint32_t i, mode = 0; /* RGB, no CSC */
517 uint32_t *matrix;
518
519 if (unlikely(!csc))
520 return;
521
522 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
523 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
524 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
525 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
526 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
527 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
528
529 matrix = csc->matrix;
530 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
531 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
532 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
533 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
534 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
535 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
536 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
537 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
538 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
539 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
540 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
541 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
542 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
543 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
544
545 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
546 uint32_t *pre_clamp = csc->pre_clamp;
547 uint32_t *post_clamp = csc->post_clamp;
548
549 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
550 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
551 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
552
553 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
554 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
555 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
556
557 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
558 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
559
560 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
561 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
562 }
563 }
564
565 #define PHASE_STEP_SHIFT 21
566 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
567
calc_phase_step(uint32_t src,uint32_t dst,uint32_t * out_phase)568 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
569 {
570 uint32_t unit;
571
572 if (src == 0 || dst == 0)
573 return -EINVAL;
574
575 /*
576 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
577 * where 2^21 represents the unity "1" in fixed-point hardware design.
578 * This leaves 5 bits for the integer part (downscale case):
579 * -> maximum downscale ratio = 0b1_1111 = 31
580 */
581 if (src > (dst * DOWN_SCALE_RATIO_MAX))
582 return -EOVERFLOW;
583
584 unit = 1 << PHASE_STEP_SHIFT;
585 *out_phase = mult_frac(unit, src, dst);
586
587 return 0;
588 }
589
calc_scalex_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasex_steps[COMP_MAX])590 static int calc_scalex_steps(struct drm_plane *plane,
591 uint32_t pixel_format, uint32_t src, uint32_t dest,
592 uint32_t phasex_steps[COMP_MAX])
593 {
594 const struct drm_format_info *info = drm_format_info(pixel_format);
595 struct mdp5_kms *mdp5_kms = get_kms(plane);
596 struct device *dev = mdp5_kms->dev->dev;
597 uint32_t phasex_step;
598 int ret;
599
600 ret = calc_phase_step(src, dest, &phasex_step);
601 if (ret) {
602 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
603 return ret;
604 }
605
606 phasex_steps[COMP_0] = phasex_step;
607 phasex_steps[COMP_3] = phasex_step;
608 phasex_steps[COMP_1_2] = phasex_step / info->hsub;
609
610 return 0;
611 }
612
calc_scaley_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasey_steps[COMP_MAX])613 static int calc_scaley_steps(struct drm_plane *plane,
614 uint32_t pixel_format, uint32_t src, uint32_t dest,
615 uint32_t phasey_steps[COMP_MAX])
616 {
617 const struct drm_format_info *info = drm_format_info(pixel_format);
618 struct mdp5_kms *mdp5_kms = get_kms(plane);
619 struct device *dev = mdp5_kms->dev->dev;
620 uint32_t phasey_step;
621 int ret;
622
623 ret = calc_phase_step(src, dest, &phasey_step);
624 if (ret) {
625 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
626 return ret;
627 }
628
629 phasey_steps[COMP_0] = phasey_step;
630 phasey_steps[COMP_3] = phasey_step;
631 phasey_steps[COMP_1_2] = phasey_step / info->vsub;
632
633 return 0;
634 }
635
get_scale_config(const struct mdp_format * format,uint32_t src,uint32_t dst,bool horz)636 static uint32_t get_scale_config(const struct mdp_format *format,
637 uint32_t src, uint32_t dst, bool horz)
638 {
639 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
640 bool scaling = format->is_yuv ? true : (src != dst);
641 uint32_t sub;
642 uint32_t ya_filter, uv_filter;
643 bool yuv = format->is_yuv;
644
645 if (!scaling)
646 return 0;
647
648 if (yuv) {
649 sub = horz ? info->hsub : info->vsub;
650 uv_filter = ((src / sub) <= dst) ?
651 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
652 }
653 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
654
655 if (horz)
656 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
657 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
658 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
659 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
660 else
661 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
662 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
663 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
664 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
665 }
666
calc_pixel_ext(const struct mdp_format * format,uint32_t src,uint32_t dst,uint32_t phase_step[2],int pix_ext_edge1[COMP_MAX],int pix_ext_edge2[COMP_MAX],bool horz)667 static void calc_pixel_ext(const struct mdp_format *format,
668 uint32_t src, uint32_t dst, uint32_t phase_step[2],
669 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
670 bool horz)
671 {
672 bool scaling = format->is_yuv ? true : (src != dst);
673 int i;
674
675 /*
676 * Note:
677 * We assume here that:
678 * 1. PCMN filter is used for downscale
679 * 2. bilinear filter is used for upscale
680 * 3. we are in a single pipe configuration
681 */
682
683 for (i = 0; i < COMP_MAX; i++) {
684 pix_ext_edge1[i] = 0;
685 pix_ext_edge2[i] = scaling ? 1 : 0;
686 }
687 }
688
mdp5_write_pixel_ext(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,const struct mdp_format * format,uint32_t src_w,int pe_left[COMP_MAX],int pe_right[COMP_MAX],uint32_t src_h,int pe_top[COMP_MAX],int pe_bottom[COMP_MAX])689 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
690 const struct mdp_format *format,
691 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
692 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
693 {
694 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
695 uint32_t lr, tb, req;
696 int i;
697
698 for (i = 0; i < COMP_MAX; i++) {
699 uint32_t roi_w = src_w;
700 uint32_t roi_h = src_h;
701
702 if (format->is_yuv && i == COMP_1_2) {
703 roi_w /= info->hsub;
704 roi_h /= info->vsub;
705 }
706
707 lr = (pe_left[i] >= 0) ?
708 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
709 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
710
711 lr |= (pe_right[i] >= 0) ?
712 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
713 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
714
715 tb = (pe_top[i] >= 0) ?
716 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
717 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
718
719 tb |= (pe_bottom[i] >= 0) ?
720 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
721 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
722
723 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
724 pe_left[i] + pe_right[i]);
725
726 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
727 pe_top[i] + pe_bottom[i]);
728
729 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
730 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
731 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
732
733 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
734 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
735 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
736 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
737 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
738 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
739
740 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
741 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
742 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
743 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
744 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
745 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
746 }
747 }
748
749 struct pixel_ext {
750 int left[COMP_MAX];
751 int right[COMP_MAX];
752 int top[COMP_MAX];
753 int bottom[COMP_MAX];
754 };
755
756 struct phase_step {
757 u32 x[COMP_MAX];
758 u32 y[COMP_MAX];
759 };
760
mdp5_hwpipe_mode_set(struct mdp5_kms * mdp5_kms,struct mdp5_hw_pipe * hwpipe,struct drm_framebuffer * fb,struct phase_step * step,struct pixel_ext * pe,u32 scale_config,u32 hdecm,u32 vdecm,bool hflip,bool vflip,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_img_w,u32 src_img_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h)761 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
762 struct mdp5_hw_pipe *hwpipe,
763 struct drm_framebuffer *fb,
764 struct phase_step *step,
765 struct pixel_ext *pe,
766 u32 scale_config, u32 hdecm, u32 vdecm,
767 bool hflip, bool vflip,
768 int crtc_x, int crtc_y,
769 unsigned int crtc_w, unsigned int crtc_h,
770 u32 src_img_w, u32 src_img_h,
771 u32 src_x, u32 src_y,
772 u32 src_w, u32 src_h)
773 {
774 enum mdp5_pipe pipe = hwpipe->pipe;
775 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
776 const struct mdp_format *format =
777 to_mdp_format(msm_framebuffer_format(fb));
778
779 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
780 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
781 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
782
783 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
784 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
785 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
786
787 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
788 MDP5_PIPE_SRC_XY_X(src_x) |
789 MDP5_PIPE_SRC_XY_Y(src_y));
790
791 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
792 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
793 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
794
795 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
796 MDP5_PIPE_OUT_XY_X(crtc_x) |
797 MDP5_PIPE_OUT_XY_Y(crtc_y));
798
799 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
800 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
801 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
802 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
803 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
804 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
805 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
806 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
807 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
808 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
809 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
810
811 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
812 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
813 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
814 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
815 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
816
817 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
818 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
819 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
820 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
821 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
822
823 /* not using secure mode: */
824 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
825
826 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
827 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
828 src_w, pe->left, pe->right,
829 src_h, pe->top, pe->bottom);
830
831 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
832 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
833 step->x[COMP_0]);
834 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
835 step->y[COMP_0]);
836 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
837 step->x[COMP_1_2]);
838 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
839 step->y[COMP_1_2]);
840 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
841 MDP5_PIPE_DECIMATION_VERT(vdecm) |
842 MDP5_PIPE_DECIMATION_HORZ(hdecm));
843 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
844 scale_config);
845 }
846
847 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
848 if (MDP_FORMAT_IS_YUV(format))
849 csc_enable(mdp5_kms, pipe,
850 mdp_get_default_csc_cfg(CSC_YUV2RGB));
851 else
852 csc_disable(mdp5_kms, pipe);
853 }
854
855 set_scanout_locked(mdp5_kms, pipe, fb);
856 }
857
mdp5_plane_mode_set(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_rect * src,struct drm_rect * dest)858 static int mdp5_plane_mode_set(struct drm_plane *plane,
859 struct drm_crtc *crtc, struct drm_framebuffer *fb,
860 struct drm_rect *src, struct drm_rect *dest)
861 {
862 struct drm_plane_state *pstate = plane->state;
863 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
864 struct mdp5_kms *mdp5_kms = get_kms(plane);
865 enum mdp5_pipe pipe = hwpipe->pipe;
866 struct mdp5_hw_pipe *right_hwpipe;
867 const struct mdp_format *format;
868 uint32_t nplanes, config = 0;
869 struct phase_step step = { { 0 } };
870 struct pixel_ext pe = { { 0 } };
871 uint32_t hdecm = 0, vdecm = 0;
872 uint32_t pix_format;
873 unsigned int rotation;
874 bool vflip, hflip;
875 int crtc_x, crtc_y;
876 unsigned int crtc_w, crtc_h;
877 uint32_t src_x, src_y;
878 uint32_t src_w, src_h;
879 uint32_t src_img_w, src_img_h;
880 int ret;
881
882 nplanes = fb->format->num_planes;
883
884 /* bad formats should already be rejected: */
885 if (WARN_ON(nplanes > pipe2nclients(pipe)))
886 return -EINVAL;
887
888 format = to_mdp_format(msm_framebuffer_format(fb));
889 pix_format = format->base.pixel_format;
890
891 src_x = src->x1;
892 src_y = src->y1;
893 src_w = drm_rect_width(src);
894 src_h = drm_rect_height(src);
895
896 crtc_x = dest->x1;
897 crtc_y = dest->y1;
898 crtc_w = drm_rect_width(dest);
899 crtc_h = drm_rect_height(dest);
900
901 /* src values are in Q16 fixed point, convert to integer: */
902 src_x = src_x >> 16;
903 src_y = src_y >> 16;
904 src_w = src_w >> 16;
905 src_h = src_h >> 16;
906
907 src_img_w = min(fb->width, src_w);
908 src_img_h = min(fb->height, src_h);
909
910 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
911 fb->base.id, src_x, src_y, src_w, src_h,
912 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
913
914 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
915 if (right_hwpipe) {
916 /*
917 * if the plane comprises of 2 hw pipes, assume that the width
918 * is split equally across them. The only parameters that varies
919 * between the 2 pipes are src_x and crtc_x
920 */
921 crtc_w /= 2;
922 src_w /= 2;
923 src_img_w /= 2;
924 }
925
926 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
927 if (ret)
928 return ret;
929
930 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
931 if (ret)
932 return ret;
933
934 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
935 calc_pixel_ext(format, src_w, crtc_w, step.x,
936 pe.left, pe.right, true);
937 calc_pixel_ext(format, src_h, crtc_h, step.y,
938 pe.top, pe.bottom, false);
939 }
940
941 /* TODO calc hdecm, vdecm */
942
943 /* SCALE is used to both scale and up-sample chroma components */
944 config |= get_scale_config(format, src_w, crtc_w, true);
945 config |= get_scale_config(format, src_h, crtc_h, false);
946 DBG("scale config = %x", config);
947
948 rotation = drm_rotation_simplify(pstate->rotation,
949 DRM_MODE_ROTATE_0 |
950 DRM_MODE_REFLECT_X |
951 DRM_MODE_REFLECT_Y);
952 hflip = !!(rotation & DRM_MODE_REFLECT_X);
953 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
954
955 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
956 config, hdecm, vdecm, hflip, vflip,
957 crtc_x, crtc_y, crtc_w, crtc_h,
958 src_img_w, src_img_h,
959 src_x, src_y, src_w, src_h);
960 if (right_hwpipe)
961 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
962 config, hdecm, vdecm, hflip, vflip,
963 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
964 src_img_w, src_img_h,
965 src_x + src_w, src_y, src_w, src_h);
966
967 return ret;
968 }
969
970 /*
971 * Use this func and the one below only after the atomic state has been
972 * successfully swapped
973 */
mdp5_plane_pipe(struct drm_plane * plane)974 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
975 {
976 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
977
978 if (WARN_ON(!pstate->hwpipe))
979 return SSPP_NONE;
980
981 return pstate->hwpipe->pipe;
982 }
983
mdp5_plane_right_pipe(struct drm_plane * plane)984 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
985 {
986 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
987
988 if (!pstate->r_hwpipe)
989 return SSPP_NONE;
990
991 return pstate->r_hwpipe->pipe;
992 }
993
mdp5_plane_get_flush(struct drm_plane * plane)994 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
995 {
996 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
997 u32 mask;
998
999 if (WARN_ON(!pstate->hwpipe))
1000 return 0;
1001
1002 mask = pstate->hwpipe->flush_mask;
1003
1004 if (pstate->r_hwpipe)
1005 mask |= pstate->r_hwpipe->flush_mask;
1006
1007 return mask;
1008 }
1009
1010 /* initialize plane */
mdp5_plane_init(struct drm_device * dev,enum drm_plane_type type)1011 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1012 enum drm_plane_type type)
1013 {
1014 struct drm_plane *plane = NULL;
1015 struct mdp5_plane *mdp5_plane;
1016 int ret;
1017
1018 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1019 if (!mdp5_plane) {
1020 ret = -ENOMEM;
1021 goto fail;
1022 }
1023
1024 plane = &mdp5_plane->base;
1025
1026 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1027 ARRAY_SIZE(mdp5_plane->formats), false);
1028
1029 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1030 mdp5_plane->formats, mdp5_plane->nformats,
1031 NULL, type, NULL);
1032 if (ret)
1033 goto fail;
1034
1035 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1036
1037 mdp5_plane_install_properties(plane, &plane->base);
1038
1039 drm_plane_enable_fb_damage_clips(plane);
1040
1041 return plane;
1042
1043 fail:
1044 if (plane)
1045 mdp5_plane_destroy(plane);
1046
1047 return ERR_PTR(ret);
1048 }
1049