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Searched defs:pll1 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/hisilicon/hibmc/
Dhibmc_drm_de.c284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
/drivers/clk/mxs/
Dclk-imx28.c133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h211 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
/drivers/clk/
Dclk-k210.c1000 struct k210_pll pll1; in k210_clk_early_init() local
/drivers/gpu/drm/tegra/
Dhdmi.c37 u32 pll1; member
Dsor.c366 unsigned int pll1; member