1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Jungchang Tsao <jungchang.tsao@mediatek.com>
5 * Daniel Hsiao <daniel.hsiao@mediatek.com>
6 * PoChun Lin <pochun.lin@mediatek.com>
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12
13 #include "../mtk_vcodec_drv.h"
14 #include "../mtk_vcodec_util.h"
15 #include "../mtk_vcodec_intr.h"
16 #include "../mtk_vcodec_enc.h"
17 #include "../mtk_vcodec_enc_pm.h"
18 #include "../venc_drv_base.h"
19 #include "../venc_ipi_msg.h"
20 #include "../venc_vpu_if.h"
21
22 static const char h264_filler_marker[] = {0x0, 0x0, 0x0, 0x1, 0xc};
23
24 #define H264_FILLER_MARKER_SIZE ARRAY_SIZE(h264_filler_marker)
25 #define VENC_PIC_BITSTREAM_BYTE_CNT 0x0098
26
27 /*
28 * enum venc_h264_frame_type - h264 encoder output bitstream frame type
29 */
30 enum venc_h264_frame_type {
31 VENC_H264_IDR_FRM,
32 VENC_H264_I_FRM,
33 VENC_H264_P_FRM,
34 VENC_H264_B_FRM,
35 };
36
37 /*
38 * enum venc_h264_vpu_work_buf - h264 encoder buffer index
39 */
40 enum venc_h264_vpu_work_buf {
41 VENC_H264_VPU_WORK_BUF_RC_INFO,
42 VENC_H264_VPU_WORK_BUF_RC_CODE,
43 VENC_H264_VPU_WORK_BUF_REC_LUMA,
44 VENC_H264_VPU_WORK_BUF_REC_CHROMA,
45 VENC_H264_VPU_WORK_BUF_REF_LUMA,
46 VENC_H264_VPU_WORK_BUF_REF_CHROMA,
47 VENC_H264_VPU_WORK_BUF_MV_INFO_1,
48 VENC_H264_VPU_WORK_BUF_MV_INFO_2,
49 VENC_H264_VPU_WORK_BUF_SKIP_FRAME,
50 VENC_H264_VPU_WORK_BUF_MAX,
51 };
52
53 /*
54 * enum venc_h264_bs_mode - for bs_mode argument in h264_enc_vpu_encode
55 */
56 enum venc_h264_bs_mode {
57 H264_BS_MODE_SPS,
58 H264_BS_MODE_PPS,
59 H264_BS_MODE_FRAME,
60 };
61
62 /*
63 * struct venc_h264_vpu_config - Structure for h264 encoder configuration
64 * AP-W/R : AP is writer/reader on this item
65 * VPU-W/R: VPU is write/reader on this item
66 * @input_fourcc: input fourcc
67 * @bitrate: target bitrate (in bps)
68 * @pic_w: picture width. Picture size is visible stream resolution, in pixels,
69 * to be used for display purposes; must be smaller or equal to buffer
70 * size.
71 * @pic_h: picture height
72 * @buf_w: buffer width. Buffer size is stream resolution in pixels aligned to
73 * hardware requirements.
74 * @buf_h: buffer height
75 * @gop_size: group of picture size (idr frame)
76 * @intra_period: intra frame period
77 * @framerate: frame rate in fps
78 * @profile: as specified in standard
79 * @level: as specified in standard
80 * @wfd: WFD mode 1:on, 0:off
81 */
82 struct venc_h264_vpu_config {
83 u32 input_fourcc;
84 u32 bitrate;
85 u32 pic_w;
86 u32 pic_h;
87 u32 buf_w;
88 u32 buf_h;
89 u32 gop_size;
90 u32 intra_period;
91 u32 framerate;
92 u32 profile;
93 u32 level;
94 u32 wfd;
95 };
96
97 /*
98 * struct venc_h264_vpu_buf - Structure for buffer information
99 * AP-W/R : AP is writer/reader on this item
100 * VPU-W/R: VPU is write/reader on this item
101 * @iova: IO virtual address
102 * @vpua: VPU side memory addr which is used by RC_CODE
103 * @size: buffer size (in bytes)
104 */
105 struct venc_h264_vpu_buf {
106 u32 iova;
107 u32 vpua;
108 u32 size;
109 };
110
111 /*
112 * struct venc_h264_vsi - Structure for VPU driver control and info share
113 * AP-W/R : AP is writer/reader on this item
114 * VPU-W/R: VPU is write/reader on this item
115 * This structure is allocated in VPU side and shared to AP side.
116 * @config: h264 encoder configuration
117 * @work_bufs: working buffer information in VPU side
118 * The work_bufs here is for storing the 'size' info shared to AP side.
119 * The similar item in struct venc_h264_inst is for memory allocation
120 * in AP side. The AP driver will copy the 'size' from here to the one in
121 * struct mtk_vcodec_mem, then invoke mtk_vcodec_mem_alloc to allocate
122 * the buffer. After that, bypass the 'dma_addr' to the 'iova' field here for
123 * register setting in VPU side.
124 */
125 struct venc_h264_vsi {
126 struct venc_h264_vpu_config config;
127 struct venc_h264_vpu_buf work_bufs[VENC_H264_VPU_WORK_BUF_MAX];
128 };
129
130 /*
131 * struct venc_h264_inst - h264 encoder AP driver instance
132 * @hw_base: h264 encoder hardware register base
133 * @work_bufs: working buffer
134 * @pps_buf: buffer to store the pps bitstream
135 * @work_buf_allocated: working buffer allocated flag
136 * @frm_cnt: encoded frame count
137 * @prepend_hdr: when the v4l2 layer send VENC_SET_PARAM_PREPEND_HEADER cmd
138 * through h264_enc_set_param interface, it will set this flag and prepend the
139 * sps/pps in h264_enc_encode function.
140 * @vpu_inst: VPU instance to exchange information between AP and VPU
141 * @vsi: driver structure allocated by VPU side and shared to AP side for
142 * control and info share
143 * @ctx: context for v4l2 layer integration
144 */
145 struct venc_h264_inst {
146 void __iomem *hw_base;
147 struct mtk_vcodec_mem work_bufs[VENC_H264_VPU_WORK_BUF_MAX];
148 struct mtk_vcodec_mem pps_buf;
149 bool work_buf_allocated;
150 unsigned int frm_cnt;
151 unsigned int skip_frm_cnt;
152 unsigned int prepend_hdr;
153 struct venc_vpu_inst vpu_inst;
154 struct venc_h264_vsi *vsi;
155 struct mtk_vcodec_ctx *ctx;
156 };
157
h264_read_reg(struct venc_h264_inst * inst,u32 addr)158 static inline u32 h264_read_reg(struct venc_h264_inst *inst, u32 addr)
159 {
160 return readl(inst->hw_base + addr);
161 }
162
h264_get_profile(struct venc_h264_inst * inst,unsigned int profile)163 static unsigned int h264_get_profile(struct venc_h264_inst *inst,
164 unsigned int profile)
165 {
166 switch (profile) {
167 case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
168 return 66;
169 case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:
170 return 77;
171 case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:
172 return 100;
173 case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:
174 mtk_vcodec_err(inst, "unsupported CONSTRAINED_BASELINE");
175 return 0;
176 case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED:
177 mtk_vcodec_err(inst, "unsupported EXTENDED");
178 return 0;
179 default:
180 mtk_vcodec_debug(inst, "unsupported profile %d", profile);
181 return 100;
182 }
183 }
184
h264_get_level(struct venc_h264_inst * inst,unsigned int level)185 static unsigned int h264_get_level(struct venc_h264_inst *inst,
186 unsigned int level)
187 {
188 switch (level) {
189 case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
190 mtk_vcodec_err(inst, "unsupported 1B");
191 return 0;
192 case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
193 return 10;
194 case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
195 return 11;
196 case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
197 return 12;
198 case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
199 return 13;
200 case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
201 return 20;
202 case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
203 return 21;
204 case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
205 return 22;
206 case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
207 return 30;
208 case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
209 return 31;
210 case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
211 return 32;
212 case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
213 return 40;
214 case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
215 return 41;
216 case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
217 return 42;
218 case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
219 return 50;
220 case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
221 return 51;
222 default:
223 mtk_vcodec_debug(inst, "unsupported level %d", level);
224 return 31;
225 }
226 }
227
h264_enc_free_work_buf(struct venc_h264_inst * inst)228 static void h264_enc_free_work_buf(struct venc_h264_inst *inst)
229 {
230 int i;
231
232 mtk_vcodec_debug_enter(inst);
233
234 /* Except the SKIP_FRAME buffers,
235 * other buffers need to be freed by AP.
236 */
237 for (i = 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) {
238 if (i != VENC_H264_VPU_WORK_BUF_SKIP_FRAME)
239 mtk_vcodec_mem_free(inst->ctx, &inst->work_bufs[i]);
240 }
241
242 mtk_vcodec_mem_free(inst->ctx, &inst->pps_buf);
243
244 mtk_vcodec_debug_leave(inst);
245 }
246
h264_enc_alloc_work_buf(struct venc_h264_inst * inst)247 static int h264_enc_alloc_work_buf(struct venc_h264_inst *inst)
248 {
249 int i;
250 int ret = 0;
251 struct venc_h264_vpu_buf *wb = inst->vsi->work_bufs;
252
253 mtk_vcodec_debug_enter(inst);
254
255 for (i = 0; i < VENC_H264_VPU_WORK_BUF_MAX; i++) {
256 /*
257 * This 'wb' structure is set by VPU side and shared to AP for
258 * buffer allocation and IO virtual addr mapping. For most of
259 * the buffers, AP will allocate the buffer according to 'size'
260 * field and store the IO virtual addr in 'iova' field. There
261 * are two exceptions:
262 * (1) RC_CODE buffer, it's pre-allocated in the VPU side, and
263 * save the VPU addr in the 'vpua' field. The AP will translate
264 * the VPU addr to the corresponding IO virtual addr and store
265 * in 'iova' field for reg setting in VPU side.
266 * (2) SKIP_FRAME buffer, it's pre-allocated in the VPU side,
267 * and save the VPU addr in the 'vpua' field. The AP will
268 * translate the VPU addr to the corresponding AP side virtual
269 * address and do some memcpy access to move to bitstream buffer
270 * assigned by v4l2 layer.
271 */
272 inst->work_bufs[i].size = wb[i].size;
273 if (i == VENC_H264_VPU_WORK_BUF_SKIP_FRAME) {
274 struct mtk_vcodec_fw *handler;
275
276 handler = inst->vpu_inst.ctx->dev->fw_handler;
277 inst->work_bufs[i].va =
278 mtk_vcodec_fw_map_dm_addr(handler, wb[i].vpua);
279 inst->work_bufs[i].dma_addr = 0;
280 } else {
281 ret = mtk_vcodec_mem_alloc(inst->ctx,
282 &inst->work_bufs[i]);
283 if (ret) {
284 mtk_vcodec_err(inst,
285 "cannot allocate buf %d", i);
286 goto err_alloc;
287 }
288 /*
289 * This RC_CODE is pre-allocated by VPU and saved in VPU
290 * addr. So we need use memcpy to copy RC_CODE from VPU
291 * addr into IO virtual addr in 'iova' field for reg
292 * setting in VPU side.
293 */
294 if (i == VENC_H264_VPU_WORK_BUF_RC_CODE) {
295 struct mtk_vcodec_fw *handler;
296 void *tmp_va;
297
298 handler = inst->vpu_inst.ctx->dev->fw_handler;
299 tmp_va = mtk_vcodec_fw_map_dm_addr(handler,
300 wb[i].vpua);
301 memcpy(inst->work_bufs[i].va, tmp_va,
302 wb[i].size);
303 }
304 }
305 wb[i].iova = inst->work_bufs[i].dma_addr;
306
307 mtk_vcodec_debug(inst,
308 "work_buf[%d] va=0x%p iova=%pad size=%zu",
309 i, inst->work_bufs[i].va,
310 &inst->work_bufs[i].dma_addr,
311 inst->work_bufs[i].size);
312 }
313
314 /* the pps_buf is used by AP side only */
315 inst->pps_buf.size = 128;
316 ret = mtk_vcodec_mem_alloc(inst->ctx, &inst->pps_buf);
317 if (ret) {
318 mtk_vcodec_err(inst, "cannot allocate pps_buf");
319 goto err_alloc;
320 }
321
322 mtk_vcodec_debug_leave(inst);
323
324 return ret;
325
326 err_alloc:
327 h264_enc_free_work_buf(inst);
328
329 return ret;
330 }
331
h264_enc_wait_venc_done(struct venc_h264_inst * inst)332 static unsigned int h264_enc_wait_venc_done(struct venc_h264_inst *inst)
333 {
334 unsigned int irq_status = 0;
335 struct mtk_vcodec_ctx *ctx = (struct mtk_vcodec_ctx *)inst->ctx;
336
337 if (!mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED,
338 WAIT_INTR_TIMEOUT_MS)) {
339 irq_status = ctx->irq_status;
340 mtk_vcodec_debug(inst, "irq_status %x <-", irq_status);
341 }
342 return irq_status;
343 }
344
h264_frame_type(struct venc_h264_inst * inst)345 static int h264_frame_type(struct venc_h264_inst *inst)
346 {
347 if ((inst->vsi->config.gop_size != 0 &&
348 (inst->frm_cnt % inst->vsi->config.gop_size) == 0) ||
349 (inst->frm_cnt == 0 && inst->vsi->config.gop_size == 0)) {
350 /* IDR frame */
351 return VENC_H264_IDR_FRM;
352 } else if ((inst->vsi->config.intra_period != 0 &&
353 (inst->frm_cnt % inst->vsi->config.intra_period) == 0) ||
354 (inst->frm_cnt == 0 && inst->vsi->config.intra_period == 0)) {
355 /* I frame */
356 return VENC_H264_I_FRM;
357 } else {
358 return VENC_H264_P_FRM; /* Note: B frames are not supported */
359 }
360 }
h264_encode_sps(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)361 static int h264_encode_sps(struct venc_h264_inst *inst,
362 struct mtk_vcodec_mem *bs_buf,
363 unsigned int *bs_size)
364 {
365 int ret = 0;
366 unsigned int irq_status;
367
368 mtk_vcodec_debug_enter(inst);
369
370 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_SPS, NULL,
371 bs_buf, bs_size, NULL);
372 if (ret)
373 return ret;
374
375 irq_status = h264_enc_wait_venc_done(inst);
376 if (irq_status != MTK_VENC_IRQ_STATUS_SPS) {
377 mtk_vcodec_err(inst, "expect irq status %d",
378 MTK_VENC_IRQ_STATUS_SPS);
379 return -EINVAL;
380 }
381
382 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
383 mtk_vcodec_debug(inst, "bs size %d <-", *bs_size);
384
385 return ret;
386 }
387
h264_encode_pps(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)388 static int h264_encode_pps(struct venc_h264_inst *inst,
389 struct mtk_vcodec_mem *bs_buf,
390 unsigned int *bs_size)
391 {
392 int ret = 0;
393 unsigned int irq_status;
394
395 mtk_vcodec_debug_enter(inst);
396
397 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_PPS, NULL,
398 bs_buf, bs_size, NULL);
399 if (ret)
400 return ret;
401
402 irq_status = h264_enc_wait_venc_done(inst);
403 if (irq_status != MTK_VENC_IRQ_STATUS_PPS) {
404 mtk_vcodec_err(inst, "expect irq status %d",
405 MTK_VENC_IRQ_STATUS_PPS);
406 return -EINVAL;
407 }
408
409 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
410 mtk_vcodec_debug(inst, "bs size %d <-", *bs_size);
411
412 return ret;
413 }
414
h264_encode_header(struct venc_h264_inst * inst,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)415 static int h264_encode_header(struct venc_h264_inst *inst,
416 struct mtk_vcodec_mem *bs_buf,
417 unsigned int *bs_size)
418 {
419 int ret = 0;
420 unsigned int bs_size_sps;
421 unsigned int bs_size_pps;
422
423 ret = h264_encode_sps(inst, bs_buf, &bs_size_sps);
424 if (ret)
425 return ret;
426
427 ret = h264_encode_pps(inst, &inst->pps_buf, &bs_size_pps);
428 if (ret)
429 return ret;
430
431 memcpy(bs_buf->va + bs_size_sps, inst->pps_buf.va, bs_size_pps);
432 *bs_size = bs_size_sps + bs_size_pps;
433
434 return ret;
435 }
436
h264_encode_frame(struct venc_h264_inst * inst,struct venc_frm_buf * frm_buf,struct mtk_vcodec_mem * bs_buf,unsigned int * bs_size)437 static int h264_encode_frame(struct venc_h264_inst *inst,
438 struct venc_frm_buf *frm_buf,
439 struct mtk_vcodec_mem *bs_buf,
440 unsigned int *bs_size)
441 {
442 int ret = 0;
443 unsigned int irq_status;
444 struct venc_frame_info frame_info;
445
446 mtk_vcodec_debug_enter(inst);
447 mtk_vcodec_debug(inst, "frm_cnt = %d\n ", inst->frm_cnt);
448 frame_info.frm_count = inst->frm_cnt;
449 frame_info.skip_frm_count = inst->skip_frm_cnt;
450 frame_info.frm_type = h264_frame_type(inst);
451 mtk_vcodec_debug(inst, "frm_count = %d,skip_frm_count =%d,frm_type=%d.\n",
452 frame_info.frm_count, frame_info.skip_frm_count,
453 frame_info.frm_type);
454 ret = vpu_enc_encode(&inst->vpu_inst, H264_BS_MODE_FRAME, frm_buf,
455 bs_buf, bs_size, &frame_info);
456 if (ret)
457 return ret;
458
459 /*
460 * skip frame case: The skip frame buffer is composed by vpu side only,
461 * it does not trigger the hw, so skip the wait interrupt operation.
462 */
463 if (inst->vpu_inst.state == VEN_IPI_MSG_ENC_STATE_SKIP) {
464 *bs_size = inst->vpu_inst.bs_size;
465 memcpy(bs_buf->va,
466 inst->work_bufs[VENC_H264_VPU_WORK_BUF_SKIP_FRAME].va,
467 *bs_size);
468 ++inst->frm_cnt;
469 ++inst->skip_frm_cnt;
470 return ret;
471 }
472
473 irq_status = h264_enc_wait_venc_done(inst);
474 if (irq_status != MTK_VENC_IRQ_STATUS_FRM) {
475 mtk_vcodec_err(inst, "irq_status=%d failed", irq_status);
476 return -EIO;
477 }
478
479 *bs_size = h264_read_reg(inst, VENC_PIC_BITSTREAM_BYTE_CNT);
480
481 ++inst->frm_cnt;
482 mtk_vcodec_debug(inst, "frm %d bs_size %d key_frm %d <-",
483 inst->frm_cnt, *bs_size, inst->vpu_inst.is_key_frm);
484
485 return ret;
486 }
487
h264_encode_filler(struct venc_h264_inst * inst,void * buf,int size)488 static void h264_encode_filler(struct venc_h264_inst *inst, void *buf,
489 int size)
490 {
491 unsigned char *p = buf;
492
493 if (size < H264_FILLER_MARKER_SIZE) {
494 mtk_vcodec_err(inst, "filler size too small %d", size);
495 return;
496 }
497
498 memcpy(p, h264_filler_marker, ARRAY_SIZE(h264_filler_marker));
499 size -= H264_FILLER_MARKER_SIZE;
500 p += H264_FILLER_MARKER_SIZE;
501 memset(p, 0xff, size);
502 }
503
h264_enc_init(struct mtk_vcodec_ctx * ctx)504 static int h264_enc_init(struct mtk_vcodec_ctx *ctx)
505 {
506 const bool is_ext = MTK_ENC_CTX_IS_EXT(ctx);
507 int ret = 0;
508 struct venc_h264_inst *inst;
509
510 inst = kzalloc(sizeof(*inst), GFP_KERNEL);
511 if (!inst)
512 return -ENOMEM;
513
514 inst->ctx = ctx;
515 inst->vpu_inst.ctx = ctx;
516 inst->vpu_inst.id = is_ext ? SCP_IPI_VENC_H264 : IPI_VENC_H264;
517 inst->hw_base = mtk_vcodec_get_reg_addr(inst->ctx, VENC_SYS);
518
519 mtk_vcodec_debug_enter(inst);
520
521 ret = vpu_enc_init(&inst->vpu_inst);
522
523 inst->vsi = (struct venc_h264_vsi *)inst->vpu_inst.vsi;
524
525 mtk_vcodec_debug_leave(inst);
526
527 if (ret)
528 kfree(inst);
529 else
530 ctx->drv_handle = inst;
531
532 return ret;
533 }
534
h264_enc_encode(void * handle,enum venc_start_opt opt,struct venc_frm_buf * frm_buf,struct mtk_vcodec_mem * bs_buf,struct venc_done_result * result)535 static int h264_enc_encode(void *handle,
536 enum venc_start_opt opt,
537 struct venc_frm_buf *frm_buf,
538 struct mtk_vcodec_mem *bs_buf,
539 struct venc_done_result *result)
540 {
541 int ret = 0;
542 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
543 struct mtk_vcodec_ctx *ctx = inst->ctx;
544
545 mtk_vcodec_debug(inst, "opt %d ->", opt);
546
547 enable_irq(ctx->dev->enc_irq);
548
549 switch (opt) {
550 case VENC_START_OPT_ENCODE_SEQUENCE_HEADER: {
551 unsigned int bs_size_hdr;
552
553 ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
554 if (ret)
555 goto encode_err;
556
557 result->bs_size = bs_size_hdr;
558 result->is_key_frm = false;
559 break;
560 }
561
562 case VENC_START_OPT_ENCODE_FRAME: {
563 int hdr_sz;
564 int hdr_sz_ext;
565 int filler_sz = 0;
566 const int bs_alignment = 128;
567 struct mtk_vcodec_mem tmp_bs_buf;
568 unsigned int bs_size_hdr;
569 unsigned int bs_size_frm;
570
571 if (!inst->prepend_hdr) {
572 ret = h264_encode_frame(inst, frm_buf, bs_buf,
573 &result->bs_size);
574 if (ret)
575 goto encode_err;
576 result->is_key_frm = inst->vpu_inst.is_key_frm;
577 break;
578 }
579
580 mtk_vcodec_debug(inst, "h264_encode_frame prepend SPS/PPS");
581
582 ret = h264_encode_header(inst, bs_buf, &bs_size_hdr);
583 if (ret)
584 goto encode_err;
585
586 hdr_sz = bs_size_hdr;
587 hdr_sz_ext = (hdr_sz & (bs_alignment - 1));
588 if (hdr_sz_ext) {
589 filler_sz = bs_alignment - hdr_sz_ext;
590 if (hdr_sz_ext + H264_FILLER_MARKER_SIZE > bs_alignment)
591 filler_sz += bs_alignment;
592 h264_encode_filler(inst, bs_buf->va + hdr_sz,
593 filler_sz);
594 }
595
596 tmp_bs_buf.va = bs_buf->va + hdr_sz + filler_sz;
597 tmp_bs_buf.dma_addr = bs_buf->dma_addr + hdr_sz + filler_sz;
598 tmp_bs_buf.size = bs_buf->size - (hdr_sz + filler_sz);
599
600 ret = h264_encode_frame(inst, frm_buf, &tmp_bs_buf,
601 &bs_size_frm);
602 if (ret)
603 goto encode_err;
604
605 result->bs_size = hdr_sz + filler_sz + bs_size_frm;
606
607 mtk_vcodec_debug(inst, "hdr %d filler %d frame %d bs %d",
608 hdr_sz, filler_sz, bs_size_frm,
609 result->bs_size);
610
611 inst->prepend_hdr = 0;
612 result->is_key_frm = inst->vpu_inst.is_key_frm;
613 break;
614 }
615
616 default:
617 mtk_vcodec_err(inst, "venc_start_opt %d not supported", opt);
618 ret = -EINVAL;
619 break;
620 }
621
622 encode_err:
623
624 disable_irq(ctx->dev->enc_irq);
625 mtk_vcodec_debug(inst, "opt %d <-", opt);
626
627 return ret;
628 }
629
h264_enc_set_param(void * handle,enum venc_set_param_type type,struct venc_enc_param * enc_prm)630 static int h264_enc_set_param(void *handle,
631 enum venc_set_param_type type,
632 struct venc_enc_param *enc_prm)
633 {
634 int ret = 0;
635 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
636
637 mtk_vcodec_debug(inst, "->type=%d", type);
638
639 switch (type) {
640 case VENC_SET_PARAM_ENC:
641 inst->vsi->config.input_fourcc = enc_prm->input_yuv_fmt;
642 inst->vsi->config.bitrate = enc_prm->bitrate;
643 inst->vsi->config.pic_w = enc_prm->width;
644 inst->vsi->config.pic_h = enc_prm->height;
645 inst->vsi->config.buf_w = enc_prm->buf_width;
646 inst->vsi->config.buf_h = enc_prm->buf_height;
647 inst->vsi->config.gop_size = enc_prm->gop_size;
648 inst->vsi->config.framerate = enc_prm->frm_rate;
649 inst->vsi->config.intra_period = enc_prm->intra_period;
650 inst->vsi->config.profile =
651 h264_get_profile(inst, enc_prm->h264_profile);
652 inst->vsi->config.level =
653 h264_get_level(inst, enc_prm->h264_level);
654 inst->vsi->config.wfd = 0;
655 ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
656 if (ret)
657 break;
658 if (inst->work_buf_allocated) {
659 h264_enc_free_work_buf(inst);
660 inst->work_buf_allocated = false;
661 }
662 ret = h264_enc_alloc_work_buf(inst);
663 if (ret)
664 break;
665 inst->work_buf_allocated = true;
666 break;
667
668 case VENC_SET_PARAM_PREPEND_HEADER:
669 inst->prepend_hdr = 1;
670 mtk_vcodec_debug(inst, "set prepend header mode");
671 break;
672 case VENC_SET_PARAM_FORCE_INTRA:
673 case VENC_SET_PARAM_GOP_SIZE:
674 case VENC_SET_PARAM_INTRA_PERIOD:
675 inst->frm_cnt = 0;
676 inst->skip_frm_cnt = 0;
677 fallthrough;
678 default:
679 ret = vpu_enc_set_param(&inst->vpu_inst, type, enc_prm);
680 break;
681 }
682
683 mtk_vcodec_debug_leave(inst);
684
685 return ret;
686 }
687
h264_enc_deinit(void * handle)688 static int h264_enc_deinit(void *handle)
689 {
690 int ret = 0;
691 struct venc_h264_inst *inst = (struct venc_h264_inst *)handle;
692
693 mtk_vcodec_debug_enter(inst);
694
695 ret = vpu_enc_deinit(&inst->vpu_inst);
696
697 if (inst->work_buf_allocated)
698 h264_enc_free_work_buf(inst);
699
700 mtk_vcodec_debug_leave(inst);
701 kfree(inst);
702
703 return ret;
704 }
705
706 const struct venc_common_if venc_h264_if = {
707 .init = h264_enc_init,
708 .encode = h264_enc_encode,
709 .set_param = h264_enc_set_param,
710 .deinit = h264_enc_deinit,
711 };
712