1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
7
8 #include <asm/bug.h>
9 #include <asm/proc-fns.h>
10
11 #include <asm/memory.h>
12 #include <asm/mte.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
16
17 /*
18 * VMALLOC range.
19 *
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
22 * and fixed mappings
23 */
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (VMEMMAP_START - SZ_256M)
26
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
28
29 #ifndef __ASSEMBLY__
30
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
36
37 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
38 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
39
40 /* Set stride and tlb_level in flush_*_tlb_range */
41 #define flush_pmd_tlb_range(vma, addr, end) \
42 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
43 #define flush_pud_tlb_range(vma, addr, end) \
44 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
45 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
46
47 /*
48 * Outside of a few very special situations (e.g. hibernation), we always
49 * use broadcast TLB invalidation instructions, therefore a spurious page
50 * fault on one CPU which has been handled concurrently by another CPU
51 * does not need to perform additional invalidation.
52 */
53 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
54
55 /*
56 * ZERO_PAGE is a global shared page that is always zero: used
57 * for zero-mapped memory areas etc..
58 */
59 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
60 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
61
62 #define pte_ERROR(e) \
63 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
64
65 /*
66 * Macros to convert between a physical address and its placement in a
67 * page table entry, taking care of 52-bit addresses.
68 */
69 #ifdef CONFIG_ARM64_PA_BITS_52
__pte_to_phys(pte_t pte)70 static inline phys_addr_t __pte_to_phys(pte_t pte)
71 {
72 return (pte_val(pte) & PTE_ADDR_LOW) |
73 ((pte_val(pte) & PTE_ADDR_HIGH) << 36);
74 }
__phys_to_pte_val(phys_addr_t phys)75 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
76 {
77 return (phys | (phys >> 36)) & PTE_ADDR_MASK;
78 }
79 #else
80 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
81 #define __phys_to_pte_val(phys) (phys)
82 #endif
83
84 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
85 #define pfn_pte(pfn,prot) \
86 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
87
88 #define pte_none(pte) (!pte_val(pte))
89 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
90 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
91
92 /*
93 * The following only work if pte_present(). Undefined behaviour otherwise.
94 */
95 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
96 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
97 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
98 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
99 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
100 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
101 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
102 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
103 PTE_ATTRINDX(MT_NORMAL_TAGGED))
104
105 #define pte_cont_addr_end(addr, end) \
106 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
107 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
108 })
109
110 #define pmd_cont_addr_end(addr, end) \
111 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
112 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
113 })
114
115 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
116 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
117 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
118
119 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
120 /*
121 * Execute-only user mappings do not have the PTE_USER bit set. All valid
122 * kernel mappings have the PTE_UXN bit set.
123 */
124 #define pte_valid_not_user(pte) \
125 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
126 /*
127 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
128 * so that we don't erroneously return false for pages that have been
129 * remapped as PROT_NONE but are yet to be flushed from the TLB.
130 * Note that we can't make any assumptions based on the state of the access
131 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
132 * TLB.
133 */
134 #define pte_accessible(mm, pte) \
135 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
136
137 /*
138 * p??_access_permitted() is true for valid user mappings (PTE_USER
139 * bit set, subject to the write permission check). For execute-only
140 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
141 * not set) must return false. PROT_NONE mappings do not have the
142 * PTE_VALID bit set.
143 */
144 #define pte_access_permitted(pte, write) \
145 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
146 #define pmd_access_permitted(pmd, write) \
147 (pte_access_permitted(pmd_pte(pmd), (write)))
148 #define pud_access_permitted(pud, write) \
149 (pte_access_permitted(pud_pte(pud), (write)))
150
clear_pte_bit(pte_t pte,pgprot_t prot)151 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
152 {
153 pte_val(pte) &= ~pgprot_val(prot);
154 return pte;
155 }
156
set_pte_bit(pte_t pte,pgprot_t prot)157 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
158 {
159 pte_val(pte) |= pgprot_val(prot);
160 return pte;
161 }
162
clear_pmd_bit(pmd_t pmd,pgprot_t prot)163 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
164 {
165 pmd_val(pmd) &= ~pgprot_val(prot);
166 return pmd;
167 }
168
set_pmd_bit(pmd_t pmd,pgprot_t prot)169 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
170 {
171 pmd_val(pmd) |= pgprot_val(prot);
172 return pmd;
173 }
174
pte_mkwrite(pte_t pte)175 static inline pte_t pte_mkwrite(pte_t pte)
176 {
177 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
178 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
179 return pte;
180 }
181
pte_mkclean(pte_t pte)182 static inline pte_t pte_mkclean(pte_t pte)
183 {
184 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
185 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
186
187 return pte;
188 }
189
pte_mkdirty(pte_t pte)190 static inline pte_t pte_mkdirty(pte_t pte)
191 {
192 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
193
194 if (pte_write(pte))
195 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
196
197 return pte;
198 }
199
pte_wrprotect(pte_t pte)200 static inline pte_t pte_wrprotect(pte_t pte)
201 {
202 /*
203 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
204 * clear), set the PTE_DIRTY bit.
205 */
206 if (pte_hw_dirty(pte))
207 pte = pte_mkdirty(pte);
208
209 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
210 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
211 return pte;
212 }
213
pte_mkold(pte_t pte)214 static inline pte_t pte_mkold(pte_t pte)
215 {
216 return clear_pte_bit(pte, __pgprot(PTE_AF));
217 }
218
pte_mkyoung(pte_t pte)219 static inline pte_t pte_mkyoung(pte_t pte)
220 {
221 return set_pte_bit(pte, __pgprot(PTE_AF));
222 }
223
pte_mkspecial(pte_t pte)224 static inline pte_t pte_mkspecial(pte_t pte)
225 {
226 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
227 }
228
pte_mkcont(pte_t pte)229 static inline pte_t pte_mkcont(pte_t pte)
230 {
231 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
232 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
233 }
234
pte_mknoncont(pte_t pte)235 static inline pte_t pte_mknoncont(pte_t pte)
236 {
237 return clear_pte_bit(pte, __pgprot(PTE_CONT));
238 }
239
pte_mkpresent(pte_t pte)240 static inline pte_t pte_mkpresent(pte_t pte)
241 {
242 return set_pte_bit(pte, __pgprot(PTE_VALID));
243 }
244
pmd_mkcont(pmd_t pmd)245 static inline pmd_t pmd_mkcont(pmd_t pmd)
246 {
247 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
248 }
249
pte_mkdevmap(pte_t pte)250 static inline pte_t pte_mkdevmap(pte_t pte)
251 {
252 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
253 }
254
set_pte(pte_t * ptep,pte_t pte)255 static inline void set_pte(pte_t *ptep, pte_t pte)
256 {
257 WRITE_ONCE(*ptep, pte);
258
259 /*
260 * Only if the new pte is valid and kernel, otherwise TLB maintenance
261 * or update_mmu_cache() have the necessary barriers.
262 */
263 if (pte_valid_not_user(pte)) {
264 dsb(ishst);
265 isb();
266 }
267 }
268
269 extern void __sync_icache_dcache(pte_t pteval);
270
271 /*
272 * PTE bits configuration in the presence of hardware Dirty Bit Management
273 * (PTE_WRITE == PTE_DBM):
274 *
275 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
276 * 0 0 | 1 0 0
277 * 0 1 | 1 1 0
278 * 1 0 | 1 0 1
279 * 1 1 | 0 1 x
280 *
281 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
282 * the page fault mechanism. Checking the dirty status of a pte becomes:
283 *
284 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
285 */
286
__check_racy_pte_update(struct mm_struct * mm,pte_t * ptep,pte_t pte)287 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
288 pte_t pte)
289 {
290 pte_t old_pte;
291
292 if (!IS_ENABLED(CONFIG_DEBUG_VM))
293 return;
294
295 old_pte = READ_ONCE(*ptep);
296
297 if (!pte_valid(old_pte) || !pte_valid(pte))
298 return;
299 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
300 return;
301
302 /*
303 * Check for potential race with hardware updates of the pte
304 * (ptep_set_access_flags safely changes valid ptes without going
305 * through an invalid entry).
306 */
307 VM_WARN_ONCE(!pte_young(pte),
308 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
309 __func__, pte_val(old_pte), pte_val(pte));
310 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
311 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
312 __func__, pte_val(old_pte), pte_val(pte));
313 }
314
315 #include <asm/android_erratum_pgtable.h>
316
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)317 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
318 pte_t *ptep, pte_t pte)
319 {
320 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
321 __sync_icache_dcache(pte);
322
323 /*
324 * If the PTE would provide user space access to the tags associated
325 * with it then ensure that the MTE tags are synchronised. Although
326 * pte_access_permitted() returns false for exec only mappings, they
327 * don't expose tags (instruction fetches don't check tags).
328 */
329 if (system_supports_mte() && pte_access_permitted(pte, false) &&
330 !pte_special(pte)) {
331 pte_t old_pte = READ_ONCE(*ptep);
332 /*
333 * We only need to synchronise if the new PTE has tags enabled
334 * or if swapping in (in which case another mapping may have
335 * set tags in the past even if this PTE isn't tagged).
336 * (!pte_none() && !pte_present()) is an open coded version of
337 * is_swap_pte()
338 */
339 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
340 mte_sync_tags(old_pte, pte);
341 }
342
343 __check_racy_pte_update(mm, ptep, pte);
344
345 arm64_update_cacheable_aliases(ptep, pte);
346 set_pte(ptep, pte);
347 }
348
349 /*
350 * Huge pte definitions.
351 */
352 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
353
354 /*
355 * Hugetlb definitions.
356 */
357 #define HUGE_MAX_HSTATE 4
358 #define HPAGE_SHIFT PMD_SHIFT
359 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
360 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
361 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
362
pgd_pte(pgd_t pgd)363 static inline pte_t pgd_pte(pgd_t pgd)
364 {
365 return __pte(pgd_val(pgd));
366 }
367
p4d_pte(p4d_t p4d)368 static inline pte_t p4d_pte(p4d_t p4d)
369 {
370 return __pte(p4d_val(p4d));
371 }
372
pud_pte(pud_t pud)373 static inline pte_t pud_pte(pud_t pud)
374 {
375 return __pte(pud_val(pud));
376 }
377
pte_pud(pte_t pte)378 static inline pud_t pte_pud(pte_t pte)
379 {
380 return __pud(pte_val(pte));
381 }
382
pud_pmd(pud_t pud)383 static inline pmd_t pud_pmd(pud_t pud)
384 {
385 return __pmd(pud_val(pud));
386 }
387
pmd_pte(pmd_t pmd)388 static inline pte_t pmd_pte(pmd_t pmd)
389 {
390 return __pte(pmd_val(pmd));
391 }
392
pte_pmd(pte_t pte)393 static inline pmd_t pte_pmd(pte_t pte)
394 {
395 return __pmd(pte_val(pte));
396 }
397
mk_pud_sect_prot(pgprot_t prot)398 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
399 {
400 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
401 }
402
mk_pmd_sect_prot(pgprot_t prot)403 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
404 {
405 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
406 }
407
408 #ifdef CONFIG_NUMA_BALANCING
409 /*
410 * See the comment in include/linux/pgtable.h
411 */
pte_protnone(pte_t pte)412 static inline int pte_protnone(pte_t pte)
413 {
414 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
415 }
416
pmd_protnone(pmd_t pmd)417 static inline int pmd_protnone(pmd_t pmd)
418 {
419 return pte_protnone(pmd_pte(pmd));
420 }
421 #endif
422
423 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
424
pmd_present(pmd_t pmd)425 static inline int pmd_present(pmd_t pmd)
426 {
427 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
428 }
429
430 /*
431 * THP definitions.
432 */
433
434 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_trans_huge(pmd_t pmd)435 static inline int pmd_trans_huge(pmd_t pmd)
436 {
437 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
438 }
439 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
440
441 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
442 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
443 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
444 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
445 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
446 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
447 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
448 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
449 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
450 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
451
pmd_mkinvalid(pmd_t pmd)452 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
453 {
454 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
455 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
456
457 return pmd;
458 }
459
460 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
461
462 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
463
464 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
465
466 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
467 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
468 #endif
pmd_mkdevmap(pmd_t pmd)469 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
470 {
471 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
472 }
473
474 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
475 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
476 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
477 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
478 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
479
480 #define pud_young(pud) pte_young(pud_pte(pud))
481 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
482 #define pud_write(pud) pte_write(pud_pte(pud))
483
484 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
485
486 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
487 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
488 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
489 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
490
491 #ifndef set_pmd_at
492 #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
493 #endif
494
495 #ifndef set_pud_at
496 #define set_pud_at(mm, addr, pudp, pud) set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud))
497 #endif
498
499 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
500 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
501
502 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
503 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
504
505 #define __pgprot_modify(prot,mask,bits) \
506 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
507
508 #define pgprot_nx(prot) \
509 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
510
511 /*
512 * Mark the prot value as uncacheable and unbufferable.
513 */
514 #define pgprot_noncached(prot) \
515 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
516 #define pgprot_writecombine(prot) \
517 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
518 #define pgprot_device(prot) \
519 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
520 #define pgprot_tagged(prot) \
521 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
522 #define pgprot_mhp pgprot_tagged
523 /*
524 * DMA allocations for non-coherent devices use what the Arm architecture calls
525 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
526 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
527 * is intended for MMIO and thus forbids speculation, preserves access size,
528 * requires strict alignment and can also force write responses to come from the
529 * endpoint.
530 */
531 #define pgprot_dmacoherent(prot) \
532 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
533 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
534
535 /*
536 * Mark the prot value as outer cacheable and inner non-cacheable. Non-coherent
537 * devices on a system with support for a system or last level cache use these
538 * attributes to cache allocations in the system cache.
539 */
540 #define pgprot_syscached(prot) \
541 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
542 PTE_ATTRINDX(MT_NORMAL_iNC_oWB) | PTE_PXN | PTE_UXN)
543
544 #define __HAVE_PHYS_MEM_ACCESS_PROT
545 struct file;
546 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
547 unsigned long size, pgprot_t vma_prot);
548
549 #define pmd_none(pmd) (!pmd_val(pmd))
550
551 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
552 PMD_TYPE_TABLE)
553 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
554 PMD_TYPE_SECT)
555 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd))
556 #define pmd_bad(pmd) (!pmd_table(pmd))
557
558 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
559 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
560
561 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
pud_sect(pud_t pud)562 static inline bool pud_sect(pud_t pud) { return false; }
pud_table(pud_t pud)563 static inline bool pud_table(pud_t pud) { return true; }
564 #else
565 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
566 PUD_TYPE_SECT)
567 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
568 PUD_TYPE_TABLE)
569 #endif
570
571 extern pgd_t init_pg_dir[PTRS_PER_PGD];
572 extern pgd_t init_pg_end[];
573 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
574 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
575 extern pgd_t idmap_pg_end[];
576 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
577 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
578
579 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
580
in_swapper_pgdir(void * addr)581 static inline bool in_swapper_pgdir(void *addr)
582 {
583 return ((unsigned long)addr & PAGE_MASK) ==
584 ((unsigned long)swapper_pg_dir & PAGE_MASK);
585 }
586
set_pmd(pmd_t * pmdp,pmd_t pmd)587 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
588 {
589 #ifdef __PAGETABLE_PMD_FOLDED
590 if (in_swapper_pgdir(pmdp)) {
591 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
592 return;
593 }
594 #endif /* __PAGETABLE_PMD_FOLDED */
595
596 WRITE_ONCE(*pmdp, pmd);
597
598 if (pmd_valid(pmd)) {
599 dsb(ishst);
600 isb();
601 }
602 }
603
pmd_clear(pmd_t * pmdp)604 static inline void pmd_clear(pmd_t *pmdp)
605 {
606 set_pmd(pmdp, __pmd(0));
607 }
608
pmd_page_paddr(pmd_t pmd)609 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
610 {
611 return __pmd_to_phys(pmd);
612 }
613
pmd_page_vaddr(pmd_t pmd)614 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
615 {
616 return (unsigned long)__va(pmd_page_paddr(pmd));
617 }
618
619 /* Find an entry in the third-level page table. */
620 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
621
622 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
623 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
624 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
625
626 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
627
628 /* use ONLY for statically allocated translation tables */
629 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
630
631 /*
632 * Conversion functions: convert a page and protection to a page entry,
633 * and a page entry and page directory to the page they refer to.
634 */
635 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
636
637 #if CONFIG_PGTABLE_LEVELS > 2
638
639 #define pmd_ERROR(e) \
640 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
641
642 #define pud_none(pud) (!pud_val(pud))
643 #define pud_bad(pud) (!pud_table(pud))
644 #define pud_present(pud) pte_present(pud_pte(pud))
645 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud))
646 #define pud_valid(pud) pte_valid(pud_pte(pud))
647
set_pud(pud_t * pudp,pud_t pud)648 static inline void set_pud(pud_t *pudp, pud_t pud)
649 {
650 #ifdef __PAGETABLE_PUD_FOLDED
651 if (in_swapper_pgdir(pudp)) {
652 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
653 return;
654 }
655 #endif /* __PAGETABLE_PUD_FOLDED */
656
657 WRITE_ONCE(*pudp, pud);
658
659 if (pud_valid(pud)) {
660 dsb(ishst);
661 isb();
662 }
663 }
664
pud_clear(pud_t * pudp)665 static inline void pud_clear(pud_t *pudp)
666 {
667 set_pud(pudp, __pud(0));
668 }
669
pud_page_paddr(pud_t pud)670 static inline phys_addr_t pud_page_paddr(pud_t pud)
671 {
672 return __pud_to_phys(pud);
673 }
674
pud_pgtable(pud_t pud)675 static inline pmd_t *pud_pgtable(pud_t pud)
676 {
677 return (pmd_t *)__va(pud_page_paddr(pud));
678 }
679
680 /* Find an entry in the second-level page table. */
681 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
682
683 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
684 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
685 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
686
687 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
688
689 /* use ONLY for statically allocated translation tables */
690 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
691
692 #else
693
694 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
695
696 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
697 #define pmd_set_fixmap(addr) NULL
698 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
699 #define pmd_clear_fixmap()
700
701 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
702
703 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
704
705 #if CONFIG_PGTABLE_LEVELS > 3
706
707 #define pud_ERROR(e) \
708 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
709
710 #define p4d_none(p4d) (!p4d_val(p4d))
711 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
712 #define p4d_present(p4d) (p4d_val(p4d))
713
set_p4d(p4d_t * p4dp,p4d_t p4d)714 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
715 {
716 if (in_swapper_pgdir(p4dp)) {
717 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
718 return;
719 }
720
721 WRITE_ONCE(*p4dp, p4d);
722 dsb(ishst);
723 isb();
724 }
725
p4d_clear(p4d_t * p4dp)726 static inline void p4d_clear(p4d_t *p4dp)
727 {
728 set_p4d(p4dp, __p4d(0));
729 }
730
p4d_page_paddr(p4d_t p4d)731 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
732 {
733 return __p4d_to_phys(p4d);
734 }
735
p4d_pgtable(p4d_t p4d)736 static inline pud_t *p4d_pgtable(p4d_t p4d)
737 {
738 return (pud_t *)__va(p4d_page_paddr(p4d));
739 }
740
741 /* Find an entry in the first-level page table. */
742 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
743
744 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
745 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
746 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
747
748 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
749
750 /* use ONLY for statically allocated translation tables */
751 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
752
753 #else
754
755 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
756 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
757
758 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
759 #define pud_set_fixmap(addr) NULL
760 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
761 #define pud_clear_fixmap()
762
763 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
764
765 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
766
767 #define pgd_ERROR(e) \
768 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
769
770 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
771 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
772
pte_modify(pte_t pte,pgprot_t newprot)773 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
774 {
775 /*
776 * Normal and Normal-Tagged are two different memory types and indices
777 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
778 */
779 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
780 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
781 PTE_ATTRINDX_MASK;
782 /* preserve the hardware dirty information */
783 if (pte_hw_dirty(pte))
784 pte = pte_mkdirty(pte);
785 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
786 /*
787 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware
788 * dirtiness again.
789 */
790 if (pte_sw_dirty(pte))
791 pte = pte_mkdirty(pte);
792 return pte;
793 }
794
pmd_modify(pmd_t pmd,pgprot_t newprot)795 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
796 {
797 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
798 }
799
800 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
801 extern int ptep_set_access_flags(struct vm_area_struct *vma,
802 unsigned long address, pte_t *ptep,
803 pte_t entry, int dirty);
804
805 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
806 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)807 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
808 unsigned long address, pmd_t *pmdp,
809 pmd_t entry, int dirty)
810 {
811 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
812 }
813
pud_devmap(pud_t pud)814 static inline int pud_devmap(pud_t pud)
815 {
816 return 0;
817 }
818
pgd_devmap(pgd_t pgd)819 static inline int pgd_devmap(pgd_t pgd)
820 {
821 return 0;
822 }
823 #endif
824
825 /*
826 * Atomic pte/pmd modifications.
827 */
828 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)829 static inline int __ptep_test_and_clear_young(pte_t *ptep)
830 {
831 pte_t old_pte, pte;
832
833 pte = READ_ONCE(*ptep);
834 do {
835 old_pte = pte;
836 pte = pte_mkold(pte);
837 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
838 pte_val(old_pte), pte_val(pte));
839 } while (pte_val(pte) != pte_val(old_pte));
840
841 return pte_young(pte);
842 }
843
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)844 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
845 unsigned long address,
846 pte_t *ptep)
847 {
848 return __ptep_test_and_clear_young(ptep);
849 }
850
851 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
852 extern bool should_flush_tlb_when_young(void);
853
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)854 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
855 unsigned long address, pte_t *ptep)
856 {
857 int young = ptep_test_and_clear_young(vma, address, ptep);
858
859 if (young && should_flush_tlb_when_young()) {
860 /*
861 * We can elide the trailing DSB here since the worst that can
862 * happen is that a CPU continues to use the young entry in its
863 * TLB and we mistakenly reclaim the associated page. The
864 * window for such an event is bounded by the next
865 * context-switch, which provides a DSB to complete the TLB
866 * invalidation.
867 */
868 flush_tlb_page_nosync(vma, address);
869 }
870
871 return young;
872 }
873
874 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
875 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)876 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
877 unsigned long address,
878 pmd_t *pmdp)
879 {
880 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
881 }
882 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
883
884 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)885 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
886 unsigned long address, pte_t *ptep)
887 {
888 arm64_update_cacheable_aliases(ptep, __pte(0));
889 return __pte(xchg_relaxed(&pte_val(*ptep), 0));
890 }
891
892 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
893 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)894 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
895 unsigned long address, pmd_t *pmdp)
896 {
897 return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
898 }
899 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
900
901 /*
902 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
903 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
904 */
905 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)906 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
907 {
908 pte_t old_pte, pte;
909
910 pte = READ_ONCE(*ptep);
911 do {
912 old_pte = pte;
913 pte = pte_wrprotect(pte);
914 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
915 pte_val(old_pte), pte_val(pte));
916 } while (pte_val(pte) != pte_val(old_pte));
917 }
918
919 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
920 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)921 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
922 unsigned long address, pmd_t *pmdp)
923 {
924 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
925 }
926
927 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)928 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
929 unsigned long address, pmd_t *pmdp, pmd_t pmd)
930 {
931 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
932 }
933 #endif
934
935 /*
936 * Encode and decode a swap entry:
937 * bits 0-1: present (must be zero)
938 * bits 2-7: swap type
939 * bits 8-57: swap offset
940 * bit 58: PTE_PROT_NONE (must be zero)
941 */
942 #define __SWP_TYPE_SHIFT 2
943 #define __SWP_TYPE_BITS 6
944 #define __SWP_OFFSET_BITS 50
945 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
946 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
947 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
948
949 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
950 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
951 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
952
953 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
954 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
955
956 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
957 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
958 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
959 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
960
961 /*
962 * Ensure that there are not more swap files than can be encoded in the kernel
963 * PTEs.
964 */
965 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
966
967 extern int kern_addr_valid(unsigned long addr);
968
969 #ifdef CONFIG_ARM64_MTE
970
971 #define __HAVE_ARCH_PREPARE_TO_SWAP
arch_prepare_to_swap(struct page * page)972 static inline int arch_prepare_to_swap(struct page *page)
973 {
974 if (system_supports_mte())
975 return mte_save_tags(page);
976 return 0;
977 }
978
979 #define __HAVE_ARCH_SWAP_INVALIDATE
arch_swap_invalidate_page(int type,pgoff_t offset)980 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
981 {
982 if (system_supports_mte())
983 mte_invalidate_tags(type, offset);
984 }
985
arch_swap_invalidate_area(int type)986 static inline void arch_swap_invalidate_area(int type)
987 {
988 if (system_supports_mte())
989 mte_invalidate_tags_area(type);
990 }
991
992 #define __HAVE_ARCH_SWAP_RESTORE
arch_swap_restore(swp_entry_t entry,struct page * page)993 static inline void arch_swap_restore(swp_entry_t entry, struct page *page)
994 {
995 if (system_supports_mte() && mte_restore_tags(entry, page))
996 set_page_mte_tagged(page);
997 }
998
999 #endif /* CONFIG_ARM64_MTE */
1000
1001 /*
1002 * On AArch64, the cache coherency is handled via the set_pte_at() function.
1003 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)1004 static inline void update_mmu_cache(struct vm_area_struct *vma,
1005 unsigned long addr, pte_t *ptep)
1006 {
1007 /*
1008 * We don't do anything here, so there's a very small chance of
1009 * us retaking a user fault which we just fixed up. The alternative
1010 * is doing a dsb(ishst), but that penalises the fastpath.
1011 */
1012 }
1013
1014 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1015
1016 #ifdef CONFIG_ARM64_PA_BITS_52
1017 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1018 #else
1019 #define phys_to_ttbr(addr) (addr)
1020 #endif
1021
1022 /*
1023 * On arm64 without hardware Access Flag, copying from user will fail because
1024 * the pte is old and cannot be marked young. So we always end up with zeroed
1025 * page after fork() + CoW for pfn mappings. We don't always have a
1026 * hardware-managed access flag on arm64.
1027 */
1028 #define arch_has_hw_pte_young cpu_has_hw_af
1029
1030 /*
1031 * Experimentally, it's cheap to set the access flag in hardware and we
1032 * benefit from prefaulting mappings as 'old' to start with.
1033 */
1034 #define arch_wants_old_prefaulted_pte cpu_has_hw_af
1035
1036 #endif /* !__ASSEMBLY__ */
1037
1038 #endif /* __ASM_PGTABLE_H */
1039