1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell PTP driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/device.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12
13 #include "ptp.h"
14 #include "mbox.h"
15 #include "rvu.h"
16
17 #define DRV_NAME "Marvell PTP Driver"
18
19 #define PCI_DEVID_OCTEONTX2_PTP 0xA00C
20 #define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100
21 #define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200
22 #define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300
23 #define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP 0xB400
24 #define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500
25 #define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600
26 #define PCI_DEVID_OCTEONTX2_RST 0xA085
27 #define PCI_DEVID_CN10K_PTP 0xA09E
28
29 #define PCI_PTP_BAR_NO 0
30 #define PCI_RST_BAR_NO 0
31
32 #define PTP_CLOCK_CFG 0xF00ULL
33 #define PTP_CLOCK_CFG_PTP_EN BIT_ULL(0)
34 #define PTP_CLOCK_LO 0xF08ULL
35 #define PTP_CLOCK_HI 0xF10ULL
36 #define PTP_CLOCK_COMP 0xF18ULL
37
38 #define RST_BOOT 0x1600ULL
39 #define RST_MUL_BITS GENMASK_ULL(38, 33)
40 #define CLOCK_BASE_RATE 50000000ULL
41
42 static struct ptp *first_ptp_block;
43 static const struct pci_device_id ptp_id_table[];
44
get_clock_rate(void)45 static u64 get_clock_rate(void)
46 {
47 u64 cfg, ret = CLOCK_BASE_RATE * 16;
48 struct pci_dev *pdev;
49 void __iomem *base;
50
51 /* To get the input clock frequency with which PTP co-processor
52 * block is running the base frequency(50 MHz) needs to be multiplied
53 * with multiplier bits present in RST_BOOT register of RESET block.
54 * Hence below code gets the multiplier bits from the RESET PCI
55 * device present in the system.
56 */
57 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
58 PCI_DEVID_OCTEONTX2_RST, NULL);
59 if (!pdev)
60 goto error;
61
62 base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO);
63 if (!base)
64 goto error_put_pdev;
65
66 cfg = readq(base + RST_BOOT);
67 ret = CLOCK_BASE_RATE * FIELD_GET(RST_MUL_BITS, cfg);
68
69 iounmap(base);
70
71 error_put_pdev:
72 pci_dev_put(pdev);
73
74 error:
75 return ret;
76 }
77
ptp_get(void)78 struct ptp *ptp_get(void)
79 {
80 struct ptp *ptp = first_ptp_block;
81
82 /* Check PTP block is present in hardware */
83 if (!pci_dev_present(ptp_id_table))
84 return ERR_PTR(-ENODEV);
85 /* Check driver is bound to PTP block */
86 if (!ptp)
87 ptp = ERR_PTR(-EPROBE_DEFER);
88 else
89 pci_dev_get(ptp->pdev);
90
91 return ptp;
92 }
93
ptp_put(struct ptp * ptp)94 void ptp_put(struct ptp *ptp)
95 {
96 if (!ptp)
97 return;
98
99 pci_dev_put(ptp->pdev);
100 }
101
ptp_adjfine(struct ptp * ptp,long scaled_ppm)102 static int ptp_adjfine(struct ptp *ptp, long scaled_ppm)
103 {
104 bool neg_adj = false;
105 u64 comp;
106 u64 adj;
107 s64 ppb;
108
109 if (scaled_ppm < 0) {
110 neg_adj = true;
111 scaled_ppm = -scaled_ppm;
112 }
113
114 /* The hardware adds the clock compensation value to the PTP clock
115 * on every coprocessor clock cycle. Typical convention is that it
116 * represent number of nanosecond betwen each cycle. In this
117 * convention compensation value is in 64 bit fixed-point
118 * representation where upper 32 bits are number of nanoseconds
119 * and lower is fractions of nanosecond.
120 * The scaled_ppm represent the ratio in "parts per million" by which
121 * the compensation value should be corrected.
122 * To calculate new compenstation value we use 64bit fixed point
123 * arithmetic on following formula
124 * comp = tbase + tbase * scaled_ppm / (1M * 2^16)
125 * where tbase is the basic compensation value calculated
126 * initialy in the probe function.
127 */
128 comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
129 /* convert scaled_ppm to ppb */
130 ppb = 1 + scaled_ppm;
131 ppb *= 125;
132 ppb >>= 13;
133 adj = comp * ppb;
134 adj = div_u64(adj, 1000000000ull);
135 comp = neg_adj ? comp - adj : comp + adj;
136
137 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP);
138
139 return 0;
140 }
141
ptp_get_clock(struct ptp * ptp,u64 * clk)142 static int ptp_get_clock(struct ptp *ptp, u64 *clk)
143 {
144 /* Return the current PTP clock */
145 *clk = readq(ptp->reg_base + PTP_CLOCK_HI);
146
147 return 0;
148 }
149
ptp_probe(struct pci_dev * pdev,const struct pci_device_id * ent)150 static int ptp_probe(struct pci_dev *pdev,
151 const struct pci_device_id *ent)
152 {
153 struct device *dev = &pdev->dev;
154 struct ptp *ptp;
155 u64 clock_comp;
156 u64 clock_cfg;
157 int err;
158
159 ptp = devm_kzalloc(dev, sizeof(*ptp), GFP_KERNEL);
160 if (!ptp) {
161 err = -ENOMEM;
162 goto error;
163 }
164
165 ptp->pdev = pdev;
166
167 err = pcim_enable_device(pdev);
168 if (err)
169 goto error_free;
170
171 err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev));
172 if (err)
173 goto error_free;
174
175 ptp->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
176
177 ptp->clock_rate = get_clock_rate();
178
179 /* Enable PTP clock */
180 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
181 clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
182 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
183
184 clock_comp = ((u64)1000000000ull << 32) / ptp->clock_rate;
185 /* Initial compensation value to start the nanosecs counter */
186 writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);
187
188 pci_set_drvdata(pdev, ptp);
189 if (!first_ptp_block)
190 first_ptp_block = ptp;
191
192 return 0;
193
194 error_free:
195 devm_kfree(dev, ptp);
196
197 error:
198 /* For `ptp_get()` we need to differentiate between the case
199 * when the core has not tried to probe this device and the case when
200 * the probe failed. In the later case we pretend that the
201 * initialization was successful and keep the error in
202 * `dev->driver_data`.
203 */
204 pci_set_drvdata(pdev, ERR_PTR(err));
205 if (!first_ptp_block)
206 first_ptp_block = ERR_PTR(err);
207
208 return 0;
209 }
210
ptp_remove(struct pci_dev * pdev)211 static void ptp_remove(struct pci_dev *pdev)
212 {
213 struct ptp *ptp = pci_get_drvdata(pdev);
214 u64 clock_cfg;
215
216 if (IS_ERR_OR_NULL(ptp))
217 return;
218
219 /* Disable PTP clock */
220 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
221 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
222 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG);
223 }
224
225 static const struct pci_device_id ptp_id_table[] = {
226 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
227 PCI_VENDOR_ID_CAVIUM,
228 PCI_SUBSYS_DEVID_OCTX2_98xx_PTP) },
229 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
230 PCI_VENDOR_ID_CAVIUM,
231 PCI_SUBSYS_DEVID_OCTX2_96XX_PTP) },
232 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
233 PCI_VENDOR_ID_CAVIUM,
234 PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) },
235 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
236 PCI_VENDOR_ID_CAVIUM,
237 PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) },
238 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
239 PCI_VENDOR_ID_CAVIUM,
240 PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) },
241 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
242 PCI_VENDOR_ID_CAVIUM,
243 PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) },
244 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) },
245 { 0, }
246 };
247
248 struct pci_driver ptp_driver = {
249 .name = DRV_NAME,
250 .id_table = ptp_id_table,
251 .probe = ptp_probe,
252 .remove = ptp_remove,
253 };
254
rvu_mbox_handler_ptp_op(struct rvu * rvu,struct ptp_req * req,struct ptp_rsp * rsp)255 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req,
256 struct ptp_rsp *rsp)
257 {
258 int err = 0;
259
260 /* This function is the PTP mailbox handler invoked when
261 * called by AF consumers/netdev drivers via mailbox mechanism.
262 * It is used by netdev driver to get the PTP clock and to set
263 * frequency adjustments. Since mailbox can be called without
264 * notion of whether the driver is bound to ptp device below
265 * validation is needed as first step.
266 */
267 if (!rvu->ptp)
268 return -ENODEV;
269
270 switch (req->op) {
271 case PTP_OP_ADJFINE:
272 err = ptp_adjfine(rvu->ptp, req->scaled_ppm);
273 break;
274 case PTP_OP_GET_CLOCK:
275 err = ptp_get_clock(rvu->ptp, &rsp->clk);
276 break;
277 default:
278 err = -EINVAL;
279 break;
280 }
281
282 return err;
283 }
284