1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/types.h>
7 #include <linux/bitops.h>
8 #include <linux/bitfield.h>
9
10 #include "hw.h"
11 #include "core.h"
12 #include "ce.h"
13 #include "hif.h"
14
15 /* Map from pdev index to hw mac index */
ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)16 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx)
17 {
18 switch (pdev_idx) {
19 case 0:
20 return 0;
21 case 1:
22 return 2;
23 case 2:
24 return 1;
25 default:
26 return ATH11K_INVALID_HW_MAC_ID;
27 }
28 }
29
ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)30 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx)
31 {
32 return pdev_idx;
33 }
34
ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)35 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab,
36 struct hal_tcl_data_cmd *tcl_cmd)
37 {
38 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE,
39 true);
40 }
41
ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)42 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab,
43 struct hal_tcl_data_cmd *tcl_cmd)
44 {
45 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
46 true);
47 }
48
ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base * ab,struct hal_tcl_data_cmd * tcl_cmd)49 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab,
50 struct hal_tcl_data_cmd *tcl_cmd)
51 {
52 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE,
53 true);
54 }
55
ath11k_init_wmi_config_qca6390(struct ath11k_base * ab,struct target_resource_config * config)56 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
57 struct target_resource_config *config)
58 {
59 config->num_vdevs = 4;
60 config->num_peers = 16;
61 config->num_tids = 32;
62
63 config->num_offload_peers = 3;
64 config->num_offload_reorder_buffs = 3;
65 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
66 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
67 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
68 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
69 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
70 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
71 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
72 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
73 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
74 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
75 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
76 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
77 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
78 config->num_mcast_groups = 0;
79 config->num_mcast_table_elems = 0;
80 config->mcast2ucast_mode = 0;
81 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
82 config->num_wds_entries = 0;
83 config->dma_burst_size = 0;
84 config->rx_skip_defrag_timeout_dup_detection_check = 0;
85 config->vow_config = TARGET_VOW_CONFIG;
86 config->gtk_offload_max_vdev = 2;
87 config->num_msdu_desc = 0x400;
88 config->beacon_tx_offload_max_vdev = 2;
89 config->rx_batchmode = TARGET_RX_BATCHMODE;
90
91 config->peer_map_unmap_v2_support = 0;
92 config->use_pdev_id = 1;
93 config->max_frag_entries = 0xa;
94 config->num_tdls_vdevs = 0x1;
95 config->num_tdls_conn_table_entries = 8;
96 config->beacon_tx_offload_max_vdev = 0x2;
97 config->num_multicast_filter_entries = 0x20;
98 config->num_wow_filters = 0x16;
99 config->num_keep_alive_pattern = 0;
100 }
101
ath11k_hw_ipq8074_reo_setup(struct ath11k_base * ab)102 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab)
103 {
104 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
105 u32 val;
106 /* Each hash entry uses three bits to map to a particular ring. */
107 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
108 HAL_HASH_ROUTING_RING_SW2 << 3 |
109 HAL_HASH_ROUTING_RING_SW3 << 6 |
110 HAL_HASH_ROUTING_RING_SW4 << 9 |
111 HAL_HASH_ROUTING_RING_SW1 << 12 |
112 HAL_HASH_ROUTING_RING_SW2 << 15 |
113 HAL_HASH_ROUTING_RING_SW3 << 18 |
114 HAL_HASH_ROUTING_RING_SW4 << 21;
115
116 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
117
118 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING;
119 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING,
120 HAL_SRNG_RING_ID_REO2SW1) |
121 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
122 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
123 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
124
125 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
126 HAL_DEFAULT_REO_TIMEOUT_USEC);
127 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
128 HAL_DEFAULT_REO_TIMEOUT_USEC);
129 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
130 HAL_DEFAULT_REO_TIMEOUT_USEC);
131 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
132 HAL_DEFAULT_REO_TIMEOUT_USEC);
133
134 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0,
135 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
136 ring_hash_map));
137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1,
138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
139 ring_hash_map));
140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
142 ring_hash_map));
143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP,
145 ring_hash_map));
146 }
147
ath11k_init_wmi_config_ipq8074(struct ath11k_base * ab,struct target_resource_config * config)148 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
149 struct target_resource_config *config)
150 {
151 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS;
152
153 if (ab->num_radios == 2) {
154 config->num_peers = TARGET_NUM_PEERS(DBS);
155 config->num_tids = TARGET_NUM_TIDS(DBS);
156 } else if (ab->num_radios == 3) {
157 config->num_peers = TARGET_NUM_PEERS(DBS_SBS);
158 config->num_tids = TARGET_NUM_TIDS(DBS_SBS);
159 } else {
160 /* Control should not reach here */
161 config->num_peers = TARGET_NUM_PEERS(SINGLE);
162 config->num_tids = TARGET_NUM_TIDS(SINGLE);
163 }
164 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS;
165 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
166 config->num_peer_keys = TARGET_NUM_PEER_KEYS;
167 config->ast_skid_limit = TARGET_AST_SKID_LIMIT;
168 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
169 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
170 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
171 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
172 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
173 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
174
175 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
176 config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
177 else
178 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
179
180 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
181 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
182 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
183 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
184 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
185 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
186 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
187 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
188 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES;
189 config->dma_burst_size = TARGET_DMA_BURST_SIZE;
190 config->rx_skip_defrag_timeout_dup_detection_check =
191 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
192 config->vow_config = TARGET_VOW_CONFIG;
193 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
194 config->num_msdu_desc = TARGET_NUM_MSDU_DESC;
195 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
196 config->rx_batchmode = TARGET_RX_BATCHMODE;
197 config->peer_map_unmap_v2_support = 1;
198 config->twt_ap_pdev_count = ab->num_radios;
199 config->twt_ap_sta_count = 1000;
200 }
201
ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)202 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw,
203 int mac_id)
204 {
205 return mac_id;
206 }
207
ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params * hw,int mac_id)208 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw,
209 int mac_id)
210 {
211 return 0;
212 }
213
ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params * hw,int mac_id)214 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw,
215 int mac_id)
216 {
217 return 0;
218 }
219
ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params * hw,int mac_id)220 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw,
221 int mac_id)
222 {
223 return mac_id;
224 }
225
ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc * desc)226 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
227 {
228 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU,
229 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
230 }
231
ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc * desc)232 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
233 {
234 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU,
235 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
236 }
237
ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)238 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
239 {
240 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
241 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2));
242 }
243
ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc * desc)244 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
245 {
246 return desc->u.ipq8074.hdr_status;
247 }
248
ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc * desc)249 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
250 {
251 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) &
252 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
253 }
254
ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)255 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
256 {
257 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
258 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
259 }
260
ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc * desc)261 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
262 {
263 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
264 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
265 }
266
ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)267 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
268 {
269 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
270 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2));
271 }
272
ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)273 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
274 {
275 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
276 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
277 }
278
ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)279 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
280 {
281 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
282 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
283 }
284
ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)285 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
286 {
287 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
288 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1));
289 }
290
ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc * desc)291 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
292 {
293 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
294 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1));
295 }
296
ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)297 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
298 {
299 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
300 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
301 }
302
ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)303 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
304 {
305 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
306 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
307 }
308
ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)309 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
310 {
311 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
312 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
313 }
314
ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)315 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
316 {
317 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data);
318 }
319
ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)320 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
321 {
322 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
323 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
324 }
325
ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)326 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
327 {
328 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
329 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3));
330 }
331
ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)332 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
333 {
334 return FIELD_GET(RX_MPDU_START_INFO2_TID,
335 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2));
336 }
337
ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)338 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
339 {
340 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id);
341 }
342
ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)343 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
344 struct hal_rx_desc *ldesc)
345 {
346 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end,
347 sizeof(struct rx_msdu_end_ipq8074));
348 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention,
349 sizeof(struct rx_attention));
350 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end,
351 sizeof(struct rx_mpdu_end));
352 }
353
ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)354 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
355 {
356 return FIELD_GET(HAL_TLV_HDR_TAG,
357 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag));
358 }
359
ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)360 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
361 {
362 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id);
363 }
364
ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)365 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
366 {
367 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1);
368
369 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
370 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
371
372 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info);
373 }
374
375 static
ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc * desc)376 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc)
377 {
378 return &desc->u.ipq8074.attention;
379 }
380
ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)381 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
382 {
383 return &desc->u.ipq8074.msdu_payload[0];
384 }
385
ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc * desc)386 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
387 {
388 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU,
389 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
390 }
391
ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc * desc)392 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
393 {
394 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU,
395 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
396 }
397
ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)398 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
399 {
400 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING,
401 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4));
402 }
403
ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc * desc)404 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
405 {
406 return desc->u.qcn9074.hdr_status;
407 }
408
ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc * desc)409 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
410 {
411 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) &
412 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID;
413 }
414
ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)415 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
416 {
417 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE,
418 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
419 }
420
ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc * desc)421 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc)
422 {
423 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
424 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
425 }
426
ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)427 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
428 {
429 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
430 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2));
431 }
432
ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)433 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
434 {
435 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID,
436 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
437 }
438
ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)439 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
440 {
441 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID,
442 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
443 }
444
ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)445 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
446 {
447 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM,
448 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11));
449 }
450
ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc * desc)451 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
452 {
453 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
454 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1));
455 }
456
ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)457 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
458 {
459 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
460 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
461 }
462
ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)463 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
464 {
465 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
466 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
467 }
468
ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)469 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
470 {
471 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
472 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
473 }
474
ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)475 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
476 {
477 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data);
478 }
479
ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)480 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
481 {
482 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
483 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
484 }
485
ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)486 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
487 {
488 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
489 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3));
490 }
491
ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)492 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
493 {
494 return FIELD_GET(RX_MPDU_START_INFO9_TID,
495 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9));
496 }
497
ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)498 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
499 {
500 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id);
501 }
502
ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)503 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
504 struct hal_rx_desc *ldesc)
505 {
506 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end,
507 sizeof(struct rx_msdu_end_qcn9074));
508 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention,
509 sizeof(struct rx_attention));
510 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end,
511 sizeof(struct rx_mpdu_end));
512 }
513
ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)514 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
515 {
516 return FIELD_GET(HAL_TLV_HDR_TAG,
517 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag));
518 }
519
ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)520 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
521 {
522 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id);
523 }
524
ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)525 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
526 {
527 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1);
528
529 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
530 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
531
532 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info);
533 }
534
535 static
ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc * desc)536 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc)
537 {
538 return &desc->u.qcn9074.attention;
539 }
540
ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)541 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
542 {
543 return &desc->u.qcn9074.msdu_payload[0];
544 }
545
ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc * desc)546 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc)
547 {
548 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855,
549 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
550 }
551
ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc * desc)552 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc)
553 {
554 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855,
555 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
556 }
557
ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc * desc)558 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc)
559 {
560 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING,
561 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2));
562 }
563
ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc * desc)564 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc)
565 {
566 return desc->u.wcn6855.hdr_status;
567 }
568
ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc * desc)569 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc)
570 {
571 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) &
572 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID;
573 }
574
ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc * desc)575 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc)
576 {
577 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE,
578 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
579 }
580
ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc * desc)581 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc)
582 {
583 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT,
584 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
585 }
586
ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc * desc)587 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc)
588 {
589 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT,
590 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2));
591 }
592
ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc * desc)593 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc)
594 {
595 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID,
596 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
597 }
598
ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc * desc)599 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc)
600 {
601 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID,
602 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
603 }
604
ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc * desc)605 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc)
606 {
607 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM,
608 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1));
609 }
610
ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc * desc)611 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc)
612 {
613 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH,
614 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1));
615 }
616
ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc * desc)617 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc)
618 {
619 return FIELD_GET(RX_MSDU_START_INFO3_SGI,
620 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
621 }
622
ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc * desc)623 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc)
624 {
625 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS,
626 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
627 }
628
ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc * desc)629 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc)
630 {
631 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW,
632 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
633 }
634
ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc * desc)635 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc)
636 {
637 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data);
638 }
639
ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc * desc)640 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc)
641 {
642 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE,
643 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
644 }
645
ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc * desc)646 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc)
647 {
648 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP,
649 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3));
650 }
651
ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc * desc)652 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc)
653 {
654 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855,
655 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2));
656 }
657
ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc * desc)658 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc)
659 {
660 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id);
661 }
662
ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc * fdesc,struct hal_rx_desc * ldesc)663 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc,
664 struct hal_rx_desc *ldesc)
665 {
666 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end,
667 sizeof(struct rx_msdu_end_wcn6855));
668 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention,
669 sizeof(struct rx_attention));
670 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end,
671 sizeof(struct rx_mpdu_end));
672 }
673
ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc * desc)674 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc)
675 {
676 return FIELD_GET(HAL_TLV_HDR_TAG,
677 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag));
678 }
679
ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc * desc)680 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc)
681 {
682 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id);
683 }
684
ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc * desc,u16 len)685 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
686 {
687 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1);
688
689 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH;
690 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len);
691
692 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info);
693 }
694
695 static
ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc * desc)696 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc)
697 {
698 return &desc->u.wcn6855.attention;
699 }
700
ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc * desc)701 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc)
702 {
703 return &desc->u.wcn6855.msdu_payload[0];
704 }
705
ath11k_hw_wcn6855_reo_setup(struct ath11k_base * ab)706 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab)
707 {
708 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG;
709 u32 val;
710 /* Each hash entry uses four bits to map to a particular ring. */
711 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 |
712 HAL_HASH_ROUTING_RING_SW2 << 4 |
713 HAL_HASH_ROUTING_RING_SW3 << 8 |
714 HAL_HASH_ROUTING_RING_SW4 << 12 |
715 HAL_HASH_ROUTING_RING_SW1 << 16 |
716 HAL_HASH_ROUTING_RING_SW2 << 20 |
717 HAL_HASH_ROUTING_RING_SW3 << 24 |
718 HAL_HASH_ROUTING_RING_SW4 << 28;
719
720 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE);
721 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) |
722 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1);
723 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val);
724
725 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL);
726 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING;
727 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1);
728 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val);
729
730 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab),
731 HAL_DEFAULT_REO_TIMEOUT_USEC);
732 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab),
733 HAL_DEFAULT_REO_TIMEOUT_USEC);
734 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab),
735 HAL_DEFAULT_REO_TIMEOUT_USEC);
736 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab),
737 HAL_DEFAULT_REO_TIMEOUT_USEC);
738
739 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2,
740 ring_hash_map);
741 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
742 ring_hash_map);
743 }
744
ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 * tlv_data)745 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data)
746 {
747 u16 peer_id = 0;
748 struct hal_rx_mpdu_info *mpdu_info =
749 (struct hal_rx_mpdu_info *)tlv_data;
750
751 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID,
752 __le32_to_cpu(mpdu_info->info0));
753
754 return peer_id;
755 }
756
ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 * tlv_data)757 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data)
758 {
759 u16 peer_id = 0;
760 struct hal_rx_mpdu_info_wcn6855 *mpdu_info =
761 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data;
762
763 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855,
764 __le32_to_cpu(mpdu_info->info0));
765 return peer_id;
766 }
767
768 const struct ath11k_hw_ops ipq8074_ops = {
769 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
770 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
771 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
772 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
773 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
774 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
775 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
776 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
777 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
778 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
779 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
780 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
781 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
782 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
783 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
784 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
785 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
786 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
787 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
788 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
789 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
790 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
791 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
792 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
793 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
794 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
795 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
796 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
797 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
798 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
799 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
800 .reo_setup = ath11k_hw_ipq8074_reo_setup,
801 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
802 };
803
804 const struct ath11k_hw_ops ipq6018_ops = {
805 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
806 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
807 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
808 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
809 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
810 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
811 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
812 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
813 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
814 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
815 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
816 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
817 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
818 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
819 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
820 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
821 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
822 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
823 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
824 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
825 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
826 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
827 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
828 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
829 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
830 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
831 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
832 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
833 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
834 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
835 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
836 .reo_setup = ath11k_hw_ipq8074_reo_setup,
837 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
838 };
839
840 const struct ath11k_hw_ops qca6390_ops = {
841 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
842 .wmi_init_config = ath11k_init_wmi_config_qca6390,
843 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
844 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
845 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable,
846 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu,
847 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu,
848 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes,
849 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status,
850 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid,
851 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type,
852 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type,
853 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl,
854 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld,
855 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid,
856 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no,
857 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len,
858 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi,
859 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs,
860 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw,
861 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq,
862 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type,
863 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss,
864 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid,
865 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id,
866 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end,
867 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag,
868 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id,
869 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len,
870 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention,
871 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload,
872 .reo_setup = ath11k_hw_ipq8074_reo_setup,
873 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
874 };
875
876 const struct ath11k_hw_ops qcn9074_ops = {
877 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id,
878 .wmi_init_config = ath11k_init_wmi_config_ipq8074,
879 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074,
880 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074,
881 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable,
882 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu,
883 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu,
884 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes,
885 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status,
886 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid,
887 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type,
888 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type,
889 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl,
890 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld,
891 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid,
892 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no,
893 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len,
894 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi,
895 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs,
896 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw,
897 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq,
898 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type,
899 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss,
900 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid,
901 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id,
902 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end,
903 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag,
904 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id,
905 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len,
906 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention,
907 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload,
908 .reo_setup = ath11k_hw_ipq8074_reo_setup,
909 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid,
910 };
911
912 const struct ath11k_hw_ops wcn6855_ops = {
913 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id,
914 .wmi_init_config = ath11k_init_wmi_config_qca6390,
915 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390,
916 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390,
917 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable,
918 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu,
919 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu,
920 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes,
921 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status,
922 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid,
923 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type,
924 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type,
925 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl,
926 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld,
927 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid,
928 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no,
929 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len,
930 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi,
931 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs,
932 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw,
933 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq,
934 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type,
935 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss,
936 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid,
937 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id,
938 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end,
939 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag,
940 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id,
941 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len,
942 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention,
943 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload,
944 .reo_setup = ath11k_hw_wcn6855_reo_setup,
945 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid,
946 };
947
948 #define ATH11K_TX_RING_MASK_0 0x1
949 #define ATH11K_TX_RING_MASK_1 0x2
950 #define ATH11K_TX_RING_MASK_2 0x4
951
952 #define ATH11K_RX_RING_MASK_0 0x1
953 #define ATH11K_RX_RING_MASK_1 0x2
954 #define ATH11K_RX_RING_MASK_2 0x4
955 #define ATH11K_RX_RING_MASK_3 0x8
956
957 #define ATH11K_RX_ERR_RING_MASK_0 0x1
958
959 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1
960
961 #define ATH11K_REO_STATUS_RING_MASK_0 0x1
962
963 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1
964 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2
965 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4
966
967 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1
968 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2
969 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4
970
971 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1
972 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2
973 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4
974
975 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = {
976 .tx = {
977 ATH11K_TX_RING_MASK_0,
978 ATH11K_TX_RING_MASK_1,
979 ATH11K_TX_RING_MASK_2,
980 },
981 .rx_mon_status = {
982 0, 0, 0, 0,
983 ATH11K_RX_MON_STATUS_RING_MASK_0,
984 ATH11K_RX_MON_STATUS_RING_MASK_1,
985 ATH11K_RX_MON_STATUS_RING_MASK_2,
986 },
987 .rx = {
988 0, 0, 0, 0, 0, 0, 0,
989 ATH11K_RX_RING_MASK_0,
990 ATH11K_RX_RING_MASK_1,
991 ATH11K_RX_RING_MASK_2,
992 ATH11K_RX_RING_MASK_3,
993 },
994 .rx_err = {
995 ATH11K_RX_ERR_RING_MASK_0,
996 },
997 .rx_wbm_rel = {
998 ATH11K_RX_WBM_REL_RING_MASK_0,
999 },
1000 .reo_status = {
1001 ATH11K_REO_STATUS_RING_MASK_0,
1002 },
1003 .rxdma2host = {
1004 ATH11K_RXDMA2HOST_RING_MASK_0,
1005 ATH11K_RXDMA2HOST_RING_MASK_1,
1006 ATH11K_RXDMA2HOST_RING_MASK_2,
1007 },
1008 .host2rxdma = {
1009 ATH11K_HOST2RXDMA_RING_MASK_0,
1010 ATH11K_HOST2RXDMA_RING_MASK_1,
1011 ATH11K_HOST2RXDMA_RING_MASK_2,
1012 },
1013 };
1014
1015 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = {
1016 .tx = {
1017 ATH11K_TX_RING_MASK_0,
1018 },
1019 .rx_mon_status = {
1020 0, 0, 0, 0,
1021 ATH11K_RX_MON_STATUS_RING_MASK_0,
1022 ATH11K_RX_MON_STATUS_RING_MASK_1,
1023 ATH11K_RX_MON_STATUS_RING_MASK_2,
1024 },
1025 .rx = {
1026 0, 0, 0, 0, 0, 0, 0,
1027 ATH11K_RX_RING_MASK_0,
1028 ATH11K_RX_RING_MASK_1,
1029 ATH11K_RX_RING_MASK_2,
1030 ATH11K_RX_RING_MASK_3,
1031 },
1032 .rx_err = {
1033 ATH11K_RX_ERR_RING_MASK_0,
1034 },
1035 .rx_wbm_rel = {
1036 ATH11K_RX_WBM_REL_RING_MASK_0,
1037 },
1038 .reo_status = {
1039 ATH11K_REO_STATUS_RING_MASK_0,
1040 },
1041 .rxdma2host = {
1042 ATH11K_RXDMA2HOST_RING_MASK_0,
1043 ATH11K_RXDMA2HOST_RING_MASK_1,
1044 ATH11K_RXDMA2HOST_RING_MASK_2,
1045 },
1046 .host2rxdma = {
1047 },
1048 };
1049
1050 /* Target firmware's Copy Engine configuration. */
1051 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = {
1052 /* CE0: host->target HTC control and raw streams */
1053 {
1054 .pipenum = __cpu_to_le32(0),
1055 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1056 .nentries = __cpu_to_le32(32),
1057 .nbytes_max = __cpu_to_le32(2048),
1058 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1059 .reserved = __cpu_to_le32(0),
1060 },
1061
1062 /* CE1: target->host HTT + HTC control */
1063 {
1064 .pipenum = __cpu_to_le32(1),
1065 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1066 .nentries = __cpu_to_le32(32),
1067 .nbytes_max = __cpu_to_le32(2048),
1068 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1069 .reserved = __cpu_to_le32(0),
1070 },
1071
1072 /* CE2: target->host WMI */
1073 {
1074 .pipenum = __cpu_to_le32(2),
1075 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1076 .nentries = __cpu_to_le32(32),
1077 .nbytes_max = __cpu_to_le32(2048),
1078 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1079 .reserved = __cpu_to_le32(0),
1080 },
1081
1082 /* CE3: host->target WMI */
1083 {
1084 .pipenum = __cpu_to_le32(3),
1085 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1086 .nentries = __cpu_to_le32(32),
1087 .nbytes_max = __cpu_to_le32(2048),
1088 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1089 .reserved = __cpu_to_le32(0),
1090 },
1091
1092 /* CE4: host->target HTT */
1093 {
1094 .pipenum = __cpu_to_le32(4),
1095 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1096 .nentries = __cpu_to_le32(256),
1097 .nbytes_max = __cpu_to_le32(256),
1098 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1099 .reserved = __cpu_to_le32(0),
1100 },
1101
1102 /* CE5: target->host Pktlog */
1103 {
1104 .pipenum = __cpu_to_le32(5),
1105 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1106 .nentries = __cpu_to_le32(32),
1107 .nbytes_max = __cpu_to_le32(2048),
1108 .flags = __cpu_to_le32(0),
1109 .reserved = __cpu_to_le32(0),
1110 },
1111
1112 /* CE6: Reserved for target autonomous hif_memcpy */
1113 {
1114 .pipenum = __cpu_to_le32(6),
1115 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1116 .nentries = __cpu_to_le32(32),
1117 .nbytes_max = __cpu_to_le32(65535),
1118 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1119 .reserved = __cpu_to_le32(0),
1120 },
1121
1122 /* CE7 used only by Host */
1123 {
1124 .pipenum = __cpu_to_le32(7),
1125 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1126 .nentries = __cpu_to_le32(32),
1127 .nbytes_max = __cpu_to_le32(2048),
1128 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1129 .reserved = __cpu_to_le32(0),
1130 },
1131
1132 /* CE8 target->host used only by IPA */
1133 {
1134 .pipenum = __cpu_to_le32(8),
1135 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1136 .nentries = __cpu_to_le32(32),
1137 .nbytes_max = __cpu_to_le32(65535),
1138 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1139 .reserved = __cpu_to_le32(0),
1140 },
1141
1142 /* CE9 host->target HTT */
1143 {
1144 .pipenum = __cpu_to_le32(9),
1145 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1146 .nentries = __cpu_to_le32(32),
1147 .nbytes_max = __cpu_to_le32(2048),
1148 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1149 .reserved = __cpu_to_le32(0),
1150 },
1151
1152 /* CE10 target->host HTT */
1153 {
1154 .pipenum = __cpu_to_le32(10),
1155 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1156 .nentries = __cpu_to_le32(0),
1157 .nbytes_max = __cpu_to_le32(0),
1158 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1159 .reserved = __cpu_to_le32(0),
1160 },
1161
1162 /* CE11 Not used */
1163 };
1164
1165 /* Map from service/endpoint to Copy Engine.
1166 * This table is derived from the CE_PCI TABLE, above.
1167 * It is passed to the Target at startup for use by firmware.
1168 */
1169 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = {
1170 {
1171 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1172 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1173 .pipenum = __cpu_to_le32(3),
1174 },
1175 {
1176 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1177 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1178 .pipenum = __cpu_to_le32(2),
1179 },
1180 {
1181 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1182 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1183 .pipenum = __cpu_to_le32(3),
1184 },
1185 {
1186 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1187 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1188 .pipenum = __cpu_to_le32(2),
1189 },
1190 {
1191 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1192 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1193 .pipenum = __cpu_to_le32(3),
1194 },
1195 {
1196 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1197 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1198 .pipenum = __cpu_to_le32(2),
1199 },
1200 {
1201 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1202 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1203 .pipenum = __cpu_to_le32(3),
1204 },
1205 {
1206 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1207 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1208 .pipenum = __cpu_to_le32(2),
1209 },
1210 {
1211 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1212 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1213 .pipenum = __cpu_to_le32(3),
1214 },
1215 {
1216 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1217 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1218 .pipenum = __cpu_to_le32(2),
1219 },
1220 {
1221 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1222 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1223 .pipenum = __cpu_to_le32(7),
1224 },
1225 {
1226 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1227 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1228 .pipenum = __cpu_to_le32(2),
1229 },
1230 {
1231 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1232 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1233 .pipenum = __cpu_to_le32(9),
1234 },
1235 {
1236 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2),
1237 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1238 .pipenum = __cpu_to_le32(2),
1239 },
1240 {
1241 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1242 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1243 .pipenum = __cpu_to_le32(0),
1244 },
1245 {
1246 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1247 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1248 .pipenum = __cpu_to_le32(1),
1249 },
1250 { /* not used */
1251 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1252 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1253 .pipenum = __cpu_to_le32(0),
1254 },
1255 { /* not used */
1256 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1257 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1258 .pipenum = __cpu_to_le32(1),
1259 },
1260 {
1261 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1262 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1263 .pipenum = __cpu_to_le32(4),
1264 },
1265 {
1266 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1267 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1268 .pipenum = __cpu_to_le32(1),
1269 },
1270 {
1271 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1272 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1273 .pipenum = __cpu_to_le32(5),
1274 },
1275
1276 /* (Additions here) */
1277
1278 { /* terminator entry */ }
1279 };
1280
1281 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = {
1282 {
1283 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1284 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1285 .pipenum = __cpu_to_le32(3),
1286 },
1287 {
1288 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1289 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1290 .pipenum = __cpu_to_le32(2),
1291 },
1292 {
1293 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1294 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1295 .pipenum = __cpu_to_le32(3),
1296 },
1297 {
1298 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1299 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1300 .pipenum = __cpu_to_le32(2),
1301 },
1302 {
1303 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1304 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1305 .pipenum = __cpu_to_le32(3),
1306 },
1307 {
1308 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1309 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1310 .pipenum = __cpu_to_le32(2),
1311 },
1312 {
1313 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1314 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1315 .pipenum = __cpu_to_le32(3),
1316 },
1317 {
1318 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1319 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1320 .pipenum = __cpu_to_le32(2),
1321 },
1322 {
1323 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1324 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1325 .pipenum = __cpu_to_le32(3),
1326 },
1327 {
1328 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1329 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1330 .pipenum = __cpu_to_le32(2),
1331 },
1332 {
1333 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1334 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1335 .pipenum = __cpu_to_le32(7),
1336 },
1337 {
1338 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1),
1339 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1340 .pipenum = __cpu_to_le32(2),
1341 },
1342 {
1343 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1344 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1345 .pipenum = __cpu_to_le32(0),
1346 },
1347 {
1348 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1349 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1350 .pipenum = __cpu_to_le32(1),
1351 },
1352 { /* not used */
1353 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1354 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1355 .pipenum = __cpu_to_le32(0),
1356 },
1357 { /* not used */
1358 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1359 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1360 .pipenum = __cpu_to_le32(1),
1361 },
1362 {
1363 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1364 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1365 .pipenum = __cpu_to_le32(4),
1366 },
1367 {
1368 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1369 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1370 .pipenum = __cpu_to_le32(1),
1371 },
1372 {
1373 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1374 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1375 .pipenum = __cpu_to_le32(5),
1376 },
1377
1378 /* (Additions here) */
1379
1380 { /* terminator entry */ }
1381 };
1382
1383 /* Target firmware's Copy Engine configuration. */
1384 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = {
1385 /* CE0: host->target HTC control and raw streams */
1386 {
1387 .pipenum = __cpu_to_le32(0),
1388 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1389 .nentries = __cpu_to_le32(32),
1390 .nbytes_max = __cpu_to_le32(2048),
1391 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1392 .reserved = __cpu_to_le32(0),
1393 },
1394
1395 /* CE1: target->host HTT + HTC control */
1396 {
1397 .pipenum = __cpu_to_le32(1),
1398 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1399 .nentries = __cpu_to_le32(32),
1400 .nbytes_max = __cpu_to_le32(2048),
1401 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1402 .reserved = __cpu_to_le32(0),
1403 },
1404
1405 /* CE2: target->host WMI */
1406 {
1407 .pipenum = __cpu_to_le32(2),
1408 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1409 .nentries = __cpu_to_le32(32),
1410 .nbytes_max = __cpu_to_le32(2048),
1411 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1412 .reserved = __cpu_to_le32(0),
1413 },
1414
1415 /* CE3: host->target WMI */
1416 {
1417 .pipenum = __cpu_to_le32(3),
1418 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1419 .nentries = __cpu_to_le32(32),
1420 .nbytes_max = __cpu_to_le32(2048),
1421 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1422 .reserved = __cpu_to_le32(0),
1423 },
1424
1425 /* CE4: host->target HTT */
1426 {
1427 .pipenum = __cpu_to_le32(4),
1428 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1429 .nentries = __cpu_to_le32(256),
1430 .nbytes_max = __cpu_to_le32(256),
1431 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1432 .reserved = __cpu_to_le32(0),
1433 },
1434
1435 /* CE5: target->host Pktlog */
1436 {
1437 .pipenum = __cpu_to_le32(5),
1438 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1439 .nentries = __cpu_to_le32(32),
1440 .nbytes_max = __cpu_to_le32(2048),
1441 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1442 .reserved = __cpu_to_le32(0),
1443 },
1444
1445 /* CE6: Reserved for target autonomous hif_memcpy */
1446 {
1447 .pipenum = __cpu_to_le32(6),
1448 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1449 .nentries = __cpu_to_le32(32),
1450 .nbytes_max = __cpu_to_le32(16384),
1451 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1452 .reserved = __cpu_to_le32(0),
1453 },
1454
1455 /* CE7 used only by Host */
1456 {
1457 .pipenum = __cpu_to_le32(7),
1458 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1459 .nentries = __cpu_to_le32(0),
1460 .nbytes_max = __cpu_to_le32(0),
1461 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1462 .reserved = __cpu_to_le32(0),
1463 },
1464
1465 /* CE8 target->host used only by IPA */
1466 {
1467 .pipenum = __cpu_to_le32(8),
1468 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1469 .nentries = __cpu_to_le32(32),
1470 .nbytes_max = __cpu_to_le32(16384),
1471 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1472 .reserved = __cpu_to_le32(0),
1473 },
1474 /* CE 9, 10, 11 are used by MHI driver */
1475 };
1476
1477 /* Map from service/endpoint to Copy Engine.
1478 * This table is derived from the CE_PCI TABLE, above.
1479 * It is passed to the Target at startup for use by firmware.
1480 */
1481 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = {
1482 {
1483 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1484 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1485 __cpu_to_le32(3),
1486 },
1487 {
1488 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1489 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1490 __cpu_to_le32(2),
1491 },
1492 {
1493 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1494 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1495 __cpu_to_le32(3),
1496 },
1497 {
1498 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1499 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1500 __cpu_to_le32(2),
1501 },
1502 {
1503 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1504 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1505 __cpu_to_le32(3),
1506 },
1507 {
1508 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1509 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1510 __cpu_to_le32(2),
1511 },
1512 {
1513 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1514 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1515 __cpu_to_le32(3),
1516 },
1517 {
1518 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1519 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1520 __cpu_to_le32(2),
1521 },
1522 {
1523 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1524 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1525 __cpu_to_le32(3),
1526 },
1527 {
1528 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1529 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1530 __cpu_to_le32(2),
1531 },
1532 {
1533 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1534 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1535 __cpu_to_le32(0),
1536 },
1537 {
1538 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1539 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1540 __cpu_to_le32(2),
1541 },
1542 {
1543 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1544 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1545 __cpu_to_le32(4),
1546 },
1547 {
1548 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1549 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1550 __cpu_to_le32(1),
1551 },
1552
1553 /* (Additions here) */
1554
1555 { /* must be last */
1556 __cpu_to_le32(0),
1557 __cpu_to_le32(0),
1558 __cpu_to_le32(0),
1559 },
1560 };
1561
1562 /* Target firmware's Copy Engine configuration. */
1563 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = {
1564 /* CE0: host->target HTC control and raw streams */
1565 {
1566 .pipenum = __cpu_to_le32(0),
1567 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1568 .nentries = __cpu_to_le32(32),
1569 .nbytes_max = __cpu_to_le32(2048),
1570 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1571 .reserved = __cpu_to_le32(0),
1572 },
1573
1574 /* CE1: target->host HTT + HTC control */
1575 {
1576 .pipenum = __cpu_to_le32(1),
1577 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1578 .nentries = __cpu_to_le32(32),
1579 .nbytes_max = __cpu_to_le32(2048),
1580 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1581 .reserved = __cpu_to_le32(0),
1582 },
1583
1584 /* CE2: target->host WMI */
1585 {
1586 .pipenum = __cpu_to_le32(2),
1587 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1588 .nentries = __cpu_to_le32(32),
1589 .nbytes_max = __cpu_to_le32(2048),
1590 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1591 .reserved = __cpu_to_le32(0),
1592 },
1593
1594 /* CE3: host->target WMI */
1595 {
1596 .pipenum = __cpu_to_le32(3),
1597 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1598 .nentries = __cpu_to_le32(32),
1599 .nbytes_max = __cpu_to_le32(2048),
1600 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1601 .reserved = __cpu_to_le32(0),
1602 },
1603
1604 /* CE4: host->target HTT */
1605 {
1606 .pipenum = __cpu_to_le32(4),
1607 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
1608 .nentries = __cpu_to_le32(256),
1609 .nbytes_max = __cpu_to_le32(256),
1610 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1611 .reserved = __cpu_to_le32(0),
1612 },
1613
1614 /* CE5: target->host Pktlog */
1615 {
1616 .pipenum = __cpu_to_le32(5),
1617 .pipedir = __cpu_to_le32(PIPEDIR_IN),
1618 .nentries = __cpu_to_le32(32),
1619 .nbytes_max = __cpu_to_le32(2048),
1620 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1621 .reserved = __cpu_to_le32(0),
1622 },
1623
1624 /* CE6: Reserved for target autonomous hif_memcpy */
1625 {
1626 .pipenum = __cpu_to_le32(6),
1627 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1628 .nentries = __cpu_to_le32(32),
1629 .nbytes_max = __cpu_to_le32(16384),
1630 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1631 .reserved = __cpu_to_le32(0),
1632 },
1633
1634 /* CE7 used only by Host */
1635 {
1636 .pipenum = __cpu_to_le32(7),
1637 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
1638 .nentries = __cpu_to_le32(0),
1639 .nbytes_max = __cpu_to_le32(0),
1640 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
1641 .reserved = __cpu_to_le32(0),
1642 },
1643
1644 /* CE8 target->host used only by IPA */
1645 {
1646 .pipenum = __cpu_to_le32(8),
1647 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
1648 .nentries = __cpu_to_le32(32),
1649 .nbytes_max = __cpu_to_le32(16384),
1650 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
1651 .reserved = __cpu_to_le32(0),
1652 },
1653 /* CE 9, 10, 11 are used by MHI driver */
1654 };
1655
1656 /* Map from service/endpoint to Copy Engine.
1657 * This table is derived from the CE_PCI TABLE, above.
1658 * It is passed to the Target at startup for use by firmware.
1659 */
1660 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = {
1661 {
1662 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1663 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1664 __cpu_to_le32(3),
1665 },
1666 {
1667 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO),
1668 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1669 __cpu_to_le32(2),
1670 },
1671 {
1672 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1673 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1674 __cpu_to_le32(3),
1675 },
1676 {
1677 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK),
1678 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1679 __cpu_to_le32(2),
1680 },
1681 {
1682 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1683 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1684 __cpu_to_le32(3),
1685 },
1686 {
1687 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE),
1688 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1689 __cpu_to_le32(2),
1690 },
1691 {
1692 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1693 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1694 __cpu_to_le32(3),
1695 },
1696 {
1697 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI),
1698 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1699 __cpu_to_le32(2),
1700 },
1701 {
1702 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1703 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1704 __cpu_to_le32(3),
1705 },
1706 {
1707 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL),
1708 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1709 __cpu_to_le32(2),
1710 },
1711 {
1712 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1713 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1714 __cpu_to_le32(0),
1715 },
1716 {
1717 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL),
1718 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1719 __cpu_to_le32(1),
1720 },
1721 {
1722 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1723 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1724 __cpu_to_le32(0),
1725 },
1726 {
1727 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS),
1728 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1729 __cpu_to_le32(1),
1730 },
1731 {
1732 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1733 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
1734 __cpu_to_le32(4),
1735 },
1736 {
1737 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG),
1738 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1739 __cpu_to_le32(1),
1740 },
1741 {
1742 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG),
1743 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
1744 __cpu_to_le32(5),
1745 },
1746
1747 /* (Additions here) */
1748
1749 { /* must be last */
1750 __cpu_to_le32(0),
1751 __cpu_to_le32(0),
1752 __cpu_to_le32(0),
1753 },
1754 };
1755
1756 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = {
1757 .tx = {
1758 ATH11K_TX_RING_MASK_0,
1759 ATH11K_TX_RING_MASK_1,
1760 ATH11K_TX_RING_MASK_2,
1761 },
1762 .rx_mon_status = {
1763 0, 0, 0,
1764 ATH11K_RX_MON_STATUS_RING_MASK_0,
1765 ATH11K_RX_MON_STATUS_RING_MASK_1,
1766 ATH11K_RX_MON_STATUS_RING_MASK_2,
1767 },
1768 .rx = {
1769 0, 0, 0, 0,
1770 ATH11K_RX_RING_MASK_0,
1771 ATH11K_RX_RING_MASK_1,
1772 ATH11K_RX_RING_MASK_2,
1773 ATH11K_RX_RING_MASK_3,
1774 },
1775 .rx_err = {
1776 0, 0, 0,
1777 ATH11K_RX_ERR_RING_MASK_0,
1778 },
1779 .rx_wbm_rel = {
1780 0, 0, 0,
1781 ATH11K_RX_WBM_REL_RING_MASK_0,
1782 },
1783 .reo_status = {
1784 0, 0, 0,
1785 ATH11K_REO_STATUS_RING_MASK_0,
1786 },
1787 .rxdma2host = {
1788 0, 0, 0,
1789 ATH11K_RXDMA2HOST_RING_MASK_0,
1790 },
1791 .host2rxdma = {
1792 0, 0, 0,
1793 ATH11K_HOST2RXDMA_RING_MASK_0,
1794 },
1795 };
1796
1797 const struct ath11k_hw_regs ipq8074_regs = {
1798 /* SW2TCL(x) R0 ring configuration address */
1799 .hal_tcl1_ring_base_lsb = 0x00000510,
1800 .hal_tcl1_ring_base_msb = 0x00000514,
1801 .hal_tcl1_ring_id = 0x00000518,
1802 .hal_tcl1_ring_misc = 0x00000520,
1803 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c,
1804 .hal_tcl1_ring_tp_addr_msb = 0x00000530,
1805 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540,
1806 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544,
1807 .hal_tcl1_ring_msi1_base_lsb = 0x00000558,
1808 .hal_tcl1_ring_msi1_base_msb = 0x0000055c,
1809 .hal_tcl1_ring_msi1_data = 0x00000560,
1810 .hal_tcl2_ring_base_lsb = 0x00000568,
1811 .hal_tcl_ring_base_lsb = 0x00000618,
1812
1813 /* TCL STATUS ring address */
1814 .hal_tcl_status_ring_base_lsb = 0x00000720,
1815
1816 /* REO2SW(x) R0 ring configuration address */
1817 .hal_reo1_ring_base_lsb = 0x0000029c,
1818 .hal_reo1_ring_base_msb = 0x000002a0,
1819 .hal_reo1_ring_id = 0x000002a4,
1820 .hal_reo1_ring_misc = 0x000002ac,
1821 .hal_reo1_ring_hp_addr_lsb = 0x000002b0,
1822 .hal_reo1_ring_hp_addr_msb = 0x000002b4,
1823 .hal_reo1_ring_producer_int_setup = 0x000002c0,
1824 .hal_reo1_ring_msi1_base_lsb = 0x000002e4,
1825 .hal_reo1_ring_msi1_base_msb = 0x000002e8,
1826 .hal_reo1_ring_msi1_data = 0x000002ec,
1827 .hal_reo2_ring_base_lsb = 0x000002f4,
1828 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
1829 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
1830 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
1831 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
1832
1833 /* REO2SW(x) R2 ring pointers (head/tail) address */
1834 .hal_reo1_ring_hp = 0x00003038,
1835 .hal_reo1_ring_tp = 0x0000303c,
1836 .hal_reo2_ring_hp = 0x00003040,
1837
1838 /* REO2TCL R0 ring configuration address */
1839 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
1840 .hal_reo_tcl_ring_hp = 0x00003058,
1841
1842 /* REO status address */
1843 .hal_reo_status_ring_base_lsb = 0x00000504,
1844 .hal_reo_status_hp = 0x00003070,
1845
1846 /* WCSS relative address */
1847 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
1848 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
1849 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
1850 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
1851
1852 /* WBM Idle address */
1853 .hal_wbm_idle_link_ring_base_lsb = 0x00000860,
1854 .hal_wbm_idle_link_ring_misc = 0x00000870,
1855
1856 /* SW2WBM release address */
1857 .hal_wbm_release_ring_base_lsb = 0x000001d8,
1858
1859 /* WBM2SW release address */
1860 .hal_wbm0_release_ring_base_lsb = 0x00000910,
1861 .hal_wbm1_release_ring_base_lsb = 0x00000968,
1862
1863 /* PCIe base address */
1864 .pcie_qserdes_sysclk_en_sel = 0x0,
1865 .pcie_pcs_osc_dtct_config_base = 0x0,
1866 };
1867
1868 const struct ath11k_hw_regs qca6390_regs = {
1869 /* SW2TCL(x) R0 ring configuration address */
1870 .hal_tcl1_ring_base_lsb = 0x00000684,
1871 .hal_tcl1_ring_base_msb = 0x00000688,
1872 .hal_tcl1_ring_id = 0x0000068c,
1873 .hal_tcl1_ring_misc = 0x00000694,
1874 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0,
1875 .hal_tcl1_ring_tp_addr_msb = 0x000006a4,
1876 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4,
1877 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8,
1878 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc,
1879 .hal_tcl1_ring_msi1_base_msb = 0x000006d0,
1880 .hal_tcl1_ring_msi1_data = 0x000006d4,
1881 .hal_tcl2_ring_base_lsb = 0x000006dc,
1882 .hal_tcl_ring_base_lsb = 0x0000078c,
1883
1884 /* TCL STATUS ring address */
1885 .hal_tcl_status_ring_base_lsb = 0x00000894,
1886
1887 /* REO2SW(x) R0 ring configuration address */
1888 .hal_reo1_ring_base_lsb = 0x00000244,
1889 .hal_reo1_ring_base_msb = 0x00000248,
1890 .hal_reo1_ring_id = 0x0000024c,
1891 .hal_reo1_ring_misc = 0x00000254,
1892 .hal_reo1_ring_hp_addr_lsb = 0x00000258,
1893 .hal_reo1_ring_hp_addr_msb = 0x0000025c,
1894 .hal_reo1_ring_producer_int_setup = 0x00000268,
1895 .hal_reo1_ring_msi1_base_lsb = 0x0000028c,
1896 .hal_reo1_ring_msi1_base_msb = 0x00000290,
1897 .hal_reo1_ring_msi1_data = 0x00000294,
1898 .hal_reo2_ring_base_lsb = 0x0000029c,
1899 .hal_reo1_aging_thresh_ix_0 = 0x0000050c,
1900 .hal_reo1_aging_thresh_ix_1 = 0x00000510,
1901 .hal_reo1_aging_thresh_ix_2 = 0x00000514,
1902 .hal_reo1_aging_thresh_ix_3 = 0x00000518,
1903
1904 /* REO2SW(x) R2 ring pointers (head/tail) address */
1905 .hal_reo1_ring_hp = 0x00003030,
1906 .hal_reo1_ring_tp = 0x00003034,
1907 .hal_reo2_ring_hp = 0x00003038,
1908
1909 /* REO2TCL R0 ring configuration address */
1910 .hal_reo_tcl_ring_base_lsb = 0x000003a4,
1911 .hal_reo_tcl_ring_hp = 0x00003050,
1912
1913 /* REO status address */
1914 .hal_reo_status_ring_base_lsb = 0x000004ac,
1915 .hal_reo_status_hp = 0x00003068,
1916
1917 /* WCSS relative address */
1918 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000,
1919 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000,
1920 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000,
1921 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000,
1922
1923 /* WBM Idle address */
1924 .hal_wbm_idle_link_ring_base_lsb = 0x00000860,
1925 .hal_wbm_idle_link_ring_misc = 0x00000870,
1926
1927 /* SW2WBM release address */
1928 .hal_wbm_release_ring_base_lsb = 0x000001d8,
1929
1930 /* WBM2SW release address */
1931 .hal_wbm0_release_ring_base_lsb = 0x00000910,
1932 .hal_wbm1_release_ring_base_lsb = 0x00000968,
1933
1934 /* PCIe base address */
1935 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
1936 .pcie_pcs_osc_dtct_config_base = 0x01e0c628,
1937 };
1938
1939 const struct ath11k_hw_regs qcn9074_regs = {
1940 /* SW2TCL(x) R0 ring configuration address */
1941 .hal_tcl1_ring_base_lsb = 0x000004f0,
1942 .hal_tcl1_ring_base_msb = 0x000004f4,
1943 .hal_tcl1_ring_id = 0x000004f8,
1944 .hal_tcl1_ring_misc = 0x00000500,
1945 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c,
1946 .hal_tcl1_ring_tp_addr_msb = 0x00000510,
1947 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520,
1948 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524,
1949 .hal_tcl1_ring_msi1_base_lsb = 0x00000538,
1950 .hal_tcl1_ring_msi1_base_msb = 0x0000053c,
1951 .hal_tcl1_ring_msi1_data = 0x00000540,
1952 .hal_tcl2_ring_base_lsb = 0x00000548,
1953 .hal_tcl_ring_base_lsb = 0x000005f8,
1954
1955 /* TCL STATUS ring address */
1956 .hal_tcl_status_ring_base_lsb = 0x00000700,
1957
1958 /* REO2SW(x) R0 ring configuration address */
1959 .hal_reo1_ring_base_lsb = 0x0000029c,
1960 .hal_reo1_ring_base_msb = 0x000002a0,
1961 .hal_reo1_ring_id = 0x000002a4,
1962 .hal_reo1_ring_misc = 0x000002ac,
1963 .hal_reo1_ring_hp_addr_lsb = 0x000002b0,
1964 .hal_reo1_ring_hp_addr_msb = 0x000002b4,
1965 .hal_reo1_ring_producer_int_setup = 0x000002c0,
1966 .hal_reo1_ring_msi1_base_lsb = 0x000002e4,
1967 .hal_reo1_ring_msi1_base_msb = 0x000002e8,
1968 .hal_reo1_ring_msi1_data = 0x000002ec,
1969 .hal_reo2_ring_base_lsb = 0x000002f4,
1970 .hal_reo1_aging_thresh_ix_0 = 0x00000564,
1971 .hal_reo1_aging_thresh_ix_1 = 0x00000568,
1972 .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
1973 .hal_reo1_aging_thresh_ix_3 = 0x00000570,
1974
1975 /* REO2SW(x) R2 ring pointers (head/tail) address */
1976 .hal_reo1_ring_hp = 0x00003038,
1977 .hal_reo1_ring_tp = 0x0000303c,
1978 .hal_reo2_ring_hp = 0x00003040,
1979
1980 /* REO2TCL R0 ring configuration address */
1981 .hal_reo_tcl_ring_base_lsb = 0x000003fc,
1982 .hal_reo_tcl_ring_hp = 0x00003058,
1983
1984 /* REO status address */
1985 .hal_reo_status_ring_base_lsb = 0x00000504,
1986 .hal_reo_status_hp = 0x00003070,
1987
1988 /* WCSS relative address */
1989 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000,
1990 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000,
1991 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000,
1992 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000,
1993
1994 /* WBM Idle address */
1995 .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
1996 .hal_wbm_idle_link_ring_misc = 0x00000884,
1997
1998 /* SW2WBM release address */
1999 .hal_wbm_release_ring_base_lsb = 0x000001ec,
2000
2001 /* WBM2SW release address */
2002 .hal_wbm0_release_ring_base_lsb = 0x00000924,
2003 .hal_wbm1_release_ring_base_lsb = 0x0000097c,
2004
2005 /* PCIe base address */
2006 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
2007 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
2008 };
2009
2010 const struct ath11k_hw_regs wcn6855_regs = {
2011 /* SW2TCL(x) R0 ring configuration address */
2012 .hal_tcl1_ring_base_lsb = 0x00000690,
2013 .hal_tcl1_ring_base_msb = 0x00000694,
2014 .hal_tcl1_ring_id = 0x00000698,
2015 .hal_tcl1_ring_misc = 0x000006a0,
2016 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac,
2017 .hal_tcl1_ring_tp_addr_msb = 0x000006b0,
2018 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0,
2019 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4,
2020 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8,
2021 .hal_tcl1_ring_msi1_base_msb = 0x000006dc,
2022 .hal_tcl1_ring_msi1_data = 0x000006e0,
2023 .hal_tcl2_ring_base_lsb = 0x000006e8,
2024 .hal_tcl_ring_base_lsb = 0x00000798,
2025
2026 /* TCL STATUS ring address */
2027 .hal_tcl_status_ring_base_lsb = 0x000008a0,
2028
2029 /* REO2SW(x) R0 ring configuration address */
2030 .hal_reo1_ring_base_lsb = 0x00000244,
2031 .hal_reo1_ring_base_msb = 0x00000248,
2032 .hal_reo1_ring_id = 0x0000024c,
2033 .hal_reo1_ring_misc = 0x00000254,
2034 .hal_reo1_ring_hp_addr_lsb = 0x00000258,
2035 .hal_reo1_ring_hp_addr_msb = 0x0000025c,
2036 .hal_reo1_ring_producer_int_setup = 0x00000268,
2037 .hal_reo1_ring_msi1_base_lsb = 0x0000028c,
2038 .hal_reo1_ring_msi1_base_msb = 0x00000290,
2039 .hal_reo1_ring_msi1_data = 0x00000294,
2040 .hal_reo2_ring_base_lsb = 0x0000029c,
2041 .hal_reo1_aging_thresh_ix_0 = 0x000005bc,
2042 .hal_reo1_aging_thresh_ix_1 = 0x000005c0,
2043 .hal_reo1_aging_thresh_ix_2 = 0x000005c4,
2044 .hal_reo1_aging_thresh_ix_3 = 0x000005c8,
2045
2046 /* REO2SW(x) R2 ring pointers (head/tail) address */
2047 .hal_reo1_ring_hp = 0x00003030,
2048 .hal_reo1_ring_tp = 0x00003034,
2049 .hal_reo2_ring_hp = 0x00003038,
2050
2051 /* REO2TCL R0 ring configuration address */
2052 .hal_reo_tcl_ring_base_lsb = 0x00000454,
2053 .hal_reo_tcl_ring_hp = 0x00003060,
2054
2055 /* REO status address */
2056 .hal_reo_status_ring_base_lsb = 0x0000055c,
2057 .hal_reo_status_hp = 0x00003078,
2058
2059 /* WCSS relative address */
2060 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000,
2061 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000,
2062 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000,
2063 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000,
2064
2065 /* WBM Idle address */
2066 .hal_wbm_idle_link_ring_base_lsb = 0x00000870,
2067 .hal_wbm_idle_link_ring_misc = 0x00000880,
2068
2069 /* SW2WBM release address */
2070 .hal_wbm_release_ring_base_lsb = 0x000001e8,
2071
2072 /* WBM2SW release address */
2073 .hal_wbm0_release_ring_base_lsb = 0x00000920,
2074 .hal_wbm1_release_ring_base_lsb = 0x00000978,
2075
2076 /* PCIe base address */
2077 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac,
2078 .pcie_pcs_osc_dtct_config_base = 0x01e0c628,
2079 };
2080