1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
3
4 #ifndef _DR_TYPES_
5 #define _DR_TYPES_
6
7 #include <linux/mlx5/vport.h>
8 #include <linux/refcount.h>
9 #include "fs_core.h"
10 #include "wq.h"
11 #include "lib/mlx5.h"
12 #include "mlx5_ifc_dr.h"
13 #include "mlx5dr.h"
14
15 #define DR_RULE_MAX_STES 18
16 #define DR_ACTION_MAX_STES 5
17 #define DR_STE_SVLAN 0x1
18 #define DR_STE_CVLAN 0x2
19 #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
20 #define DR_NUM_OF_FLEX_PARSERS 8
21 #define DR_STE_MAX_FLEX_0_ID 3
22 #define DR_STE_MAX_FLEX_1_ID 7
23
24 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
25 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
26 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
27
dr_is_flex_parser_0_id(u8 parser_id)28 static inline bool dr_is_flex_parser_0_id(u8 parser_id)
29 {
30 return parser_id <= DR_STE_MAX_FLEX_0_ID;
31 }
32
dr_is_flex_parser_1_id(u8 parser_id)33 static inline bool dr_is_flex_parser_1_id(u8 parser_id)
34 {
35 return parser_id > DR_STE_MAX_FLEX_0_ID;
36 }
37
38 enum mlx5dr_icm_chunk_size {
39 DR_CHUNK_SIZE_1,
40 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
41 DR_CHUNK_SIZE_2,
42 DR_CHUNK_SIZE_4,
43 DR_CHUNK_SIZE_8,
44 DR_CHUNK_SIZE_16,
45 DR_CHUNK_SIZE_32,
46 DR_CHUNK_SIZE_64,
47 DR_CHUNK_SIZE_128,
48 DR_CHUNK_SIZE_256,
49 DR_CHUNK_SIZE_512,
50 DR_CHUNK_SIZE_1K,
51 DR_CHUNK_SIZE_2K,
52 DR_CHUNK_SIZE_4K,
53 DR_CHUNK_SIZE_8K,
54 DR_CHUNK_SIZE_16K,
55 DR_CHUNK_SIZE_32K,
56 DR_CHUNK_SIZE_64K,
57 DR_CHUNK_SIZE_128K,
58 DR_CHUNK_SIZE_256K,
59 DR_CHUNK_SIZE_512K,
60 DR_CHUNK_SIZE_1024K,
61 DR_CHUNK_SIZE_2048K,
62 DR_CHUNK_SIZE_MAX,
63 };
64
65 enum mlx5dr_icm_type {
66 DR_ICM_TYPE_STE,
67 DR_ICM_TYPE_MODIFY_ACTION,
68 };
69
70 static inline enum mlx5dr_icm_chunk_size
mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)71 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)
72 {
73 chunk += 2;
74 if (chunk < DR_CHUNK_SIZE_MAX)
75 return chunk;
76
77 return DR_CHUNK_SIZE_MAX;
78 }
79
80 enum {
81 DR_STE_SIZE = 64,
82 DR_STE_SIZE_CTRL = 32,
83 DR_STE_SIZE_TAG = 16,
84 DR_STE_SIZE_MASK = 16,
85 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
86 };
87
88 enum mlx5dr_ste_ctx_action_cap {
89 DR_STE_CTX_ACTION_CAP_NONE = 0,
90 DR_STE_CTX_ACTION_CAP_TX_POP = 1 << 0,
91 DR_STE_CTX_ACTION_CAP_RX_PUSH = 1 << 1,
92 DR_STE_CTX_ACTION_CAP_RX_ENCAP = 1 << 2,
93 };
94
95 enum {
96 DR_MODIFY_ACTION_SIZE = 8,
97 };
98
99 enum mlx5dr_matcher_criteria {
100 DR_MATCHER_CRITERIA_EMPTY = 0,
101 DR_MATCHER_CRITERIA_OUTER = 1 << 0,
102 DR_MATCHER_CRITERIA_MISC = 1 << 1,
103 DR_MATCHER_CRITERIA_INNER = 1 << 2,
104 DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
105 DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
106 DR_MATCHER_CRITERIA_MISC4 = 1 << 5,
107 DR_MATCHER_CRITERIA_MAX = 1 << 6,
108 };
109
110 enum mlx5dr_action_type {
111 DR_ACTION_TYP_TNL_L2_TO_L2,
112 DR_ACTION_TYP_L2_TO_TNL_L2,
113 DR_ACTION_TYP_TNL_L3_TO_L2,
114 DR_ACTION_TYP_L2_TO_TNL_L3,
115 DR_ACTION_TYP_DROP,
116 DR_ACTION_TYP_QP,
117 DR_ACTION_TYP_FT,
118 DR_ACTION_TYP_CTR,
119 DR_ACTION_TYP_TAG,
120 DR_ACTION_TYP_MODIFY_HDR,
121 DR_ACTION_TYP_VPORT,
122 DR_ACTION_TYP_POP_VLAN,
123 DR_ACTION_TYP_PUSH_VLAN,
124 DR_ACTION_TYP_INSERT_HDR,
125 DR_ACTION_TYP_REMOVE_HDR,
126 DR_ACTION_TYP_SAMPLER,
127 DR_ACTION_TYP_MAX,
128 };
129
130 enum mlx5dr_ipv {
131 DR_RULE_IPV4,
132 DR_RULE_IPV6,
133 DR_RULE_IPV_MAX,
134 };
135
136 struct mlx5dr_icm_pool;
137 struct mlx5dr_icm_chunk;
138 struct mlx5dr_icm_buddy_mem;
139 struct mlx5dr_ste_htbl;
140 struct mlx5dr_match_param;
141 struct mlx5dr_cmd_caps;
142 struct mlx5dr_rule_rx_tx;
143 struct mlx5dr_matcher_rx_tx;
144 struct mlx5dr_ste_ctx;
145
146 struct mlx5dr_ste {
147 u8 *hw_ste;
148 /* refcount: indicates the num of rules that using this ste */
149 u32 refcount;
150
151 /* attached to the miss_list head at each htbl entry */
152 struct list_head miss_list_node;
153
154 /* this ste is member of htbl */
155 struct mlx5dr_ste_htbl *htbl;
156
157 struct mlx5dr_ste_htbl *next_htbl;
158
159 /* The rule this STE belongs to */
160 struct mlx5dr_rule_rx_tx *rule_rx_tx;
161
162 /* this ste is part of a rule, located in ste's chain */
163 u8 ste_chain_location;
164 };
165
166 struct mlx5dr_ste_htbl_ctrl {
167 /* total number of valid entries belonging to this hash table. This
168 * includes the non collision and collision entries
169 */
170 unsigned int num_of_valid_entries;
171
172 /* total number of collisions entries attached to this table */
173 unsigned int num_of_collisions;
174 };
175
176 struct mlx5dr_ste_htbl {
177 u16 lu_type;
178 u16 byte_mask;
179 u32 refcount;
180 struct mlx5dr_icm_chunk *chunk;
181 struct mlx5dr_ste *ste_arr;
182 u8 *hw_ste_arr;
183
184 struct list_head *miss_list;
185
186 enum mlx5dr_icm_chunk_size chunk_size;
187 struct mlx5dr_ste *pointing_ste;
188
189 struct mlx5dr_ste_htbl_ctrl ctrl;
190 };
191
192 struct mlx5dr_ste_send_info {
193 struct mlx5dr_ste *ste;
194 struct list_head send_list;
195 u16 size;
196 u16 offset;
197 u8 data_cont[DR_STE_SIZE];
198 u8 *data;
199 };
200
201 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size,
202 u16 offset, u8 *data,
203 struct mlx5dr_ste_send_info *ste_info,
204 struct list_head *send_list,
205 bool copy_data);
206
207 struct mlx5dr_ste_build {
208 u8 inner:1;
209 u8 rx:1;
210 u8 vhca_id_valid:1;
211 struct mlx5dr_domain *dmn;
212 struct mlx5dr_cmd_caps *caps;
213 u16 lu_type;
214 u16 byte_mask;
215 u8 bit_mask[DR_STE_SIZE_MASK];
216 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec,
217 struct mlx5dr_ste_build *sb,
218 u8 *tag);
219 };
220
221 struct mlx5dr_ste_htbl *
222 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
223 enum mlx5dr_icm_chunk_size chunk_size,
224 u16 lu_type, u16 byte_mask);
225
226 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl);
227
mlx5dr_htbl_put(struct mlx5dr_ste_htbl * htbl)228 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl)
229 {
230 htbl->refcount--;
231 if (!htbl->refcount)
232 mlx5dr_ste_htbl_free(htbl);
233 }
234
mlx5dr_htbl_get(struct mlx5dr_ste_htbl * htbl)235 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl)
236 {
237 htbl->refcount++;
238 }
239
240 /* STE utils */
241 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
242 void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx,
243 u8 *hw_ste, u64 miss_addr);
244 void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx,
245 u8 *hw_ste, u64 icm_addr, u32 ht_size);
246 void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx,
247 u8 *hw_ste,
248 struct mlx5dr_ste_htbl *next_htbl);
249 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
250 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher,
251 u8 ste_location);
252 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste);
253 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste);
254 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste);
255
256 #define MLX5DR_MAX_VLANS 2
257
258 struct mlx5dr_ste_actions_attr {
259 u32 modify_index;
260 u16 modify_actions;
261 u32 decap_index;
262 u16 decap_actions;
263 u8 decap_with_vlan:1;
264 u64 final_icm_addr;
265 u32 flow_tag;
266 u32 ctr_id;
267 u16 gvmi;
268 u16 hit_gvmi;
269 struct {
270 u32 id;
271 u32 size;
272 u8 param_0;
273 u8 param_1;
274 } reformat;
275 struct {
276 int count;
277 u32 headers[MLX5DR_MAX_VLANS];
278 } vlans;
279 };
280
281 void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx,
282 struct mlx5dr_domain *dmn,
283 u8 *action_type_set,
284 u8 *last_ste,
285 struct mlx5dr_ste_actions_attr *attr,
286 u32 *added_stes);
287 void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx,
288 struct mlx5dr_domain *dmn,
289 u8 *action_type_set,
290 u8 *last_ste,
291 struct mlx5dr_ste_actions_attr *attr,
292 u32 *added_stes);
293
294 void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx,
295 __be64 *hw_action,
296 u8 hw_field,
297 u8 shifter,
298 u8 length,
299 u32 data);
300 void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx,
301 __be64 *hw_action,
302 u8 hw_field,
303 u8 shifter,
304 u8 length,
305 u32 data);
306 void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx,
307 __be64 *hw_action,
308 u8 dst_hw_field,
309 u8 dst_shifter,
310 u8 dst_len,
311 u8 src_hw_field,
312 u8 src_shifter);
313 int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx,
314 void *data,
315 u32 data_sz,
316 u8 *hw_action,
317 u32 hw_action_sz,
318 u16 *used_hw_action_num);
319
320 const struct mlx5dr_ste_action_modify_field *
321 mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field);
322
323 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version);
324 void mlx5dr_ste_free(struct mlx5dr_ste *ste,
325 struct mlx5dr_matcher *matcher,
326 struct mlx5dr_matcher_rx_tx *nic_matcher);
mlx5dr_ste_put(struct mlx5dr_ste * ste,struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher)327 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste,
328 struct mlx5dr_matcher *matcher,
329 struct mlx5dr_matcher_rx_tx *nic_matcher)
330 {
331 ste->refcount--;
332 if (!ste->refcount)
333 mlx5dr_ste_free(ste, matcher, nic_matcher);
334 }
335
336 /* initial as 0, increased only when ste appears in a new rule */
mlx5dr_ste_get(struct mlx5dr_ste * ste)337 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste)
338 {
339 ste->refcount++;
340 }
341
mlx5dr_ste_is_not_used(struct mlx5dr_ste * ste)342 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste)
343 {
344 return !ste->refcount;
345 }
346
347 bool mlx5dr_ste_equal_tag(void *src, void *dst);
348 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher,
349 struct mlx5dr_matcher_rx_tx *nic_matcher,
350 struct mlx5dr_ste *ste,
351 u8 *cur_hw_ste,
352 enum mlx5dr_icm_chunk_size log_table_size);
353
354 /* STE build functions */
355 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
356 u8 match_criteria,
357 struct mlx5dr_match_param *mask,
358 struct mlx5dr_match_param *value);
359 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher,
360 struct mlx5dr_matcher_rx_tx *nic_matcher,
361 struct mlx5dr_match_param *value,
362 u8 *ste_arr);
363 void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx,
364 struct mlx5dr_ste_build *builder,
365 struct mlx5dr_match_param *mask,
366 bool inner, bool rx);
367 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx,
368 struct mlx5dr_ste_build *sb,
369 struct mlx5dr_match_param *mask,
370 bool inner, bool rx);
371 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx,
372 struct mlx5dr_ste_build *sb,
373 struct mlx5dr_match_param *mask,
374 bool inner, bool rx);
375 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx,
376 struct mlx5dr_ste_build *sb,
377 struct mlx5dr_match_param *mask,
378 bool inner, bool rx);
379 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx,
380 struct mlx5dr_ste_build *sb,
381 struct mlx5dr_match_param *mask,
382 bool inner, bool rx);
383 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx,
384 struct mlx5dr_ste_build *sb,
385 struct mlx5dr_match_param *mask,
386 bool inner, bool rx);
387 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx,
388 struct mlx5dr_ste_build *sb,
389 struct mlx5dr_match_param *mask,
390 bool inner, bool rx);
391 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx,
392 struct mlx5dr_ste_build *sb,
393 struct mlx5dr_match_param *mask,
394 bool inner, bool rx);
395 void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx,
396 struct mlx5dr_ste_build *sb,
397 struct mlx5dr_match_param *mask,
398 bool inner, bool rx);
399 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx,
400 struct mlx5dr_ste_build *sb,
401 struct mlx5dr_match_param *mask,
402 bool inner, bool rx);
403 void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx,
404 struct mlx5dr_ste_build *sb,
405 struct mlx5dr_match_param *mask,
406 bool inner, bool rx);
407 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx,
408 struct mlx5dr_ste_build *sb,
409 struct mlx5dr_match_param *mask,
410 bool inner, bool rx);
411 void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx,
412 struct mlx5dr_ste_build *sb,
413 struct mlx5dr_match_param *mask,
414 bool inner, bool rx);
415 void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx,
416 struct mlx5dr_ste_build *sb,
417 struct mlx5dr_match_param *mask,
418 struct mlx5dr_cmd_caps *caps,
419 bool inner, bool rx);
420 void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx,
421 struct mlx5dr_ste_build *sb,
422 struct mlx5dr_match_param *mask,
423 struct mlx5dr_cmd_caps *caps,
424 bool inner, bool rx);
425 void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx,
426 struct mlx5dr_ste_build *sb,
427 struct mlx5dr_match_param *mask,
428 struct mlx5dr_cmd_caps *caps,
429 bool inner, bool rx);
430 void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx,
431 struct mlx5dr_ste_build *sb,
432 struct mlx5dr_match_param *mask,
433 bool inner, bool rx);
434 void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx,
435 struct mlx5dr_ste_build *sb,
436 struct mlx5dr_match_param *mask,
437 bool inner, bool rx);
438 void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx,
439 struct mlx5dr_ste_build *sb,
440 struct mlx5dr_match_param *mask,
441 struct mlx5dr_cmd_caps *caps,
442 bool inner, bool rx);
443 void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx,
444 struct mlx5dr_ste_build *sb,
445 struct mlx5dr_match_param *mask,
446 bool inner, bool rx);
447 void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx,
448 struct mlx5dr_ste_build *sb,
449 struct mlx5dr_match_param *mask,
450 struct mlx5dr_cmd_caps *caps,
451 bool inner, bool rx);
452 void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
453 struct mlx5dr_ste_build *sb,
454 struct mlx5dr_match_param *mask,
455 struct mlx5dr_cmd_caps *caps,
456 bool inner, bool rx);
457 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx,
458 struct mlx5dr_ste_build *sb,
459 struct mlx5dr_match_param *mask,
460 bool inner, bool rx);
461 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx,
462 struct mlx5dr_ste_build *sb,
463 struct mlx5dr_match_param *mask,
464 bool inner, bool rx);
465 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx,
466 struct mlx5dr_ste_build *sb,
467 struct mlx5dr_match_param *mask,
468 bool inner, bool rx);
469 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx,
470 struct mlx5dr_ste_build *sb,
471 struct mlx5dr_match_param *mask,
472 struct mlx5dr_domain *dmn,
473 bool inner, bool rx);
474 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx,
475 struct mlx5dr_ste_build *sb,
476 struct mlx5dr_match_param *mask,
477 bool inner, bool rx);
478 void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
479 struct mlx5dr_ste_build *sb,
480 struct mlx5dr_match_param *mask,
481 bool inner, bool rx);
482 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
483
484 /* Actions utils */
485 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
486 struct mlx5dr_matcher_rx_tx *nic_matcher,
487 struct mlx5dr_action *actions[],
488 u32 num_actions,
489 u8 *ste_arr,
490 u32 *new_hw_ste_arr_sz);
491
492 struct mlx5dr_match_spec {
493 u32 smac_47_16; /* Source MAC address of incoming packet */
494 /* Incoming packet Ethertype - this is the Ethertype
495 * following the last VLAN tag of the packet
496 */
497 u32 ethertype:16;
498 u32 smac_15_0:16; /* Source MAC address of incoming packet */
499 u32 dmac_47_16; /* Destination MAC address of incoming packet */
500 /* VLAN ID of first VLAN tag in the incoming packet.
501 * Valid only when cvlan_tag==1 or svlan_tag==1
502 */
503 u32 first_vid:12;
504 /* CFI bit of first VLAN tag in the incoming packet.
505 * Valid only when cvlan_tag==1 or svlan_tag==1
506 */
507 u32 first_cfi:1;
508 /* Priority of first VLAN tag in the incoming packet.
509 * Valid only when cvlan_tag==1 or svlan_tag==1
510 */
511 u32 first_prio:3;
512 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */
513 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK;
514 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS
515 */
516 u32 tcp_flags:9;
517 u32 ip_version:4; /* IP version */
518 u32 frag:1; /* Packet is an IP fragment */
519 /* The first vlan in the packet is s-vlan (0x8a88).
520 * cvlan_tag and svlan_tag cannot be set together
521 */
522 u32 svlan_tag:1;
523 /* The first vlan in the packet is c-vlan (0x8100).
524 * cvlan_tag and svlan_tag cannot be set together
525 */
526 u32 cvlan_tag:1;
527 /* Explicit Congestion Notification derived from
528 * Traffic Class/TOS field of IPv6/v4
529 */
530 u32 ip_ecn:2;
531 /* Differentiated Services Code Point derived from
532 * Traffic Class/TOS field of IPv6/v4
533 */
534 u32 ip_dscp:6;
535 u32 ip_protocol:8; /* IP protocol */
536 /* TCP destination port.
537 * tcp and udp sport/dport are mutually exclusive
538 */
539 u32 tcp_dport:16;
540 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */
541 u32 tcp_sport:16;
542 u32 ttl_hoplimit:8;
543 u32 reserved:24;
544 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */
545 u32 udp_dport:16;
546 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */
547 u32 udp_sport:16;
548 /* IPv6 source address of incoming packets
549 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
550 * This field should be qualified by an appropriate ethertype
551 */
552 u32 src_ip_127_96;
553 /* IPv6 source address of incoming packets
554 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
555 * This field should be qualified by an appropriate ethertype
556 */
557 u32 src_ip_95_64;
558 /* IPv6 source address of incoming packets
559 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
560 * This field should be qualified by an appropriate ethertype
561 */
562 u32 src_ip_63_32;
563 /* IPv6 source address of incoming packets
564 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
565 * This field should be qualified by an appropriate ethertype
566 */
567 u32 src_ip_31_0;
568 /* IPv6 destination address of incoming packets
569 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
570 * This field should be qualified by an appropriate ethertype
571 */
572 u32 dst_ip_127_96;
573 /* IPv6 destination address of incoming packets
574 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
575 * This field should be qualified by an appropriate ethertype
576 */
577 u32 dst_ip_95_64;
578 /* IPv6 destination address of incoming packets
579 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
580 * This field should be qualified by an appropriate ethertype
581 */
582 u32 dst_ip_63_32;
583 /* IPv6 destination address of incoming packets
584 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
585 * This field should be qualified by an appropriate ethertype
586 */
587 u32 dst_ip_31_0;
588 };
589
590 struct mlx5dr_match_misc {
591 u32 source_sqn:24; /* Source SQN */
592 u32 source_vhca_port:4;
593 /* used with GRE, sequence number exist when gre_s_present == 1 */
594 u32 gre_s_present:1;
595 /* used with GRE, key exist when gre_k_present == 1 */
596 u32 gre_k_present:1;
597 u32 reserved_auto1:1;
598 /* used with GRE, checksum exist when gre_c_present == 1 */
599 u32 gre_c_present:1;
600 /* Source port.;0xffff determines wire port */
601 u32 source_port:16;
602 u32 source_eswitch_owner_vhca_id:16;
603 /* VLAN ID of first VLAN tag the inner header of the incoming packet.
604 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
605 */
606 u32 inner_second_vid:12;
607 /* CFI bit of first VLAN tag in the inner header of the incoming packet.
608 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
609 */
610 u32 inner_second_cfi:1;
611 /* Priority of second VLAN tag in the inner header of the incoming packet.
612 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
613 */
614 u32 inner_second_prio:3;
615 /* VLAN ID of first VLAN tag the outer header of the incoming packet.
616 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
617 */
618 u32 outer_second_vid:12;
619 /* CFI bit of first VLAN tag in the outer header of the incoming packet.
620 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
621 */
622 u32 outer_second_cfi:1;
623 /* Priority of second VLAN tag in the outer header of the incoming packet.
624 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
625 */
626 u32 outer_second_prio:3;
627 u32 gre_protocol:16; /* GRE Protocol (outer) */
628 u32 reserved_auto3:12;
629 /* The second vlan in the inner header of the packet is s-vlan (0x8a88).
630 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
631 */
632 u32 inner_second_svlan_tag:1;
633 /* The second vlan in the outer header of the packet is s-vlan (0x8a88).
634 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
635 */
636 u32 outer_second_svlan_tag:1;
637 /* The second vlan in the inner header of the packet is c-vlan (0x8100).
638 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
639 */
640 u32 inner_second_cvlan_tag:1;
641 /* The second vlan in the outer header of the packet is c-vlan (0x8100).
642 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
643 */
644 u32 outer_second_cvlan_tag:1;
645 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */
646 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */
647 u32 reserved_auto4:8;
648 u32 vxlan_vni:24; /* VXLAN VNI (outer) */
649 u32 geneve_oam:1; /* GENEVE OAM field (outer) */
650 u32 reserved_auto5:7;
651 u32 geneve_vni:24; /* GENEVE VNI field (outer) */
652 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */
653 u32 reserved_auto6:12;
654 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */
655 u32 reserved_auto7:12;
656 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */
657 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */
658 u32 reserved_auto8:10;
659 u32 bth_dst_qp:24; /* Destination QP in BTH header */
660 u32 reserved_auto9:8;
661 u8 reserved_auto10[20];
662 };
663
664 struct mlx5dr_match_misc2 {
665 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */
666 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */
667 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */
668 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */
669 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */
670 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */
671 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */
672 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */
673 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */
674 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */
675 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */
676 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */
677 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */
678 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */
679 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */
680 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */
681 u32 metadata_reg_c_7; /* metadata_reg_c_7 */
682 u32 metadata_reg_c_6; /* metadata_reg_c_6 */
683 u32 metadata_reg_c_5; /* metadata_reg_c_5 */
684 u32 metadata_reg_c_4; /* metadata_reg_c_4 */
685 u32 metadata_reg_c_3; /* metadata_reg_c_3 */
686 u32 metadata_reg_c_2; /* metadata_reg_c_2 */
687 u32 metadata_reg_c_1; /* metadata_reg_c_1 */
688 u32 metadata_reg_c_0; /* metadata_reg_c_0 */
689 u32 metadata_reg_a; /* metadata_reg_a */
690 u8 reserved_auto2[12];
691 };
692
693 struct mlx5dr_match_misc3 {
694 u32 inner_tcp_seq_num;
695 u32 outer_tcp_seq_num;
696 u32 inner_tcp_ack_num;
697 u32 outer_tcp_ack_num;
698 u32 outer_vxlan_gpe_vni:24;
699 u32 reserved_auto1:8;
700 u32 reserved_auto2:16;
701 u32 outer_vxlan_gpe_flags:8;
702 u32 outer_vxlan_gpe_next_protocol:8;
703 u32 icmpv4_header_data;
704 u32 icmpv6_header_data;
705 u8 icmpv6_code;
706 u8 icmpv6_type;
707 u8 icmpv4_code;
708 u8 icmpv4_type;
709 u32 geneve_tlv_option_0_data;
710 u8 gtpu_msg_flags;
711 u8 gtpu_msg_type;
712 u32 gtpu_teid;
713 u32 gtpu_dw_2;
714 u32 gtpu_first_ext_dw_0;
715 u32 gtpu_dw_0;
716 };
717
718 struct mlx5dr_match_misc4 {
719 u32 prog_sample_field_value_0;
720 u32 prog_sample_field_id_0;
721 u32 prog_sample_field_value_1;
722 u32 prog_sample_field_id_1;
723 u32 prog_sample_field_value_2;
724 u32 prog_sample_field_id_2;
725 u32 prog_sample_field_value_3;
726 u32 prog_sample_field_id_3;
727 };
728
729 struct mlx5dr_match_param {
730 struct mlx5dr_match_spec outer;
731 struct mlx5dr_match_misc misc;
732 struct mlx5dr_match_spec inner;
733 struct mlx5dr_match_misc2 misc2;
734 struct mlx5dr_match_misc3 misc3;
735 struct mlx5dr_match_misc4 misc4;
736 };
737
738 #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \
739 (_misc3)->icmpv4_code || \
740 (_misc3)->icmpv4_header_data)
741
742 #define DR_MASK_IS_SRC_IP_SET(_spec) ((_spec)->src_ip_127_96 || \
743 (_spec)->src_ip_95_64 || \
744 (_spec)->src_ip_63_32 || \
745 (_spec)->src_ip_31_0)
746
747 #define DR_MASK_IS_DST_IP_SET(_spec) ((_spec)->dst_ip_127_96 || \
748 (_spec)->dst_ip_95_64 || \
749 (_spec)->dst_ip_63_32 || \
750 (_spec)->dst_ip_31_0)
751
752 struct mlx5dr_esw_caps {
753 u64 drop_icm_address_rx;
754 u64 drop_icm_address_tx;
755 u64 uplink_icm_address_rx;
756 u64 uplink_icm_address_tx;
757 u8 sw_owner:1;
758 u8 sw_owner_v2:1;
759 };
760
761 struct mlx5dr_cmd_vport_cap {
762 u16 vport_gvmi;
763 u16 vhca_gvmi;
764 u64 icm_address_rx;
765 u64 icm_address_tx;
766 u32 num;
767 };
768
769 struct mlx5dr_roce_cap {
770 u8 roce_en:1;
771 u8 fl_rc_qp_when_roce_disabled:1;
772 u8 fl_rc_qp_when_roce_enabled:1;
773 };
774
775 struct mlx5dr_cmd_caps {
776 u16 gvmi;
777 u64 nic_rx_drop_address;
778 u64 nic_tx_drop_address;
779 u64 nic_tx_allow_address;
780 u64 esw_rx_drop_address;
781 u64 esw_tx_drop_address;
782 u32 log_icm_size;
783 u64 hdr_modify_icm_addr;
784 u32 flex_protocols;
785 u8 flex_parser_id_icmp_dw0;
786 u8 flex_parser_id_icmp_dw1;
787 u8 flex_parser_id_icmpv6_dw0;
788 u8 flex_parser_id_icmpv6_dw1;
789 u8 flex_parser_id_geneve_tlv_option_0;
790 u8 flex_parser_id_mpls_over_gre;
791 u8 flex_parser_id_mpls_over_udp;
792 u8 flex_parser_id_gtpu_dw_0;
793 u8 flex_parser_id_gtpu_teid;
794 u8 flex_parser_id_gtpu_dw_2;
795 u8 flex_parser_id_gtpu_first_ext_dw_0;
796 u8 max_ft_level;
797 u16 roce_min_src_udp;
798 u8 num_esw_ports;
799 u8 sw_format_ver;
800 bool eswitch_manager;
801 bool rx_sw_owner;
802 bool tx_sw_owner;
803 bool fdb_sw_owner;
804 u8 rx_sw_owner_v2:1;
805 u8 tx_sw_owner_v2:1;
806 u8 fdb_sw_owner_v2:1;
807 u32 num_vports;
808 struct mlx5dr_esw_caps esw_caps;
809 struct mlx5dr_cmd_vport_cap *vports_caps;
810 bool prio_tag_required;
811 struct mlx5dr_roce_cap roce_caps;
812 u8 isolate_vl_tc:1;
813 };
814
815 enum mlx5dr_domain_nic_type {
816 DR_DOMAIN_NIC_TYPE_RX,
817 DR_DOMAIN_NIC_TYPE_TX,
818 };
819
820 struct mlx5dr_domain_rx_tx {
821 u64 drop_icm_addr;
822 u64 default_icm_addr;
823 enum mlx5dr_domain_nic_type type;
824 struct mutex mutex; /* protect rx/tx domain */
825 };
826
827 struct mlx5dr_domain_info {
828 bool supp_sw_steering;
829 u32 max_inline_size;
830 u32 max_send_wr;
831 u32 max_log_sw_icm_sz;
832 u32 max_log_action_icm_sz;
833 struct mlx5dr_domain_rx_tx rx;
834 struct mlx5dr_domain_rx_tx tx;
835 struct mlx5dr_cmd_caps caps;
836 };
837
838 struct mlx5dr_domain_cache {
839 struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft;
840 };
841
842 struct mlx5dr_domain {
843 struct mlx5dr_domain *peer_dmn;
844 struct mlx5_core_dev *mdev;
845 u32 pdn;
846 struct mlx5_uars_page *uar;
847 enum mlx5dr_domain_type type;
848 refcount_t refcount;
849 struct mlx5dr_icm_pool *ste_icm_pool;
850 struct mlx5dr_icm_pool *action_icm_pool;
851 struct mlx5dr_send_ring *send_ring;
852 struct mlx5dr_domain_info info;
853 struct mlx5dr_domain_cache cache;
854 struct mlx5dr_ste_ctx *ste_ctx;
855 };
856
857 struct mlx5dr_table_rx_tx {
858 struct mlx5dr_ste_htbl *s_anchor;
859 struct mlx5dr_domain_rx_tx *nic_dmn;
860 u64 default_icm_addr;
861 };
862
863 struct mlx5dr_table {
864 struct mlx5dr_domain *dmn;
865 struct mlx5dr_table_rx_tx rx;
866 struct mlx5dr_table_rx_tx tx;
867 u32 level;
868 u32 table_type;
869 u32 table_id;
870 u32 flags;
871 struct list_head matcher_list;
872 struct mlx5dr_action *miss_action;
873 refcount_t refcount;
874 };
875
876 struct mlx5dr_matcher_rx_tx {
877 struct mlx5dr_ste_htbl *s_htbl;
878 struct mlx5dr_ste_htbl *e_anchor;
879 struct mlx5dr_ste_build *ste_builder;
880 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX]
881 [DR_RULE_IPV_MAX]
882 [DR_RULE_MAX_STES];
883 u8 num_of_builders;
884 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX];
885 u64 default_icm_addr;
886 struct mlx5dr_table_rx_tx *nic_tbl;
887 };
888
889 struct mlx5dr_matcher {
890 struct mlx5dr_table *tbl;
891 struct mlx5dr_matcher_rx_tx rx;
892 struct mlx5dr_matcher_rx_tx tx;
893 struct list_head list_node;
894 u32 prio;
895 struct mlx5dr_match_param mask;
896 u8 match_criteria;
897 refcount_t refcount;
898 struct mlx5dv_flow_matcher *dv_matcher;
899 };
900
901 struct mlx5dr_ste_action_modify_field {
902 u16 hw_field;
903 u8 start;
904 u8 end;
905 u8 l3_type;
906 u8 l4_type;
907 };
908
909 struct mlx5dr_action_rewrite {
910 struct mlx5dr_domain *dmn;
911 struct mlx5dr_icm_chunk *chunk;
912 u8 *data;
913 u16 num_of_actions;
914 u32 index;
915 u8 allow_rx:1;
916 u8 allow_tx:1;
917 u8 modify_ttl:1;
918 };
919
920 struct mlx5dr_action_reformat {
921 struct mlx5dr_domain *dmn;
922 u32 id;
923 u32 size;
924 u8 param_0;
925 u8 param_1;
926 };
927
928 struct mlx5dr_action_sampler {
929 struct mlx5dr_domain *dmn;
930 u64 rx_icm_addr;
931 u64 tx_icm_addr;
932 u32 sampler_id;
933 };
934
935 struct mlx5dr_action_dest_tbl {
936 u8 is_fw_tbl:1;
937 union {
938 struct mlx5dr_table *tbl;
939 struct {
940 struct mlx5dr_domain *dmn;
941 u32 id;
942 u32 group_id;
943 enum fs_flow_table_type type;
944 u64 rx_icm_addr;
945 u64 tx_icm_addr;
946 struct mlx5dr_action **ref_actions;
947 u32 num_of_ref_actions;
948 } fw_tbl;
949 };
950 };
951
952 struct mlx5dr_action_ctr {
953 u32 ctr_id;
954 u32 offeset;
955 };
956
957 struct mlx5dr_action_vport {
958 struct mlx5dr_domain *dmn;
959 struct mlx5dr_cmd_vport_cap *caps;
960 };
961
962 struct mlx5dr_action_push_vlan {
963 u32 vlan_hdr; /* tpid_pcp_dei_vid */
964 };
965
966 struct mlx5dr_action_flow_tag {
967 u32 flow_tag;
968 };
969
970 struct mlx5dr_action {
971 enum mlx5dr_action_type action_type;
972 refcount_t refcount;
973
974 union {
975 void *data;
976 struct mlx5dr_action_rewrite *rewrite;
977 struct mlx5dr_action_reformat *reformat;
978 struct mlx5dr_action_sampler *sampler;
979 struct mlx5dr_action_dest_tbl *dest_tbl;
980 struct mlx5dr_action_ctr *ctr;
981 struct mlx5dr_action_vport *vport;
982 struct mlx5dr_action_push_vlan *push_vlan;
983 struct mlx5dr_action_flow_tag *flow_tag;
984 };
985 };
986
987 enum mlx5dr_connect_type {
988 CONNECT_HIT = 1,
989 CONNECT_MISS = 2,
990 };
991
992 struct mlx5dr_htbl_connect_info {
993 enum mlx5dr_connect_type type;
994 union {
995 struct mlx5dr_ste_htbl *hit_next_htbl;
996 u64 miss_icm_addr;
997 };
998 };
999
1000 struct mlx5dr_rule_rx_tx {
1001 struct mlx5dr_matcher_rx_tx *nic_matcher;
1002 struct mlx5dr_ste *last_rule_ste;
1003 };
1004
1005 struct mlx5dr_rule {
1006 struct mlx5dr_matcher *matcher;
1007 struct mlx5dr_rule_rx_tx rx;
1008 struct mlx5dr_rule_rx_tx tx;
1009 struct list_head rule_actions_list;
1010 u32 flow_source;
1011 };
1012
1013 void mlx5dr_rule_set_last_member(struct mlx5dr_rule_rx_tx *nic_rule,
1014 struct mlx5dr_ste *ste,
1015 bool force);
1016 int mlx5dr_rule_get_reverse_rule_members(struct mlx5dr_ste **ste_arr,
1017 struct mlx5dr_ste *curr_ste,
1018 int *num_of_stes);
1019
1020 struct mlx5dr_icm_chunk {
1021 struct mlx5dr_icm_buddy_mem *buddy_mem;
1022 struct list_head chunk_list;
1023 u32 rkey;
1024 u32 num_of_entries;
1025 u32 byte_size;
1026 u64 icm_addr;
1027 u64 mr_addr;
1028
1029 /* indicates the index of this chunk in the whole memory,
1030 * used for deleting the chunk from the buddy
1031 */
1032 unsigned int seg;
1033
1034 /* Memory optimisation */
1035 struct mlx5dr_ste *ste_arr;
1036 u8 *hw_ste_arr;
1037 struct list_head *miss_list;
1038 };
1039
mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx * nic_dmn)1040 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn)
1041 {
1042 mutex_lock(&nic_dmn->mutex);
1043 }
1044
mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx * nic_dmn)1045 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn)
1046 {
1047 mutex_unlock(&nic_dmn->mutex);
1048 }
1049
mlx5dr_domain_lock(struct mlx5dr_domain * dmn)1050 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn)
1051 {
1052 mlx5dr_domain_nic_lock(&dmn->info.rx);
1053 mlx5dr_domain_nic_lock(&dmn->info.tx);
1054 }
1055
mlx5dr_domain_unlock(struct mlx5dr_domain * dmn)1056 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn)
1057 {
1058 mlx5dr_domain_nic_unlock(&dmn->info.tx);
1059 mlx5dr_domain_nic_unlock(&dmn->info.rx);
1060 }
1061
1062 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher,
1063 struct mlx5dr_matcher_rx_tx *nic_matcher,
1064 enum mlx5dr_ipv outer_ipv,
1065 enum mlx5dr_ipv inner_ipv);
1066
1067 static inline int
mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type)1068 mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type)
1069 {
1070 if (icm_type == DR_ICM_TYPE_STE)
1071 return DR_STE_SIZE;
1072
1073 return DR_MODIFY_ACTION_SIZE;
1074 }
1075
1076 static inline u32
mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)1077 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)
1078 {
1079 return 1 << chunk_size;
1080 }
1081
1082 static inline int
mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,enum mlx5dr_icm_type icm_type)1083 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,
1084 enum mlx5dr_icm_type icm_type)
1085 {
1086 int num_of_entries;
1087 int entry_size;
1088
1089 entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type);
1090 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size);
1091
1092 return entry_size * num_of_entries;
1093 }
1094
1095 static inline int
mlx5dr_ste_htbl_increase_threshold(struct mlx5dr_ste_htbl * htbl)1096 mlx5dr_ste_htbl_increase_threshold(struct mlx5dr_ste_htbl *htbl)
1097 {
1098 int num_of_entries =
1099 mlx5dr_icm_pool_chunk_size_to_entries(htbl->chunk_size);
1100
1101 /* Threshold is 50%, one is added to table of size 1 */
1102 return (num_of_entries + 1) / 2;
1103 }
1104
1105 static inline bool
mlx5dr_ste_htbl_may_grow(struct mlx5dr_ste_htbl * htbl)1106 mlx5dr_ste_htbl_may_grow(struct mlx5dr_ste_htbl *htbl)
1107 {
1108 if (htbl->chunk_size == DR_CHUNK_SIZE_MAX - 1 || !htbl->byte_mask)
1109 return false;
1110
1111 return true;
1112 }
1113
1114 static inline struct mlx5dr_cmd_vport_cap *
mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps * caps,u32 vport)1115 mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport)
1116 {
1117 if (!caps->vports_caps ||
1118 (vport >= caps->num_vports && vport != MLX5_VPORT_UPLINK))
1119 return NULL;
1120
1121 if (vport == MLX5_VPORT_UPLINK)
1122 vport = caps->num_vports;
1123
1124 return &caps->vports_caps[vport];
1125 }
1126
1127 struct mlx5dr_cmd_query_flow_table_details {
1128 u8 status;
1129 u8 level;
1130 u64 sw_owner_icm_root_1;
1131 u64 sw_owner_icm_root_0;
1132 };
1133
1134 struct mlx5dr_cmd_create_flow_table_attr {
1135 u32 table_type;
1136 u64 icm_addr_rx;
1137 u64 icm_addr_tx;
1138 u8 level;
1139 bool sw_owner;
1140 bool term_tbl;
1141 bool decap_en;
1142 bool reformat_en;
1143 };
1144
1145 /* internal API functions */
1146 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
1147 struct mlx5dr_cmd_caps *caps);
1148 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
1149 bool other_vport, u16 vport_number,
1150 u64 *icm_address_rx,
1151 u64 *icm_address_tx);
1152 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev,
1153 bool other_vport, u16 vport_number, u16 *gvmi);
1154 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
1155 struct mlx5dr_esw_caps *caps);
1156 int mlx5dr_cmd_query_flow_sampler(struct mlx5_core_dev *dev,
1157 u32 sampler_id,
1158 u64 *rx_icm_addr,
1159 u64 *tx_icm_addr);
1160 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev);
1161 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
1162 u32 table_type,
1163 u32 table_id,
1164 u32 group_id,
1165 u32 modify_header_id,
1166 u32 vport_id);
1167 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
1168 u32 table_type,
1169 u32 table_id);
1170 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
1171 u32 table_type,
1172 u8 num_of_actions,
1173 u64 *actions,
1174 u32 *modify_header_id);
1175 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
1176 u32 modify_header_id);
1177 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
1178 u32 table_type,
1179 u32 table_id,
1180 u32 *group_id);
1181 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
1182 u32 table_type,
1183 u32 table_id,
1184 u32 group_id);
1185 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
1186 struct mlx5dr_cmd_create_flow_table_attr *attr,
1187 u64 *fdb_rx_icm_addr,
1188 u32 *table_id);
1189 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
1190 u32 table_id,
1191 u32 table_type);
1192 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
1193 enum fs_flow_table_type type,
1194 u32 table_id,
1195 struct mlx5dr_cmd_query_flow_table_details *output);
1196 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
1197 enum mlx5_reformat_ctx_type rt,
1198 u8 reformat_param_0,
1199 u8 reformat_param_1,
1200 size_t reformat_size,
1201 void *reformat_data,
1202 u32 *reformat_id);
1203 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
1204 u32 reformat_id);
1205
1206 struct mlx5dr_cmd_gid_attr {
1207 u8 gid[16];
1208 u8 mac[6];
1209 u32 roce_ver;
1210 };
1211
1212 struct mlx5dr_cmd_qp_create_attr {
1213 u32 page_id;
1214 u32 pdn;
1215 u32 cqn;
1216 u32 pm_state;
1217 u32 service_type;
1218 u32 buff_umem_id;
1219 u32 db_umem_id;
1220 u32 sq_wqe_cnt;
1221 u32 rq_wqe_cnt;
1222 u32 rq_wqe_shift;
1223 u8 isolate_vl_tc:1;
1224 };
1225
1226 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
1227 u16 index, struct mlx5dr_cmd_gid_attr *attr);
1228
1229 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn,
1230 enum mlx5dr_icm_type icm_type);
1231 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool);
1232
1233 struct mlx5dr_icm_chunk *
1234 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool,
1235 enum mlx5dr_icm_chunk_size chunk_size);
1236 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk);
1237
1238 void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx,
1239 u8 *hw_ste_p, u32 ste_size);
1240 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn,
1241 struct mlx5dr_domain_rx_tx *nic_dmn,
1242 struct mlx5dr_ste_htbl *htbl,
1243 struct mlx5dr_htbl_connect_info *connect_info,
1244 bool update_hw_ste);
1245 void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
1246 u16 gvmi,
1247 enum mlx5dr_domain_nic_type nic_type,
1248 struct mlx5dr_ste_htbl *htbl,
1249 u8 *formatted_ste,
1250 struct mlx5dr_htbl_connect_info *connect_info);
1251 void mlx5dr_ste_copy_param(u8 match_criteria,
1252 struct mlx5dr_match_param *set_param,
1253 struct mlx5dr_match_parameters *mask);
1254
1255 struct mlx5dr_qp {
1256 struct mlx5_core_dev *mdev;
1257 struct mlx5_wq_qp wq;
1258 struct mlx5_uars_page *uar;
1259 struct mlx5_wq_ctrl wq_ctrl;
1260 u32 qpn;
1261 struct {
1262 unsigned int pc;
1263 unsigned int cc;
1264 unsigned int size;
1265 unsigned int *wqe_head;
1266 unsigned int wqe_cnt;
1267 } sq;
1268 struct {
1269 unsigned int pc;
1270 unsigned int cc;
1271 unsigned int size;
1272 unsigned int wqe_cnt;
1273 } rq;
1274 int max_inline_data;
1275 };
1276
1277 struct mlx5dr_cq {
1278 struct mlx5_core_dev *mdev;
1279 struct mlx5_cqwq wq;
1280 struct mlx5_wq_ctrl wq_ctrl;
1281 struct mlx5_core_cq mcq;
1282 struct mlx5dr_qp *qp;
1283 };
1284
1285 struct mlx5dr_mr {
1286 struct mlx5_core_dev *mdev;
1287 struct mlx5_core_mkey mkey;
1288 dma_addr_t dma_addr;
1289 void *addr;
1290 size_t size;
1291 };
1292
1293 #define MAX_SEND_CQE 64
1294 #define MIN_READ_SYNC 64
1295
1296 struct mlx5dr_send_ring {
1297 struct mlx5dr_cq *cq;
1298 struct mlx5dr_qp *qp;
1299 struct mlx5dr_mr *mr;
1300 /* How much wqes are waiting for completion */
1301 u32 pending_wqe;
1302 /* Signal request per this trash hold value */
1303 u16 signal_th;
1304 /* Each post_send_size less than max_post_send_size */
1305 u32 max_post_send_size;
1306 /* manage the send queue */
1307 u32 tx_head;
1308 void *buf;
1309 u32 buf_size;
1310 u8 sync_buff[MIN_READ_SYNC];
1311 struct mlx5dr_mr *sync_mr;
1312 spinlock_t lock; /* Protect the data path of the send ring */
1313 bool err_state; /* send_ring is not usable in err state */
1314 };
1315
1316 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn);
1317 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn,
1318 struct mlx5dr_send_ring *send_ring);
1319 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn);
1320 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn,
1321 struct mlx5dr_ste *ste,
1322 u8 *data,
1323 u16 size,
1324 u16 offset);
1325 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
1326 struct mlx5dr_ste_htbl *htbl,
1327 u8 *formatted_ste, u8 *mask);
1328 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
1329 struct mlx5dr_ste_htbl *htbl,
1330 u8 *ste_init_data,
1331 bool update_hw_ste);
1332 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn,
1333 struct mlx5dr_action *action);
1334
1335 struct mlx5dr_cmd_ft_info {
1336 u32 id;
1337 u16 vport;
1338 enum fs_flow_table_type type;
1339 };
1340
1341 struct mlx5dr_cmd_flow_destination_hw_info {
1342 enum mlx5_flow_destination_type type;
1343 union {
1344 u32 tir_num;
1345 u32 ft_num;
1346 u32 ft_id;
1347 u32 counter_id;
1348 u32 sampler_id;
1349 struct {
1350 u16 num;
1351 u16 vhca_id;
1352 u32 reformat_id;
1353 u8 flags;
1354 } vport;
1355 };
1356 };
1357
1358 struct mlx5dr_cmd_fte_info {
1359 u32 dests_size;
1360 u32 index;
1361 struct mlx5_flow_context flow_context;
1362 u32 *val;
1363 struct mlx5_flow_act action;
1364 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr;
1365 bool ignore_flow_level;
1366 };
1367
1368 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
1369 int opmod, int modify_mask,
1370 struct mlx5dr_cmd_ft_info *ft,
1371 u32 group_id,
1372 struct mlx5dr_cmd_fte_info *fte);
1373
1374 bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps);
1375
1376 struct mlx5dr_fw_recalc_cs_ft {
1377 u64 rx_icm_addr;
1378 u32 table_id;
1379 u32 group_id;
1380 u32 modify_hdr_id;
1381 };
1382
1383 struct mlx5dr_fw_recalc_cs_ft *
1384 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num);
1385 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn,
1386 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft);
1387 int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn,
1388 u32 vport_num,
1389 u64 *rx_icm_addr);
1390 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
1391 struct mlx5dr_cmd_flow_destination_hw_info *dest,
1392 int num_dest,
1393 bool reformat_req,
1394 u32 *tbl_id,
1395 u32 *group_id,
1396 bool ignore_flow_level,
1397 u32 flow_source);
1398 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id,
1399 u32 group_id);
1400 #endif /* _DR_TYPES_H_ */
1401