1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16
17 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
18 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
19
20 /*
21 * Supported formats.
22 */
23
24 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
25 {
26 .fourcc = V4L2_PIX_FMT_YUV420M,
27 .codec_mode = HANTRO_MODE_NONE,
28 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
29 },
30 {
31 .fourcc = V4L2_PIX_FMT_NV12M,
32 .codec_mode = HANTRO_MODE_NONE,
33 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
34 },
35 {
36 .fourcc = V4L2_PIX_FMT_YUYV,
37 .codec_mode = HANTRO_MODE_NONE,
38 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
39 },
40 {
41 .fourcc = V4L2_PIX_FMT_UYVY,
42 .codec_mode = HANTRO_MODE_NONE,
43 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
44 },
45 {
46 .fourcc = V4L2_PIX_FMT_JPEG,
47 .codec_mode = HANTRO_MODE_JPEG_ENC,
48 .max_depth = 2,
49 .header_size = JPEG_HEADER_SIZE,
50 .frmsize = {
51 .min_width = 96,
52 .max_width = 8192,
53 .step_width = MB_DIM,
54 .min_height = 32,
55 .max_height = 8192,
56 .step_height = MB_DIM,
57 },
58 },
59 };
60
61 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
62 {
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .codec_mode = HANTRO_MODE_NONE,
65 .postprocessed = true,
66 },
67 };
68
69 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
70 {
71 .fourcc = V4L2_PIX_FMT_NV12,
72 .codec_mode = HANTRO_MODE_NONE,
73 },
74 {
75 .fourcc = V4L2_PIX_FMT_H264_SLICE,
76 .codec_mode = HANTRO_MODE_H264_DEC,
77 .max_depth = 2,
78 .frmsize = {
79 .min_width = 48,
80 .max_width = 1920,
81 .step_width = MB_DIM,
82 .min_height = 48,
83 .max_height = 1088,
84 .step_height = MB_DIM,
85 },
86 },
87 {
88 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
89 .codec_mode = HANTRO_MODE_MPEG2_DEC,
90 .max_depth = 2,
91 .frmsize = {
92 .min_width = 48,
93 .max_width = 1920,
94 .step_width = MB_DIM,
95 .min_height = 48,
96 .max_height = 1088,
97 .step_height = MB_DIM,
98 },
99 },
100 {
101 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
102 .codec_mode = HANTRO_MODE_VP8_DEC,
103 .max_depth = 2,
104 .frmsize = {
105 .min_width = 48,
106 .max_width = 1920,
107 .step_width = MB_DIM,
108 .min_height = 48,
109 .max_height = 1088,
110 .step_height = MB_DIM,
111 },
112 },
113 };
114
115 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
116 {
117 .fourcc = V4L2_PIX_FMT_NV12,
118 .codec_mode = HANTRO_MODE_NONE,
119 },
120 {
121 .fourcc = V4L2_PIX_FMT_H264_SLICE,
122 .codec_mode = HANTRO_MODE_H264_DEC,
123 .max_depth = 2,
124 .frmsize = {
125 .min_width = 48,
126 .max_width = 4096,
127 .step_width = MB_DIM,
128 .min_height = 48,
129 .max_height = 2304,
130 .step_height = MB_DIM,
131 },
132 },
133 {
134 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
135 .codec_mode = HANTRO_MODE_MPEG2_DEC,
136 .max_depth = 2,
137 .frmsize = {
138 .min_width = 48,
139 .max_width = 1920,
140 .step_width = MB_DIM,
141 .min_height = 48,
142 .max_height = 1088,
143 .step_height = MB_DIM,
144 },
145 },
146 {
147 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
148 .codec_mode = HANTRO_MODE_VP8_DEC,
149 .max_depth = 2,
150 .frmsize = {
151 .min_width = 48,
152 .max_width = 3840,
153 .step_width = MB_DIM,
154 .min_height = 48,
155 .max_height = 2160,
156 .step_height = MB_DIM,
157 },
158 },
159 };
160
161 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
162 {
163 .fourcc = V4L2_PIX_FMT_NV12,
164 .codec_mode = HANTRO_MODE_NONE,
165 },
166 {
167 .fourcc = V4L2_PIX_FMT_H264_SLICE,
168 .codec_mode = HANTRO_MODE_H264_DEC,
169 .max_depth = 2,
170 .frmsize = {
171 .min_width = 48,
172 .max_width = 1920,
173 .step_width = MB_DIM,
174 .min_height = 48,
175 .max_height = 1088,
176 .step_height = MB_DIM,
177 },
178 },
179 {
180 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
181 .codec_mode = HANTRO_MODE_MPEG2_DEC,
182 .max_depth = 2,
183 .frmsize = {
184 .min_width = 48,
185 .max_width = 1920,
186 .step_width = MB_DIM,
187 .min_height = 48,
188 .max_height = 1088,
189 .step_height = MB_DIM,
190 },
191 },
192 {
193 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
194 .codec_mode = HANTRO_MODE_VP8_DEC,
195 .max_depth = 2,
196 .frmsize = {
197 .min_width = 48,
198 .max_width = 3840,
199 .step_width = MB_DIM,
200 .min_height = 48,
201 .max_height = 2160,
202 .step_height = MB_DIM,
203 },
204 },
205 };
206
rockchip_vpu1_vepu_irq(int irq,void * dev_id)207 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
208 {
209 struct hantro_dev *vpu = dev_id;
210 enum vb2_buffer_state state;
211 u32 status;
212
213 status = vepu_read(vpu, H1_REG_INTERRUPT);
214 state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
215 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
216
217 vepu_write(vpu, 0, H1_REG_INTERRUPT);
218 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
219
220 hantro_irq_done(vpu, state);
221
222 return IRQ_HANDLED;
223 }
224
rockchip_vpu2_vdpu_irq(int irq,void * dev_id)225 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
226 {
227 struct hantro_dev *vpu = dev_id;
228 enum vb2_buffer_state state;
229 u32 status;
230
231 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
232 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
233 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
234
235 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
236 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
237
238 hantro_irq_done(vpu, state);
239
240 return IRQ_HANDLED;
241 }
242
rockchip_vpu2_vepu_irq(int irq,void * dev_id)243 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
244 {
245 struct hantro_dev *vpu = dev_id;
246 enum vb2_buffer_state state;
247 u32 status;
248
249 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
250 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
251 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
252
253 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
254 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
255
256 hantro_irq_done(vpu, state);
257
258 return IRQ_HANDLED;
259 }
260
rk3036_vpu_hw_init(struct hantro_dev * vpu)261 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
262 {
263 /* Bump ACLK to max. possible freq. to improve performance. */
264 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
265 return 0;
266 }
267
rk3066_vpu_hw_init(struct hantro_dev * vpu)268 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
269 {
270 /* Bump ACLKs to max. possible freq. to improve performance. */
271 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
272 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
273 return 0;
274 }
275
rockchip_vpu_hw_init(struct hantro_dev * vpu)276 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
277 {
278 /* Bump ACLK to max. possible freq. to improve performance. */
279 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
280 return 0;
281 }
282
rk3066_vpu_dec_reset(struct hantro_ctx * ctx)283 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
284 {
285 struct hantro_dev *vpu = ctx->dev;
286
287 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
288 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
289 }
290
rockchip_vpu1_enc_reset(struct hantro_ctx * ctx)291 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
292 {
293 struct hantro_dev *vpu = ctx->dev;
294
295 vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
296 vepu_write(vpu, 0, H1_REG_ENC_CTRL);
297 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
298 }
299
rockchip_vpu2_dec_reset(struct hantro_ctx * ctx)300 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
301 {
302 struct hantro_dev *vpu = ctx->dev;
303
304 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
305 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
306 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
307 }
308
rockchip_vpu2_enc_reset(struct hantro_ctx * ctx)309 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
310 {
311 struct hantro_dev *vpu = ctx->dev;
312
313 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
314 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
315 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
316 }
317
318 /*
319 * Supported codec ops.
320 */
321 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
322 [HANTRO_MODE_H264_DEC] = {
323 .run = hantro_g1_h264_dec_run,
324 .reset = hantro_g1_reset,
325 .init = hantro_h264_dec_init,
326 .exit = hantro_h264_dec_exit,
327 },
328 [HANTRO_MODE_MPEG2_DEC] = {
329 .run = hantro_g1_mpeg2_dec_run,
330 .reset = hantro_g1_reset,
331 .init = hantro_mpeg2_dec_init,
332 .exit = hantro_mpeg2_dec_exit,
333 },
334 [HANTRO_MODE_VP8_DEC] = {
335 .run = hantro_g1_vp8_dec_run,
336 .reset = hantro_g1_reset,
337 .init = hantro_vp8_dec_init,
338 .exit = hantro_vp8_dec_exit,
339 },
340 };
341
342 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
343 [HANTRO_MODE_JPEG_ENC] = {
344 .run = hantro_h1_jpeg_enc_run,
345 .reset = rockchip_vpu1_enc_reset,
346 .init = hantro_jpeg_enc_init,
347 .done = hantro_h1_jpeg_enc_done,
348 .exit = hantro_jpeg_enc_exit,
349 },
350 [HANTRO_MODE_H264_DEC] = {
351 .run = hantro_g1_h264_dec_run,
352 .reset = rk3066_vpu_dec_reset,
353 .init = hantro_h264_dec_init,
354 .exit = hantro_h264_dec_exit,
355 },
356 [HANTRO_MODE_MPEG2_DEC] = {
357 .run = hantro_g1_mpeg2_dec_run,
358 .reset = rk3066_vpu_dec_reset,
359 .init = hantro_mpeg2_dec_init,
360 .exit = hantro_mpeg2_dec_exit,
361 },
362 [HANTRO_MODE_VP8_DEC] = {
363 .run = hantro_g1_vp8_dec_run,
364 .reset = rk3066_vpu_dec_reset,
365 .init = hantro_vp8_dec_init,
366 .exit = hantro_vp8_dec_exit,
367 },
368 };
369
370 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
371 [HANTRO_MODE_JPEG_ENC] = {
372 .run = hantro_h1_jpeg_enc_run,
373 .reset = rockchip_vpu1_enc_reset,
374 .init = hantro_jpeg_enc_init,
375 .done = hantro_h1_jpeg_enc_done,
376 .exit = hantro_jpeg_enc_exit,
377 },
378 [HANTRO_MODE_H264_DEC] = {
379 .run = hantro_g1_h264_dec_run,
380 .reset = hantro_g1_reset,
381 .init = hantro_h264_dec_init,
382 .exit = hantro_h264_dec_exit,
383 },
384 [HANTRO_MODE_MPEG2_DEC] = {
385 .run = hantro_g1_mpeg2_dec_run,
386 .reset = hantro_g1_reset,
387 .init = hantro_mpeg2_dec_init,
388 .exit = hantro_mpeg2_dec_exit,
389 },
390 [HANTRO_MODE_VP8_DEC] = {
391 .run = hantro_g1_vp8_dec_run,
392 .reset = hantro_g1_reset,
393 .init = hantro_vp8_dec_init,
394 .exit = hantro_vp8_dec_exit,
395 },
396 };
397
398 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
399 [HANTRO_MODE_JPEG_ENC] = {
400 .run = rockchip_vpu2_jpeg_enc_run,
401 .reset = rockchip_vpu2_enc_reset,
402 .init = hantro_jpeg_enc_init,
403 .done = rockchip_vpu2_jpeg_enc_done,
404 .exit = hantro_jpeg_enc_exit,
405 },
406 [HANTRO_MODE_H264_DEC] = {
407 .run = rockchip_vpu2_h264_dec_run,
408 .reset = rockchip_vpu2_dec_reset,
409 .init = hantro_h264_dec_init,
410 .exit = hantro_h264_dec_exit,
411 },
412 [HANTRO_MODE_MPEG2_DEC] = {
413 .run = rockchip_vpu2_mpeg2_dec_run,
414 .reset = rockchip_vpu2_dec_reset,
415 .init = hantro_mpeg2_dec_init,
416 .exit = hantro_mpeg2_dec_exit,
417 },
418 [HANTRO_MODE_VP8_DEC] = {
419 .run = rockchip_vpu2_vp8_dec_run,
420 .reset = rockchip_vpu2_dec_reset,
421 .init = hantro_vp8_dec_init,
422 .exit = hantro_vp8_dec_exit,
423 },
424 };
425
426 /*
427 * VPU variant.
428 */
429
430 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
431 { "vdpu", hantro_g1_irq },
432 };
433
434 static const struct hantro_irq rockchip_vpu1_irqs[] = {
435 { "vepu", rockchip_vpu1_vepu_irq },
436 { "vdpu", hantro_g1_irq },
437 };
438
439 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
440 { "vdpu", rockchip_vpu2_vdpu_irq },
441 };
442
443 static const struct hantro_irq rockchip_vpu2_irqs[] = {
444 { "vepu", rockchip_vpu2_vepu_irq },
445 { "vdpu", rockchip_vpu2_vdpu_irq },
446 };
447
448 static const char * const rk3066_vpu_clk_names[] = {
449 "aclk_vdpu", "hclk_vdpu",
450 "aclk_vepu", "hclk_vepu"
451 };
452
453 static const char * const rockchip_vpu_clk_names[] = {
454 "aclk", "hclk"
455 };
456
457 /* VDPU1/VEPU1 */
458
459 const struct hantro_variant rk3036_vpu_variant = {
460 .dec_offset = 0x400,
461 .dec_fmts = rk3066_vpu_dec_fmts,
462 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
463 .postproc_fmts = rockchip_vpu1_postproc_fmts,
464 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
465 .postproc_regs = &hantro_g1_postproc_regs,
466 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
467 HANTRO_H264_DECODER,
468 .codec_ops = rk3036_vpu_codec_ops,
469 .irqs = rockchip_vdpu1_irqs,
470 .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
471 .init = rk3036_vpu_hw_init,
472 .clk_names = rockchip_vpu_clk_names,
473 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
474 };
475
476 /*
477 * Despite this variant has separate clocks for decoder and encoder,
478 * it's still required to enable all four of them for either decoding
479 * or encoding and we can't split it in separate g1/h1 variants.
480 */
481 const struct hantro_variant rk3066_vpu_variant = {
482 .enc_offset = 0x0,
483 .enc_fmts = rockchip_vpu_enc_fmts,
484 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
485 .dec_offset = 0x400,
486 .dec_fmts = rk3066_vpu_dec_fmts,
487 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
488 .postproc_fmts = rockchip_vpu1_postproc_fmts,
489 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
490 .postproc_regs = &hantro_g1_postproc_regs,
491 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
492 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
493 .codec_ops = rk3066_vpu_codec_ops,
494 .irqs = rockchip_vpu1_irqs,
495 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
496 .init = rk3066_vpu_hw_init,
497 .clk_names = rk3066_vpu_clk_names,
498 .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
499 };
500
501 const struct hantro_variant rk3288_vpu_variant = {
502 .enc_offset = 0x0,
503 .enc_fmts = rockchip_vpu_enc_fmts,
504 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
505 .dec_offset = 0x400,
506 .dec_fmts = rk3288_vpu_dec_fmts,
507 .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
508 .postproc_fmts = rockchip_vpu1_postproc_fmts,
509 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
510 .postproc_regs = &hantro_g1_postproc_regs,
511 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
512 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
513 .codec_ops = rk3288_vpu_codec_ops,
514 .irqs = rockchip_vpu1_irqs,
515 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
516 .init = rockchip_vpu_hw_init,
517 .clk_names = rockchip_vpu_clk_names,
518 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
519 };
520
521 /* VDPU2/VEPU2 */
522
523 const struct hantro_variant rk3328_vpu_variant = {
524 .dec_offset = 0x400,
525 .dec_fmts = rk3399_vpu_dec_fmts,
526 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
527 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
528 HANTRO_H264_DECODER,
529 .codec_ops = rk3399_vpu_codec_ops,
530 .irqs = rockchip_vdpu2_irqs,
531 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
532 .init = rockchip_vpu_hw_init,
533 .clk_names = rockchip_vpu_clk_names,
534 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
535 };
536
537 const struct hantro_variant rk3399_vpu_variant = {
538 .enc_offset = 0x0,
539 .enc_fmts = rockchip_vpu_enc_fmts,
540 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
541 .dec_offset = 0x400,
542 .dec_fmts = rk3399_vpu_dec_fmts,
543 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
544 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
545 HANTRO_VP8_DECODER,
546 .codec_ops = rk3399_vpu_codec_ops,
547 .irqs = rockchip_vpu2_irqs,
548 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
549 .init = rockchip_vpu_hw_init,
550 .clk_names = rockchip_vpu_clk_names,
551 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
552 };
553
554 const struct hantro_variant px30_vpu_variant = {
555 .enc_offset = 0x0,
556 .enc_fmts = rockchip_vpu_enc_fmts,
557 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
558 .dec_offset = 0x400,
559 .dec_fmts = rk3399_vpu_dec_fmts,
560 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
561 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
562 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
563 .codec_ops = rk3399_vpu_codec_ops,
564 .irqs = rockchip_vpu2_irqs,
565 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
566 .init = rk3036_vpu_hw_init,
567 .clk_names = rockchip_vpu_clk_names,
568 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
569 };
570