1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
35
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43
44 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
45 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
46
47 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
48 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
49
50 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
51 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
52 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
53 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
54 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
55
56 #define UART_EXAR_INT0 0x80
57 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
58 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
59 #define UART_EXAR_DVID 0x8d /* Device identification */
60
61 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
62 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
63 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
64 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
65 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
66 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
67 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
68
69 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
70 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
71
72 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
73 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
74 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
75 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
76 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
77 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
78 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
79 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
80 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
81 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
82 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
83 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
84
85 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
86
87 /*
88 * IOT2040 MPIO wiring semantics:
89 *
90 * MPIO Port Function
91 * ---- ---- --------
92 * 0 2 Mode bit 0
93 * 1 2 Mode bit 1
94 * 2 2 Terminate bus
95 * 3 - <reserved>
96 * 4 3 Mode bit 0
97 * 5 3 Mode bit 1
98 * 6 3 Terminate bus
99 * 7 - <reserved>
100 * 8 2 Enable
101 * 9 3 Enable
102 * 10 - Red LED
103 * 11..15 - <unused>
104 */
105
106 /* IOT2040 MPIOs 0..7 */
107 #define IOT2040_UART_MODE_RS232 0x01
108 #define IOT2040_UART_MODE_RS485 0x02
109 #define IOT2040_UART_MODE_RS422 0x03
110 #define IOT2040_UART_TERMINATE_BUS 0x04
111
112 #define IOT2040_UART1_MASK 0x0f
113 #define IOT2040_UART2_SHIFT 4
114
115 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
116 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
117
118 /* IOT2040 MPIOs 8..15 */
119 #define IOT2040_UARTS_ENABLE 0x03
120 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
121
122 struct exar8250;
123
124 struct exar8250_platform {
125 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
126 const struct serial_rs485 *rs485_supported;
127 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
128 void (*unregister_gpio)(struct uart_8250_port *);
129 };
130
131 /**
132 * struct exar8250_board - board information
133 * @num_ports: number of serial ports
134 * @reg_shift: describes UART register mapping in PCI memory
135 * @setup: quirk run at ->probe() stage
136 * @exit: quirk run at ->remove() stage
137 */
138 struct exar8250_board {
139 unsigned int num_ports;
140 unsigned int reg_shift;
141 int (*setup)(struct exar8250 *, struct pci_dev *,
142 struct uart_8250_port *, int);
143 void (*exit)(struct pci_dev *pcidev);
144 };
145
146 struct exar8250 {
147 unsigned int nr;
148 struct exar8250_board *board;
149 void __iomem *virt;
150 int line[];
151 };
152
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)153 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
154 {
155 /*
156 * Exar UARTs have a SLEEP register that enables or disables each UART
157 * to enter sleep mode separately. On the XR17V35x the register
158 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
159 * the UART channel may only write to the corresponding bit.
160 */
161 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
162 }
163
164 /*
165 * XR17V35x UARTs have an extra fractional divisor register (DLD)
166 * Calculate divisor with extra 4-bit fractional portion
167 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)168 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
169 unsigned int *frac)
170 {
171 unsigned int quot_16;
172
173 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
174 *frac = quot_16 & 0x0f;
175
176 return quot_16 >> 4;
177 }
178
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)179 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
180 unsigned int quot, unsigned int quot_frac)
181 {
182 serial8250_do_set_divisor(p, baud, quot, quot_frac);
183
184 /* Preserve bits not related to baudrate; DLD[7:4]. */
185 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
186 serial_port_out(p, 0x2, quot_frac);
187 }
188
xr17v35x_startup(struct uart_port * port)189 static int xr17v35x_startup(struct uart_port *port)
190 {
191 /*
192 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
193 * MCR [7:5] and MSR [7:0]
194 */
195 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
196
197 /*
198 * Make sure all interrups are masked until initialization is
199 * complete and the FIFOs are cleared
200 */
201 serial_port_out(port, UART_IER, 0);
202
203 return serial8250_do_startup(port);
204 }
205
exar_shutdown(struct uart_port * port)206 static void exar_shutdown(struct uart_port *port)
207 {
208 unsigned char lsr;
209 bool tx_complete = false;
210 struct uart_8250_port *up = up_to_u8250p(port);
211 struct circ_buf *xmit = &port->state->xmit;
212 int i = 0;
213
214 do {
215 lsr = serial_in(up, UART_LSR);
216 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
217 tx_complete = true;
218 else
219 tx_complete = false;
220 usleep_range(1000, 1100);
221 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
222
223 serial8250_do_shutdown(port);
224 }
225
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)226 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
227 int idx, unsigned int offset,
228 struct uart_8250_port *port)
229 {
230 const struct exar8250_board *board = priv->board;
231 unsigned int bar = 0;
232 unsigned char status;
233
234 port->port.iotype = UPIO_MEM;
235 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
236 port->port.membase = priv->virt + offset;
237 port->port.regshift = board->reg_shift;
238
239 /*
240 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
241 * with when DLAB is set which will cause the device to incorrectly match
242 * and assign port type to PORT_16650. The EFR for this UART is found
243 * at offset 0x09. Instead check the Deice ID (DVID) register
244 * for a 2, 4 or 8 port UART.
245 */
246 status = readb(port->port.membase + UART_EXAR_DVID);
247 if (status == 0x82 || status == 0x84 || status == 0x88) {
248 port->port.type = PORT_XR17V35X;
249
250 port->port.get_divisor = xr17v35x_get_divisor;
251 port->port.set_divisor = xr17v35x_set_divisor;
252
253 port->port.startup = xr17v35x_startup;
254 } else {
255 port->port.type = PORT_XR17D15X;
256 }
257
258 port->port.pm = exar_pm;
259 port->port.shutdown = exar_shutdown;
260
261 return 0;
262 }
263
264 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)265 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
266 struct uart_8250_port *port, int idx)
267 {
268 unsigned int offset = idx * 0x200;
269 unsigned int baud = 1843200;
270 u8 __iomem *p;
271 int err;
272
273 port->port.uartclk = baud * 16;
274
275 err = default_setup(priv, pcidev, idx, offset, port);
276 if (err)
277 return err;
278
279 p = port->port.membase;
280
281 writeb(0x00, p + UART_EXAR_8XMODE);
282 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
283 writeb(32, p + UART_EXAR_TXTRG);
284 writeb(32, p + UART_EXAR_RXTRG);
285
286 /*
287 * Setup Multipurpose Input/Output pins.
288 */
289 if (idx == 0) {
290 switch (pcidev->device) {
291 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
292 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
293 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
294 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
295 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
296 break;
297 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
298 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
299 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
300 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
301 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
302 break;
303 }
304 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
305 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
306 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
307 }
308
309 return 0;
310 }
311
312 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)313 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
314 struct uart_8250_port *port, int idx)
315 {
316 unsigned int offset = idx * 0x200;
317 unsigned int baud = 1843200;
318
319 port->port.uartclk = baud * 16;
320 return default_setup(priv, pcidev, idx, offset, port);
321 }
322
323 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)324 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
325 struct uart_8250_port *port, int idx)
326 {
327 unsigned int offset = idx * 0x200;
328 unsigned int baud = 921600;
329
330 port->port.uartclk = baud * 16;
331 return default_setup(priv, pcidev, idx, offset, port);
332 }
333
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)334 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
335 {
336 /*
337 * The Commtech adapters required the MPIOs to be driven low. The Exar
338 * devices will export them as GPIOs, so we pre-configure them safely
339 * as inputs.
340 */
341
342 u8 dir = 0x00;
343
344 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
345 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
346 // Configure GPIO as inputs for Commtech adapters
347 dir = 0xff;
348 } else {
349 // Configure GPIO as outputs for SeaLevel adapters
350 dir = 0x00;
351 }
352
353 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
354 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
355 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
356 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
357 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
358 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
359 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
360 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
361 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
362 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
363 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
364 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
365 }
366
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)367 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
368 const struct software_node *node)
369 {
370 struct platform_device *pdev;
371
372 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
373 if (!pdev)
374 return NULL;
375
376 pdev->dev.parent = &pcidev->dev;
377 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
378
379 if (device_add_software_node(&pdev->dev, node) < 0 ||
380 platform_device_add(pdev) < 0) {
381 platform_device_put(pdev);
382 return NULL;
383 }
384
385 return pdev;
386 }
387
__xr17v35x_unregister_gpio(struct platform_device * pdev)388 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
389 {
390 device_remove_software_node(&pdev->dev);
391 platform_device_unregister(pdev);
392 }
393
394 static const struct property_entry exar_gpio_properties[] = {
395 PROPERTY_ENTRY_U32("exar,first-pin", 0),
396 PROPERTY_ENTRY_U32("ngpios", 16),
397 { }
398 };
399
400 static const struct software_node exar_gpio_node = {
401 .properties = exar_gpio_properties,
402 };
403
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)404 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
405 {
406 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
407 port->port.private_data =
408 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
409
410 return 0;
411 }
412
xr17v35x_unregister_gpio(struct uart_8250_port * port)413 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
414 {
415 if (!port->port.private_data)
416 return;
417
418 __xr17v35x_unregister_gpio(port->port.private_data);
419 port->port.private_data = NULL;
420 }
421
generic_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)422 static int generic_rs485_config(struct uart_port *port,
423 struct serial_rs485 *rs485)
424 {
425 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
426 u8 __iomem *p = port->membase;
427 u8 value;
428
429 value = readb(p + UART_EXAR_FCTR);
430 if (is_rs485)
431 value |= UART_FCTR_EXAR_485;
432 else
433 value &= ~UART_FCTR_EXAR_485;
434
435 writeb(value, p + UART_EXAR_FCTR);
436
437 if (is_rs485)
438 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
439
440 port->rs485 = *rs485;
441
442 return 0;
443 }
444
445 static const struct serial_rs485 generic_rs485_supported = {
446 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
447 };
448
449 static const struct exar8250_platform exar8250_default_platform = {
450 .register_gpio = xr17v35x_register_gpio,
451 .unregister_gpio = xr17v35x_unregister_gpio,
452 .rs485_config = generic_rs485_config,
453 .rs485_supported = &generic_rs485_supported,
454 };
455
iot2040_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)456 static int iot2040_rs485_config(struct uart_port *port,
457 struct serial_rs485 *rs485)
458 {
459 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
460 u8 __iomem *p = port->membase;
461 u8 mask = IOT2040_UART1_MASK;
462 u8 mode, value;
463
464 if (is_rs485) {
465 if (rs485->flags & SER_RS485_RX_DURING_TX)
466 mode = IOT2040_UART_MODE_RS422;
467 else
468 mode = IOT2040_UART_MODE_RS485;
469
470 if (rs485->flags & SER_RS485_TERMINATE_BUS)
471 mode |= IOT2040_UART_TERMINATE_BUS;
472 } else {
473 mode = IOT2040_UART_MODE_RS232;
474 }
475
476 if (port->line == 3) {
477 mask <<= IOT2040_UART2_SHIFT;
478 mode <<= IOT2040_UART2_SHIFT;
479 }
480
481 value = readb(p + UART_EXAR_MPIOLVL_7_0);
482 value &= ~mask;
483 value |= mode;
484 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
485
486 return generic_rs485_config(port, rs485);
487 }
488
489 static const struct serial_rs485 iot2040_rs485_supported = {
490 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
491 SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
492 };
493
494 static const struct property_entry iot2040_gpio_properties[] = {
495 PROPERTY_ENTRY_U32("exar,first-pin", 10),
496 PROPERTY_ENTRY_U32("ngpios", 1),
497 { }
498 };
499
500 static const struct software_node iot2040_gpio_node = {
501 .properties = iot2040_gpio_properties,
502 };
503
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)504 static int iot2040_register_gpio(struct pci_dev *pcidev,
505 struct uart_8250_port *port)
506 {
507 u8 __iomem *p = port->port.membase;
508
509 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
510 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
511 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
512 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
513
514 port->port.private_data =
515 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
516
517 return 0;
518 }
519
520 static const struct exar8250_platform iot2040_platform = {
521 .rs485_config = iot2040_rs485_config,
522 .rs485_supported = &iot2040_rs485_supported,
523 .register_gpio = iot2040_register_gpio,
524 .unregister_gpio = xr17v35x_unregister_gpio,
525 };
526
527 /*
528 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
529 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
530 * board name after the device was found.
531 */
532 static const struct dmi_system_id exar_platforms[] = {
533 {
534 .matches = {
535 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
536 },
537 .driver_data = (void *)&iot2040_platform,
538 },
539 {}
540 };
541
exar_get_platform(void)542 static const struct exar8250_platform *exar_get_platform(void)
543 {
544 const struct dmi_system_id *dmi_match;
545
546 dmi_match = dmi_first_match(exar_platforms);
547 if (dmi_match)
548 return dmi_match->driver_data;
549
550 return &exar8250_default_platform;
551 }
552
553 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)554 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
555 struct uart_8250_port *port, int idx)
556 {
557 const struct exar8250_platform *platform = exar_get_platform();
558 unsigned int offset = idx * 0x400;
559 unsigned int baud = 7812500;
560 u8 __iomem *p;
561 int ret;
562
563 port->port.uartclk = baud * 16;
564 port->port.rs485_config = platform->rs485_config;
565 port->port.rs485_supported = platform->rs485_supported;
566
567 /*
568 * Setup the UART clock for the devices on expansion slot to
569 * half the clock speed of the main chip (which is 125MHz)
570 */
571 if (idx >= 8)
572 port->port.uartclk /= 2;
573
574 ret = default_setup(priv, pcidev, idx, offset, port);
575 if (ret)
576 return ret;
577
578 p = port->port.membase;
579
580 writeb(0x00, p + UART_EXAR_8XMODE);
581 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
582 writeb(128, p + UART_EXAR_TXTRG);
583 writeb(128, p + UART_EXAR_RXTRG);
584
585 if (idx == 0) {
586 /* Setup Multipurpose Input/Output pins. */
587 setup_gpio(pcidev, p);
588
589 ret = platform->register_gpio(pcidev, port);
590 }
591
592 return ret;
593 }
594
pci_xr17v35x_exit(struct pci_dev * pcidev)595 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
596 {
597 const struct exar8250_platform *platform = exar_get_platform();
598 struct exar8250 *priv = pci_get_drvdata(pcidev);
599 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
600
601 platform->unregister_gpio(port);
602 }
603
exar_misc_clear(struct exar8250 * priv)604 static inline void exar_misc_clear(struct exar8250 *priv)
605 {
606 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
607 readb(priv->virt + UART_EXAR_INT0);
608
609 /* Clear INT0 for Expansion Interface slave ports, too */
610 if (priv->board->num_ports > 8)
611 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
612 }
613
614 /*
615 * These Exar UARTs have an extra interrupt indicator that could fire for a
616 * few interrupts that are not presented/cleared through IIR. One of which is
617 * a wakeup interrupt when coming out of sleep. These interrupts are only
618 * cleared by reading global INT0 or INT1 registers as interrupts are
619 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
620 * channel's address space, but for the sake of bus efficiency we register a
621 * dedicated handler at the PCI device level to handle them.
622 */
exar_misc_handler(int irq,void * data)623 static irqreturn_t exar_misc_handler(int irq, void *data)
624 {
625 exar_misc_clear(data);
626
627 return IRQ_HANDLED;
628 }
629
630 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)631 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
632 {
633 unsigned int nr_ports, i, bar = 0, maxnr;
634 struct exar8250_board *board;
635 struct uart_8250_port uart;
636 struct exar8250 *priv;
637 int rc;
638
639 board = (struct exar8250_board *)ent->driver_data;
640 if (!board)
641 return -EINVAL;
642
643 rc = pcim_enable_device(pcidev);
644 if (rc)
645 return rc;
646
647 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
648
649 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
650 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
651 else if (board->num_ports)
652 nr_ports = board->num_ports;
653 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
654 nr_ports = pcidev->device & 0xff;
655 else
656 nr_ports = pcidev->device & 0x0f;
657
658 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
659 if (!priv)
660 return -ENOMEM;
661
662 priv->board = board;
663 priv->virt = pcim_iomap(pcidev, bar, 0);
664 if (!priv->virt)
665 return -ENOMEM;
666
667 pci_set_master(pcidev);
668
669 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
670 if (rc < 0)
671 return rc;
672
673 memset(&uart, 0, sizeof(uart));
674 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
675 uart.port.irq = pci_irq_vector(pcidev, 0);
676 uart.port.dev = &pcidev->dev;
677
678 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
679 IRQF_SHARED, "exar_uart", priv);
680 if (rc)
681 return rc;
682
683 /* Clear interrupts */
684 exar_misc_clear(priv);
685
686 for (i = 0; i < nr_ports && i < maxnr; i++) {
687 rc = board->setup(priv, pcidev, &uart, i);
688 if (rc) {
689 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
690 break;
691 }
692
693 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
694 uart.port.iobase, uart.port.irq, uart.port.iotype);
695
696 priv->line[i] = serial8250_register_8250_port(&uart);
697 if (priv->line[i] < 0) {
698 dev_err(&pcidev->dev,
699 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
700 uart.port.iobase, uart.port.irq,
701 uart.port.iotype, priv->line[i]);
702 break;
703 }
704 }
705 priv->nr = i;
706 pci_set_drvdata(pcidev, priv);
707 return 0;
708 }
709
exar_pci_remove(struct pci_dev * pcidev)710 static void exar_pci_remove(struct pci_dev *pcidev)
711 {
712 struct exar8250 *priv = pci_get_drvdata(pcidev);
713 unsigned int i;
714
715 for (i = 0; i < priv->nr; i++)
716 serial8250_unregister_port(priv->line[i]);
717
718 if (priv->board->exit)
719 priv->board->exit(pcidev);
720 }
721
exar_suspend(struct device * dev)722 static int __maybe_unused exar_suspend(struct device *dev)
723 {
724 struct pci_dev *pcidev = to_pci_dev(dev);
725 struct exar8250 *priv = pci_get_drvdata(pcidev);
726 unsigned int i;
727
728 for (i = 0; i < priv->nr; i++)
729 if (priv->line[i] >= 0)
730 serial8250_suspend_port(priv->line[i]);
731
732 /* Ensure that every init quirk is properly torn down */
733 if (priv->board->exit)
734 priv->board->exit(pcidev);
735
736 return 0;
737 }
738
exar_resume(struct device * dev)739 static int __maybe_unused exar_resume(struct device *dev)
740 {
741 struct exar8250 *priv = dev_get_drvdata(dev);
742 unsigned int i;
743
744 exar_misc_clear(priv);
745
746 for (i = 0; i < priv->nr; i++)
747 if (priv->line[i] >= 0)
748 serial8250_resume_port(priv->line[i]);
749
750 return 0;
751 }
752
753 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
754
755 static const struct exar8250_board pbn_fastcom335_2 = {
756 .num_ports = 2,
757 .setup = pci_fastcom335_setup,
758 };
759
760 static const struct exar8250_board pbn_fastcom335_4 = {
761 .num_ports = 4,
762 .setup = pci_fastcom335_setup,
763 };
764
765 static const struct exar8250_board pbn_fastcom335_8 = {
766 .num_ports = 8,
767 .setup = pci_fastcom335_setup,
768 };
769
770 static const struct exar8250_board pbn_connect = {
771 .setup = pci_connect_tech_setup,
772 };
773
774 static const struct exar8250_board pbn_exar_ibm_saturn = {
775 .num_ports = 1,
776 .setup = pci_xr17c154_setup,
777 };
778
779 static const struct exar8250_board pbn_exar_XR17C15x = {
780 .setup = pci_xr17c154_setup,
781 };
782
783 static const struct exar8250_board pbn_exar_XR17V35x = {
784 .setup = pci_xr17v35x_setup,
785 .exit = pci_xr17v35x_exit,
786 };
787
788 static const struct exar8250_board pbn_fastcom35x_2 = {
789 .num_ports = 2,
790 .setup = pci_xr17v35x_setup,
791 .exit = pci_xr17v35x_exit,
792 };
793
794 static const struct exar8250_board pbn_fastcom35x_4 = {
795 .num_ports = 4,
796 .setup = pci_xr17v35x_setup,
797 .exit = pci_xr17v35x_exit,
798 };
799
800 static const struct exar8250_board pbn_fastcom35x_8 = {
801 .num_ports = 8,
802 .setup = pci_xr17v35x_setup,
803 .exit = pci_xr17v35x_exit,
804 };
805
806 static const struct exar8250_board pbn_exar_XR17V4358 = {
807 .num_ports = 12,
808 .setup = pci_xr17v35x_setup,
809 .exit = pci_xr17v35x_exit,
810 };
811
812 static const struct exar8250_board pbn_exar_XR17V8358 = {
813 .num_ports = 16,
814 .setup = pci_xr17v35x_setup,
815 .exit = pci_xr17v35x_exit,
816 };
817
818 #define CONNECT_DEVICE(devid, sdevid, bd) { \
819 PCI_DEVICE_SUB( \
820 PCI_VENDOR_ID_EXAR, \
821 PCI_DEVICE_ID_EXAR_##devid, \
822 PCI_SUBVENDOR_ID_CONNECT_TECH, \
823 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
824 (kernel_ulong_t)&bd \
825 }
826
827 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
828
829 #define IBM_DEVICE(devid, sdevid, bd) { \
830 PCI_DEVICE_SUB( \
831 PCI_VENDOR_ID_EXAR, \
832 PCI_DEVICE_ID_EXAR_##devid, \
833 PCI_VENDOR_ID_IBM, \
834 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
835 (kernel_ulong_t)&bd \
836 }
837
838 #define USR_DEVICE(devid, sdevid, bd) { \
839 PCI_DEVICE_SUB( \
840 PCI_VENDOR_ID_USR, \
841 PCI_DEVICE_ID_EXAR_##devid, \
842 PCI_VENDOR_ID_EXAR, \
843 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
844 (kernel_ulong_t)&bd \
845 }
846
847 static const struct pci_device_id exar_pci_tbl[] = {
848 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
849 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
850 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
851 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
852 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
853 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
854 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
855
856 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
857 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
858 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
859 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
860 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
861 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
862 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
863 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
864 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
865 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
866 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
867 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
868
869 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
870
871 /* USRobotics USR298x-OEM PCI Modems */
872 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
873 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
874
875 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
876 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
877 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
878 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
879
880 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
881 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
882 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
883 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
884 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
885 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
886 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
887 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
888 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
889
890 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
891 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
892 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
893 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
894
895 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
896 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
897 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
898 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
899 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
900 { 0, }
901 };
902 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
903
904 static struct pci_driver exar_pci_driver = {
905 .name = "exar_serial",
906 .probe = exar_pci_probe,
907 .remove = exar_pci_remove,
908 .driver = {
909 .pm = &exar_pci_pm,
910 },
911 .id_table = exar_pci_tbl,
912 };
913 module_pci_driver(exar_pci_driver);
914
915 MODULE_LICENSE("GPL");
916 MODULE_DESCRIPTION("Exar Serial Driver");
917 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
918