1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/list.h>
24 #include <linux/usb.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/wireless.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <net/mac80211.h>
32 #include "rtl8xxxu.h"
33 #include "rtl8xxxu_regs.h"
34
35 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
36 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
37 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
38 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
39 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
40 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
41 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
42 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
43 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
44 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
45 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
46 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
47 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
48 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
49 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
50 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
51 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
52 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
53 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
54 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
55 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
56 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
57 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
58 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
59 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
60 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
61 {0x70b, 0x87},
62 {0xffff, 0xff},
63 };
64
65 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
66 {0x800, 0x80040000}, {0x804, 0x00000003},
67 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
68 {0x810, 0x10001331}, {0x814, 0x020c3d10},
69 {0x818, 0x02220385}, {0x81c, 0x00000000},
70 {0x820, 0x01000100}, {0x824, 0x00390204},
71 {0x828, 0x01000100}, {0x82c, 0x00390204},
72 {0x830, 0x32323232}, {0x834, 0x30303030},
73 {0x838, 0x30303030}, {0x83c, 0x30303030},
74 {0x840, 0x00010000}, {0x844, 0x00010000},
75 {0x848, 0x28282828}, {0x84c, 0x28282828},
76 {0x850, 0x00000000}, {0x854, 0x00000000},
77 {0x858, 0x009a009a}, {0x85c, 0x01000014},
78 {0x860, 0x66f60000}, {0x864, 0x061f0000},
79 {0x868, 0x30303030}, {0x86c, 0x30303030},
80 {0x870, 0x00000000}, {0x874, 0x55004200},
81 {0x878, 0x08080808}, {0x87c, 0x00000000},
82 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
83 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
84 {0x890, 0x00000800}, {0x894, 0xfffffffe},
85 {0x898, 0x40302010}, {0x900, 0x00000000},
86 {0x904, 0x00000023}, {0x908, 0x00000000},
87 {0x90c, 0x81121313}, {0x910, 0x806c0001},
88 {0x914, 0x00000001}, {0x918, 0x00000000},
89 {0x91c, 0x00010000}, {0x924, 0x00000001},
90 {0x928, 0x00000000}, {0x92c, 0x00000000},
91 {0x930, 0x00000000}, {0x934, 0x00000000},
92 {0x938, 0x00000000}, {0x93c, 0x00000000},
93 {0x940, 0x00000000}, {0x944, 0x00000000},
94 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
95 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
96 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
97 {0xa14, 0x1114d028}, {0xa18, 0x00881117},
98 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
99 {0xa24, 0x090e1317}, {0xa28, 0x00000204},
100 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
101 {0xa74, 0x00000007}, {0xa78, 0x00000900},
102 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
103 {0xb38, 0x00000000}, {0xc00, 0x48071d40},
104 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
105 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
106 {0xc14, 0x40000100}, {0xc18, 0x08800000},
107 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
108 {0xc24, 0x00000000}, {0xc28, 0x00000000},
109 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
110 {0xc34, 0x469652af}, {0xc38, 0x49795994},
111 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
112 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
113 {0xc4c, 0x007f037f},
114 #ifdef EXT_PA_8192EU
115 /* External PA or external LNA */
116 {0xc50, 0x00340220},
117 #else
118 {0xc50, 0x00340020},
119 #endif
120 {0xc54, 0x0080801f},
121 #ifdef EXT_PA_8192EU
122 /* External PA or external LNA */
123 {0xc58, 0x00000220},
124 #else
125 {0xc58, 0x00000020},
126 #endif
127 {0xc5c, 0x00248492}, {0xc60, 0x00000000},
128 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
129 {0xc6c, 0x00000036}, {0xc70, 0x00000600},
130 {0xc74, 0x02013169}, {0xc78, 0x0000001f},
131 {0xc7c, 0x00b91612},
132 #ifdef EXT_PA_8192EU
133 /* External PA or external LNA */
134 {0xc80, 0x2d4000b5},
135 #else
136 {0xc80, 0x40000100},
137 #endif
138 {0xc84, 0x21f60000},
139 #ifdef EXT_PA_8192EU
140 /* External PA or external LNA */
141 {0xc88, 0x2d4000b5},
142 #else
143 {0xc88, 0x40000100},
144 #endif
145 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
146 {0xc94, 0x00000000}, {0xc98, 0x00121820},
147 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
148 {0xca4, 0x000300a0}, {0xca8, 0x00000000},
149 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
150 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
151 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
152 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
153 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
154 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
155 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
156 {0xce4, 0x00040000}, {0xce8, 0x77644302},
157 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
158 {0xd04, 0x00020403}, {0xd08, 0x0000907f},
159 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
160 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
161 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
162 {0xd30, 0x00000000}, {0xd34, 0x80608000},
163 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
164 {0xd40, 0x00000000}, {0xd44, 0x00000000},
165 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
166 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
167 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
168 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
169 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
170 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
171 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
172 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
173 {0xe00, 0x30303030}, {0xe04, 0x30303030},
174 {0xe08, 0x03903030}, {0xe10, 0x30303030},
175 {0xe14, 0x30303030}, {0xe18, 0x30303030},
176 {0xe1c, 0x30303030}, {0xe28, 0x00000000},
177 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
178 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
179 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
180 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
181 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
182 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
183 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
184 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
185 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
186 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
187 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
188 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
189 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
190 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
191 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
192 {0xee8, 0x00000001}, {0xf14, 0x00000003},
193 {0xf4c, 0x00000000}, {0xf00, 0x00000300},
194 {0xffff, 0xffffffff},
195 };
196
197 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
198 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
199 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
200 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
201 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
202 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
203 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
204 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
205 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
206 {0xc78, 0xf0100001}, {0xc78, 0xef110001},
207 {0xc78, 0xee120001}, {0xc78, 0xed130001},
208 {0xc78, 0xec140001}, {0xc78, 0xeb150001},
209 {0xc78, 0xea160001}, {0xc78, 0xe9170001},
210 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
211 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
212 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
213 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
214 {0xc78, 0x04200001}, {0xc78, 0x03210001},
215 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
216 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
217 {0xc78, 0xa6260001}, {0xc78, 0x85270001},
218 {0xc78, 0x84280001}, {0xc78, 0x83290001},
219 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
220 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
221 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
222 {0xc78, 0x65300001}, {0xc78, 0x64310001},
223 {0xc78, 0x63320001}, {0xc78, 0x62330001},
224 {0xc78, 0x61340001}, {0xc78, 0x45350001},
225 {0xc78, 0x44360001}, {0xc78, 0x43370001},
226 {0xc78, 0x42380001}, {0xc78, 0x41390001},
227 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
228 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
229 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
230 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
231 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
232 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
233 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
234 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
235 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
236 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
237 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
238 {0xc78, 0xf0500001}, {0xc78, 0xef510001},
239 {0xc78, 0xee520001}, {0xc78, 0xed530001},
240 {0xc78, 0xec540001}, {0xc78, 0xeb550001},
241 {0xc78, 0xea560001}, {0xc78, 0xe9570001},
242 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
243 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
244 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
245 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
246 {0xc78, 0x8a600001}, {0xc78, 0x89610001},
247 {0xc78, 0x88620001}, {0xc78, 0x87630001},
248 {0xc78, 0x86640001}, {0xc78, 0x85650001},
249 {0xc78, 0x84660001}, {0xc78, 0x83670001},
250 {0xc78, 0x82680001}, {0xc78, 0x6b690001},
251 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
252 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
253 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
254 {0xc78, 0x64700001}, {0xc78, 0x63710001},
255 {0xc78, 0x62720001}, {0xc78, 0x61730001},
256 {0xc78, 0x49740001}, {0xc78, 0x48750001},
257 {0xc78, 0x47760001}, {0xc78, 0x46770001},
258 {0xc78, 0x45780001}, {0xc78, 0x44790001},
259 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
260 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
261 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
262 {0xc50, 0x00040022}, {0xc50, 0x00040020},
263 {0xffff, 0xffffffff}
264 };
265
266 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
267 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
268 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
269 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
270 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
271 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
272 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
273 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
274 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
275 {0xc78, 0xea100001}, {0xc78, 0xe9110001},
276 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
277 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
278 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
279 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
280 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
281 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
282 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
283 {0xc78, 0x84200001}, {0xc78, 0x83210001},
284 {0xc78, 0x82220001}, {0xc78, 0x6a230001},
285 {0xc78, 0x69240001}, {0xc78, 0x68250001},
286 {0xc78, 0x67260001}, {0xc78, 0x66270001},
287 {0xc78, 0x65280001}, {0xc78, 0x64290001},
288 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
289 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
290 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
291 {0xc78, 0x45300001}, {0xc78, 0x44310001},
292 {0xc78, 0x43320001}, {0xc78, 0x42330001},
293 {0xc78, 0x41340001}, {0xc78, 0x40350001},
294 {0xc78, 0x40360001}, {0xc78, 0x40370001},
295 {0xc78, 0x40380001}, {0xc78, 0x40390001},
296 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
297 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
298 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
299 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
300 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
301 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
302 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
303 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
304 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
305 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
306 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
307 {0xc78, 0xea500001}, {0xc78, 0xe9510001},
308 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
309 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
310 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
311 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
312 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
313 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
314 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
315 {0xc78, 0x84600001}, {0xc78, 0x83610001},
316 {0xc78, 0x82620001}, {0xc78, 0x6a630001},
317 {0xc78, 0x69640001}, {0xc78, 0x68650001},
318 {0xc78, 0x67660001}, {0xc78, 0x66670001},
319 {0xc78, 0x65680001}, {0xc78, 0x64690001},
320 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
321 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
322 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
323 {0xc78, 0x45700001}, {0xc78, 0x44710001},
324 {0xc78, 0x43720001}, {0xc78, 0x42730001},
325 {0xc78, 0x41740001}, {0xc78, 0x40750001},
326 {0xc78, 0x40760001}, {0xc78, 0x40770001},
327 {0xc78, 0x40780001}, {0xc78, 0x40790001},
328 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
329 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
330 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
331 {0xc50, 0x00040222}, {0xc50, 0x00040220},
332 {0xffff, 0xffffffff}
333 };
334
335 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
336 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
337 {0x00, 0x00030000}, {0x08, 0x00008400},
338 {0x18, 0x00000407}, {0x19, 0x00000012},
339 {0x1b, 0x00000064}, {0x1e, 0x00080009},
340 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
341 {0x3f, 0x00000000}, {0x42, 0x000060c0},
342 {0x57, 0x000d0000}, {0x58, 0x000be180},
343 {0x67, 0x00001552}, {0x83, 0x00000000},
344 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
345 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
346 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
347 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
348 {0xb9, 0x00080001}, {0xba, 0x00040001},
349 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
350 {0xc2, 0x00002400}, {0xc3, 0x00000009},
351 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
352 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
353 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
354 {0xca, 0x00080000}, {0xdf, 0x00000180},
355 {0xef, 0x000001a0}, {0x51, 0x00069545},
356 {0x52, 0x0007e45e}, {0x53, 0x00000071},
357 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
358 {0x35, 0x000001e2}, {0x35, 0x000002a8},
359 {0x36, 0x00001c24}, {0x36, 0x00009c24},
360 {0x36, 0x00011c24}, {0x36, 0x00019c24},
361 {0x18, 0x00000c07}, {0x5a, 0x00048000},
362 {0x19, 0x000739d0},
363 #ifdef EXT_PA_8192EU
364 /* External PA or external LNA */
365 {0x34, 0x0000a093}, {0x34, 0x0000908f},
366 {0x34, 0x0000808c}, {0x34, 0x0000704d},
367 {0x34, 0x0000604a}, {0x34, 0x00005047},
368 {0x34, 0x0000400a}, {0x34, 0x00003007},
369 {0x34, 0x00002004}, {0x34, 0x00001001},
370 {0x34, 0x00000000},
371 #else
372 /* Regular */
373 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
374 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
375 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
376 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
377 {0x34, 0x0000244f}, {0x34, 0x0000144c},
378 {0x34, 0x00000014},
379 #endif
380 {0x00, 0x00030159},
381 {0x84, 0x00068180},
382 {0x86, 0x0000014e},
383 {0x87, 0x00048e00},
384 {0x8e, 0x00065540},
385 {0x8f, 0x00088000},
386 {0xef, 0x000020a0},
387 #ifdef EXT_PA_8192EU
388 /* External PA or external LNA */
389 {0x3b, 0x000f07b0},
390 #else
391 {0x3b, 0x000f02b0},
392 #endif
393 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
394 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
395 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
396 {0x3b, 0x0008f780},
397 #ifdef EXT_PA_8192EU
398 /* External PA or external LNA */
399 {0x3b, 0x000787b0},
400 #else
401 {0x3b, 0x00078730},
402 #endif
403 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
404 {0x3b, 0x00040620}, {0x3b, 0x00037090},
405 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
406 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
407 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
408 {0xfe, 0x00000000}, {0xfe, 0x00000000},
409 {0xfe, 0x00000000}, {0xfe, 0x00000000},
410 {0x1e, 0x00000001}, {0x1f, 0x00080000},
411 {0x00, 0x00033e70},
412 {0xff, 0xffffffff}
413 };
414
415 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
416 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
417 {0x00, 0x00030000}, {0x08, 0x00008400},
418 {0x18, 0x00000407}, {0x19, 0x00000012},
419 {0x1b, 0x00000064}, {0x1e, 0x00080009},
420 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
421 {0x3f, 0x00000000}, {0x42, 0x000060c0},
422 {0x57, 0x000d0000}, {0x58, 0x000be180},
423 {0x67, 0x00001552}, {0x7f, 0x00000082},
424 {0x81, 0x0003f000}, {0x83, 0x00000000},
425 {0xdf, 0x00000180}, {0xef, 0x000001a0},
426 {0x51, 0x00069545}, {0x52, 0x0007e42e},
427 {0x53, 0x00000071}, {0x56, 0x00051ff3},
428 {0x35, 0x000000a8}, {0x35, 0x000001e0},
429 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
430 {0x36, 0x00009c24}, {0x36, 0x00011c24},
431 {0x36, 0x00019c24}, {0x18, 0x00000c07},
432 {0x5a, 0x00048000}, {0x19, 0x000739d0},
433 #ifdef EXT_PA_8192EU
434 /* External PA or external LNA */
435 {0x34, 0x0000a093}, {0x34, 0x0000908f},
436 {0x34, 0x0000808c}, {0x34, 0x0000704d},
437 {0x34, 0x0000604a}, {0x34, 0x00005047},
438 {0x34, 0x0000400a}, {0x34, 0x00003007},
439 {0x34, 0x00002004}, {0x34, 0x00001001},
440 {0x34, 0x00000000},
441 #else
442 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
443 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
444 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
445 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
446 {0x34, 0x0000244f}, {0x34, 0x0000144c},
447 {0x34, 0x00000014},
448 #endif
449 {0x00, 0x00030159}, {0x84, 0x00068180},
450 {0x86, 0x000000ce}, {0x87, 0x00048a00},
451 {0x8e, 0x00065540}, {0x8f, 0x00088000},
452 {0xef, 0x000020a0},
453 #ifdef EXT_PA_8192EU
454 /* External PA or external LNA */
455 {0x3b, 0x000f07b0},
456 #else
457 {0x3b, 0x000f02b0},
458 #endif
459
460 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
461 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
462 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
463 {0x3b, 0x0008f780},
464 #ifdef EXT_PA_8192EU
465 /* External PA or external LNA */
466 {0x3b, 0x000787b0},
467 #else
468 {0x3b, 0x00078730},
469 #endif
470 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
471 {0x3b, 0x00040620}, {0x3b, 0x00037090},
472 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
473 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
474 {0x00, 0x00010159}, {0xfe, 0x00000000},
475 {0xfe, 0x00000000}, {0xfe, 0x00000000},
476 {0xfe, 0x00000000}, {0x1e, 0x00000001},
477 {0x1f, 0x00080000}, {0x00, 0x00033e70},
478 {0xff, 0xffffffff}
479 };
480
481 static void
rtl8192e_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)482 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
483 {
484 u32 val32, ofdm, mcs;
485 u8 cck, ofdmbase, mcsbase;
486 int group, tx_idx;
487
488 tx_idx = 0;
489 group = rtl8xxxu_gen2_channel_to_group(channel);
490
491 cck = priv->cck_tx_power_index_A[group];
492
493 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
494 val32 &= 0xffff00ff;
495 val32 |= (cck << 8);
496 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
497
498 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
499 val32 &= 0xff;
500 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
501 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
502
503 ofdmbase = priv->ht40_1s_tx_power_index_A[group];
504 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
505 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
506
507 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
508 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
509
510 mcsbase = priv->ht40_1s_tx_power_index_A[group];
511 if (ht40)
512 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
513 else
514 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
515 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
516
517 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
518 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
519 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
520 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
521
522 if (priv->tx_paths > 1) {
523 cck = priv->cck_tx_power_index_B[group];
524
525 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
526 val32 &= 0xff;
527 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
528 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
529
530 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
531 val32 &= 0xffffff00;
532 val32 |= cck;
533 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
534
535 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
536 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
537 ofdm = ofdmbase | ofdmbase << 8 |
538 ofdmbase << 16 | ofdmbase << 24;
539
540 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
541 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
542
543 mcsbase = priv->ht40_1s_tx_power_index_B[group];
544 if (ht40)
545 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
546 else
547 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
548 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
549
550 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
551 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
552 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
553 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
554 }
555 }
556
rtl8192eu_log_next_device_info(struct rtl8xxxu_priv * priv,char * record_name,char * device_info,unsigned int * record_offset)557 static void rtl8192eu_log_next_device_info(struct rtl8xxxu_priv *priv,
558 char *record_name,
559 char *device_info,
560 unsigned int *record_offset)
561 {
562 char *record = device_info + *record_offset;
563
564 /* A record is [ total length | 0x03 | value ] */
565 unsigned char l = record[0];
566
567 /*
568 * The whole device info section seems to be 80 characters, make sure
569 * we don't read further.
570 */
571 if (*record_offset + l > 80) {
572 dev_warn(&priv->udev->dev,
573 "invalid record length %d while parsing \"%s\" at offset %u.\n",
574 l, record_name, *record_offset);
575 return;
576 }
577
578 if (l >= 2) {
579 char value[80];
580
581 memcpy(value, &record[2], l - 2);
582 value[l - 2] = '\0';
583 dev_info(&priv->udev->dev, "%s: %s\n", record_name, value);
584 *record_offset = *record_offset + l;
585 } else {
586 dev_info(&priv->udev->dev, "%s not available.\n", record_name);
587 }
588 }
589
rtl8192eu_parse_efuse(struct rtl8xxxu_priv * priv)590 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
591 {
592 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
593 unsigned int record_offset;
594 int i;
595
596 if (efuse->rtl_id != cpu_to_le16(0x8129))
597 return -EINVAL;
598
599 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
600
601 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
602 sizeof(efuse->tx_power_index_A.cck_base));
603 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
604 sizeof(efuse->tx_power_index_B.cck_base));
605
606 memcpy(priv->ht40_1s_tx_power_index_A,
607 efuse->tx_power_index_A.ht40_base,
608 sizeof(efuse->tx_power_index_A.ht40_base));
609 memcpy(priv->ht40_1s_tx_power_index_B,
610 efuse->tx_power_index_B.ht40_base,
611 sizeof(efuse->tx_power_index_B.ht40_base));
612
613 priv->ht20_tx_power_diff[0].a =
614 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
615 priv->ht20_tx_power_diff[0].b =
616 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
617
618 priv->ht40_tx_power_diff[0].a = 0;
619 priv->ht40_tx_power_diff[0].b = 0;
620
621 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
622 priv->ofdm_tx_power_diff[i].a =
623 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
624 priv->ofdm_tx_power_diff[i].b =
625 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
626
627 priv->ht20_tx_power_diff[i].a =
628 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
629 priv->ht20_tx_power_diff[i].b =
630 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
631
632 priv->ht40_tx_power_diff[i].a =
633 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
634 priv->ht40_tx_power_diff[i].b =
635 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
636 }
637
638 priv->has_xtalk = 1;
639 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
640
641 /*
642 * device_info section seems to be laid out as records
643 * [ total length | 0x03 | value ] so:
644 * - vendor length + 2
645 * - 0x03
646 * - vendor string (not null terminated)
647 * - product length + 2
648 * - 0x03
649 * - product string (not null terminated)
650 * Then there is one or 2 0x00 on all the 4 devices I own or found
651 * dumped online.
652 * As previous version of the code handled an optional serial
653 * string, I now assume there may be a third record if the
654 * length is not 0.
655 */
656 record_offset = 0;
657 rtl8192eu_log_next_device_info(priv, "Vendor", efuse->device_info, &record_offset);
658 rtl8192eu_log_next_device_info(priv, "Product", efuse->device_info, &record_offset);
659 rtl8192eu_log_next_device_info(priv, "Serial", efuse->device_info, &record_offset);
660
661 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
662 unsigned char *raw = priv->efuse_wifi.raw;
663
664 dev_info(&priv->udev->dev,
665 "%s: dumping efuse (0x%02zx bytes):\n",
666 __func__, sizeof(struct rtl8192eu_efuse));
667 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8)
668 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]);
669 }
670 return 0;
671 }
672
rtl8192eu_load_firmware(struct rtl8xxxu_priv * priv)673 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
674 {
675 char *fw_name;
676 int ret;
677
678 fw_name = "rtlwifi/rtl8192eu_nic.bin";
679
680 ret = rtl8xxxu_load_firmware(priv, fw_name);
681
682 return ret;
683 }
684
rtl8192eu_init_phy_bb(struct rtl8xxxu_priv * priv)685 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
686 {
687 u8 val8;
688 u16 val16;
689
690 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
691 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
692 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
693
694 /* 6. 0x1f[7:0] = 0x07 */
695 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
696 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
697
698 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
699 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
700 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
701 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
702 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
703 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
704 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
705
706 if (priv->hi_pa)
707 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
708 else
709 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
710 }
711
rtl8192eu_init_phy_rf(struct rtl8xxxu_priv * priv)712 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
713 {
714 int ret;
715
716 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
717 if (ret)
718 goto exit;
719
720 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
721
722 exit:
723 return ret;
724 }
725
rtl8192eu_iqk_path_a(struct rtl8xxxu_priv * priv)726 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
727 {
728 u32 reg_eac, reg_e94, reg_e9c;
729 int result = 0;
730
731 /*
732 * TX IQK
733 * PA/PAD controlled by 0x0
734 */
735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
736 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
737 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
738
739 /* Path A IQK setting */
740 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
741 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
742 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
743 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
744
745 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
746 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
747
748 /* LO calibration setting */
749 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
750
751 /* One shot, path A LOK & IQK */
752 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
753 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
754
755 mdelay(10);
756
757 /* Check failed */
758 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
759 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
760 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
761
762 if (!(reg_eac & BIT(28)) &&
763 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
764 ((reg_e9c & 0x03ff0000) != 0x00420000))
765 result |= 0x01;
766
767 return result;
768 }
769
rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv * priv)770 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
771 {
772 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
773 int result = 0;
774
775 /* Leave IQK mode */
776 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
777
778 /* Enable path A PA in TX IQK mode */
779 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
780 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
781 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
782 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
783
784 /* PA/PAD control by 0x56, and set = 0x0 */
785 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
786 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
787
788 /* Enter IQK mode */
789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
790
791 /* TX IQK setting */
792 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
793 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
794
795 /* path-A IQK setting */
796 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
797 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
798 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
799 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
800
801 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
802 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
803
804 /* LO calibration setting */
805 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
806
807 /* One shot, path A LOK & IQK */
808 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
809 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
810
811 mdelay(10);
812
813 /* Check failed */
814 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
815 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
816 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
817
818 if (!(reg_eac & BIT(28)) &&
819 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
820 ((reg_e9c & 0x03ff0000) != 0x00420000)) {
821 result |= 0x01;
822 } else {
823 /* PA/PAD controlled by 0x0 */
824 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
826 goto out;
827 }
828
829 val32 = 0x80007c00 |
830 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
831 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
832
833 /* Modify RX IQK mode table */
834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
835
836 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
837 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
838 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
839 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
840
841 /* PA/PAD control by 0x56, and set = 0x0 */
842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
843 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
844
845 /* Enter IQK mode */
846 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
847
848 /* IQK setting */
849 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
850
851 /* Path A IQK setting */
852 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
853 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
854 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
855 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
856
857 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
858 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
859
860 /* LO calibration setting */
861 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
862
863 /* One shot, path A LOK & IQK */
864 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
865 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
866
867 mdelay(10);
868
869 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
870 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
871
872 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
873 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
874
875 if (!(reg_eac & BIT(27)) &&
876 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
877 ((reg_eac & 0x03ff0000) != 0x00360000))
878 result |= 0x02;
879 else
880 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
881 __func__);
882
883 out:
884 return result;
885 }
886
rtl8192eu_iqk_path_b(struct rtl8xxxu_priv * priv)887 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
888 {
889 u32 reg_eac, reg_eb4, reg_ebc;
890 int result = 0;
891
892 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
893 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
894 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
895
896 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
897 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
898
899 /* Path B IQK setting */
900 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
901 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
902 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
903 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
904
905 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
906 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
907
908 /* LO calibration setting */
909 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
910
911 /* One shot, path A LOK & IQK */
912 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
913 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
914
915 mdelay(1);
916
917 /* Check failed */
918 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
919 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
920 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
921
922 if (!(reg_eac & BIT(31)) &&
923 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
924 ((reg_ebc & 0x03ff0000) != 0x00420000))
925 result |= 0x01;
926 else
927 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
928 __func__);
929
930 return result;
931 }
932
rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv * priv)933 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
934 {
935 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
936 int result = 0;
937
938 /* Leave IQK mode */
939 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
940
941 /* Enable path A PA in TX IQK mode */
942 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
943 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
944 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
945 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
946
947 /* PA/PAD control by 0x56, and set = 0x0 */
948 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
949 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
950
951 /* Enter IQK mode */
952 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
953
954 /* TX IQK setting */
955 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
956 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
957
958 /* path-A IQK setting */
959 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
960 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
961 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
962 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
963
964 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
965 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
966
967 /* LO calibration setting */
968 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
969
970 /* One shot, path A LOK & IQK */
971 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
972 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
973
974 mdelay(10);
975
976 /* Check failed */
977 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
978 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
979 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
980
981 if (!(reg_eac & BIT(31)) &&
982 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
983 ((reg_ebc & 0x03ff0000) != 0x00420000)) {
984 result |= 0x01;
985 } else {
986 /*
987 * PA/PAD controlled by 0x0
988 * Vendor driver restores RF_A here which I believe is a bug
989 */
990 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
991 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
992 goto out;
993 }
994
995 val32 = 0x80007c00 |
996 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
997 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
998
999 /* Modify RX IQK mode table */
1000 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1001
1002 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
1003 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
1004 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
1005 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
1006
1007 /* PA/PAD control by 0x56, and set = 0x0 */
1008 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
1009 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
1010
1011 /* Enter IQK mode */
1012 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1013
1014 /* IQK setting */
1015 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1016
1017 /* Path A IQK setting */
1018 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
1019 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1020 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
1021 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
1022
1023 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
1024 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
1025
1026 /* LO calibration setting */
1027 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
1028
1029 /* One shot, path A LOK & IQK */
1030 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
1031 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1032
1033 mdelay(10);
1034
1035 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1036 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
1037 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
1038
1039 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1040 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
1041
1042 if (!(reg_eac & BIT(30)) &&
1043 ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
1044 ((reg_ecc & 0x03ff0000) != 0x00360000))
1045 result |= 0x02;
1046 else
1047 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
1048 __func__);
1049
1050 out:
1051 return result;
1052 }
1053
rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)1054 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1055 int result[][8], int t)
1056 {
1057 struct device *dev = &priv->udev->dev;
1058 u32 i, val32;
1059 int path_a_ok, path_b_ok;
1060 int retry = 2;
1061 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1062 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1063 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1064 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1065 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1066 REG_TX_TO_TX, REG_RX_CCK,
1067 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1068 REG_RX_TO_RX, REG_STANDBY,
1069 REG_SLEEP, REG_PMPD_ANAEN
1070 };
1071 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1072 REG_TXPAUSE, REG_BEACON_CTRL,
1073 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1074 };
1075 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1076 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1077 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1078 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1079 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1080 };
1081 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
1082 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
1083
1084 /*
1085 * Note: IQ calibration must be performed after loading
1086 * PHY_REG.txt , and radio_a, radio_b.txt
1087 */
1088
1089 if (t == 0) {
1090 /* Save ADDA parameters, turn Path A ADDA on */
1091 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1092 RTL8XXXU_ADDA_REGS);
1093 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1094 rtl8xxxu_save_regs(priv, iqk_bb_regs,
1095 priv->bb_backup, RTL8XXXU_BB_REGS);
1096 }
1097
1098 rtl8xxxu_path_adda_on(priv, adda_regs, true);
1099
1100 /* MAC settings */
1101 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
1102
1103 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1104 val32 |= 0x0f000000;
1105 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1106
1107 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
1108 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1109 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
1110
1111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
1112 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
1113 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
1114
1115 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
1116 val32 |= BIT(10);
1117 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
1118 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
1119 val32 |= BIT(10);
1120 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
1121
1122 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1123 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1124 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1125
1126 for (i = 0; i < retry; i++) {
1127 path_a_ok = rtl8192eu_iqk_path_a(priv);
1128 if (path_a_ok == 0x01) {
1129 val32 = rtl8xxxu_read32(priv,
1130 REG_TX_POWER_BEFORE_IQK_A);
1131 result[t][0] = (val32 >> 16) & 0x3ff;
1132 val32 = rtl8xxxu_read32(priv,
1133 REG_TX_POWER_AFTER_IQK_A);
1134 result[t][1] = (val32 >> 16) & 0x3ff;
1135
1136 break;
1137 }
1138 }
1139
1140 if (!path_a_ok)
1141 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1142
1143 for (i = 0; i < retry; i++) {
1144 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
1145 if (path_a_ok == 0x03) {
1146 val32 = rtl8xxxu_read32(priv,
1147 REG_RX_POWER_BEFORE_IQK_A_2);
1148 result[t][2] = (val32 >> 16) & 0x3ff;
1149 val32 = rtl8xxxu_read32(priv,
1150 REG_RX_POWER_AFTER_IQK_A_2);
1151 result[t][3] = (val32 >> 16) & 0x3ff;
1152
1153 break;
1154 }
1155 }
1156
1157 if (!path_a_ok)
1158 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1159
1160 if (priv->rf_paths > 1) {
1161 /* Path A into standby */
1162 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1163 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1164 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1165
1166 /* Turn Path B ADDA on */
1167 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1168
1169 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1170 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1171 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1172
1173 for (i = 0; i < retry; i++) {
1174 path_b_ok = rtl8192eu_iqk_path_b(priv);
1175 if (path_b_ok == 0x01) {
1176 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1177 result[t][4] = (val32 >> 16) & 0x3ff;
1178 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1179 result[t][5] = (val32 >> 16) & 0x3ff;
1180 break;
1181 }
1182 }
1183
1184 if (!path_b_ok)
1185 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1186
1187 for (i = 0; i < retry; i++) {
1188 path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
1189 if (path_b_ok == 0x03) {
1190 val32 = rtl8xxxu_read32(priv,
1191 REG_RX_POWER_BEFORE_IQK_B_2);
1192 result[t][6] = (val32 >> 16) & 0x3ff;
1193 val32 = rtl8xxxu_read32(priv,
1194 REG_RX_POWER_AFTER_IQK_B_2);
1195 result[t][7] = (val32 >> 16) & 0x3ff;
1196 break;
1197 }
1198 }
1199
1200 if (!path_b_ok)
1201 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1202 }
1203
1204 /* Back to BB mode, load original value */
1205 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1206
1207 if (t) {
1208 /* Reload ADDA power saving parameters */
1209 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1210 RTL8XXXU_ADDA_REGS);
1211
1212 /* Reload MAC parameters */
1213 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1214
1215 /* Reload BB parameters */
1216 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1217 priv->bb_backup, RTL8XXXU_BB_REGS);
1218
1219 /* Restore RX initial gain */
1220 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1221 val32 &= 0xffffff00;
1222 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1223 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1224
1225 if (priv->rf_paths > 1) {
1226 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1227 val32 &= 0xffffff00;
1228 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1229 val32 | 0x50);
1230 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1231 val32 | xb_agc);
1232 }
1233
1234 /* Load 0xe30 IQC default value */
1235 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1236 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1237 }
1238 }
1239
rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv * priv)1240 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1241 {
1242 struct device *dev = &priv->udev->dev;
1243 int result[4][8]; /* last is final result */
1244 int i, candidate;
1245 bool path_a_ok, path_b_ok;
1246 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1247 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1248 bool simu;
1249
1250 memset(result, 0, sizeof(result));
1251 candidate = -1;
1252
1253 path_a_ok = false;
1254 path_b_ok = false;
1255
1256 for (i = 0; i < 3; i++) {
1257 rtl8192eu_phy_iqcalibrate(priv, result, i);
1258
1259 if (i == 1) {
1260 simu = rtl8xxxu_gen2_simularity_compare(priv,
1261 result, 0, 1);
1262 if (simu) {
1263 candidate = 0;
1264 break;
1265 }
1266 }
1267
1268 if (i == 2) {
1269 simu = rtl8xxxu_gen2_simularity_compare(priv,
1270 result, 0, 2);
1271 if (simu) {
1272 candidate = 0;
1273 break;
1274 }
1275
1276 simu = rtl8xxxu_gen2_simularity_compare(priv,
1277 result, 1, 2);
1278 if (simu)
1279 candidate = 1;
1280 else
1281 candidate = 3;
1282 }
1283 }
1284
1285 for (i = 0; i < 4; i++) {
1286 reg_e94 = result[i][0];
1287 reg_e9c = result[i][1];
1288 reg_ea4 = result[i][2];
1289 reg_eb4 = result[i][4];
1290 reg_ebc = result[i][5];
1291 reg_ec4 = result[i][6];
1292 }
1293
1294 if (candidate >= 0) {
1295 reg_e94 = result[candidate][0];
1296 priv->rege94 = reg_e94;
1297 reg_e9c = result[candidate][1];
1298 priv->rege9c = reg_e9c;
1299 reg_ea4 = result[candidate][2];
1300 reg_eac = result[candidate][3];
1301 reg_eb4 = result[candidate][4];
1302 priv->regeb4 = reg_eb4;
1303 reg_ebc = result[candidate][5];
1304 priv->regebc = reg_ebc;
1305 reg_ec4 = result[candidate][6];
1306 reg_ecc = result[candidate][7];
1307 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1308 dev_dbg(dev,
1309 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1310 __func__, reg_e94, reg_e9c,
1311 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1312 path_a_ok = true;
1313 path_b_ok = true;
1314 } else {
1315 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1316 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1317 }
1318
1319 if (reg_e94 && candidate >= 0)
1320 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1321 candidate, (reg_ea4 == 0));
1322
1323 if (priv->rf_paths > 1)
1324 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1325 candidate, (reg_ec4 == 0));
1326
1327 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1328 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1329 }
1330
1331 /*
1332 * This is needed for 8723bu as well, presumable
1333 */
rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv * priv)1334 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
1335 {
1336 u8 val8;
1337 u32 val32;
1338
1339 /*
1340 * 40Mhz crystal source, MAC 0x28[2]=0
1341 */
1342 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1343 val8 &= 0xfb;
1344 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1345
1346 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1347 val32 &= 0xfffffc7f;
1348 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1349
1350 /*
1351 * 92e AFE parameter
1352 * AFE PLL KVCO selection, MAC 0x28[6]=1
1353 */
1354 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1355 val8 &= 0xbf;
1356 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1357
1358 /*
1359 * AFE PLL KVCO selection, MAC 0x78[21]=0
1360 */
1361 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1362 val32 &= 0xffdfffff;
1363 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1364 }
1365
rtl8192e_disabled_to_emu(struct rtl8xxxu_priv * priv)1366 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
1367 {
1368 u8 val8;
1369
1370 /* Clear suspend enable and power down enable*/
1371 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1372 val8 &= ~(BIT(3) | BIT(4));
1373 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1374 }
1375
rtl8192e_emu_to_active(struct rtl8xxxu_priv * priv)1376 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
1377 {
1378 u8 val8;
1379 u32 val32;
1380 int count, ret = 0;
1381
1382 /* disable HWPDN 0x04[15]=0*/
1383 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1384 val8 &= ~BIT(7);
1385 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1386
1387 /* disable SW LPS 0x04[10]= 0 */
1388 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1389 val8 &= ~BIT(2);
1390 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1391
1392 /* disable WL suspend*/
1393 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1394 val8 &= ~(BIT(3) | BIT(4));
1395 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1396
1397 /* wait till 0x04[17] = 1 power ready*/
1398 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1399 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1400 if (val32 & BIT(17))
1401 break;
1402
1403 udelay(10);
1404 }
1405
1406 if (!count) {
1407 ret = -EBUSY;
1408 goto exit;
1409 }
1410
1411 /* We should be able to optimize the following three entries into one */
1412
1413 /* release WLON reset 0x04[16]= 1*/
1414 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1415 val8 |= BIT(0);
1416 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1417
1418 /* set, then poll until 0 */
1419 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1420 val32 |= APS_FSMCO_MAC_ENABLE;
1421 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1422
1423 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1424 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1425 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1426 ret = 0;
1427 break;
1428 }
1429 udelay(10);
1430 }
1431
1432 if (!count) {
1433 ret = -EBUSY;
1434 goto exit;
1435 }
1436
1437 exit:
1438 return ret;
1439 }
1440
rtl8192eu_active_to_lps(struct rtl8xxxu_priv * priv)1441 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
1442 {
1443 struct device *dev = &priv->udev->dev;
1444 u8 val8;
1445 u16 val16;
1446 u32 val32;
1447 int retry, retval;
1448
1449 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1450
1451 retry = 100;
1452 retval = -EBUSY;
1453 /*
1454 * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
1455 */
1456 do {
1457 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1458 if (!val32) {
1459 retval = 0;
1460 break;
1461 }
1462 } while (retry--);
1463
1464 if (!retry) {
1465 dev_warn(dev, "Failed to flush TX queue\n");
1466 retval = -EBUSY;
1467 goto out;
1468 }
1469
1470 /* Disable CCK and OFDM, clock gated */
1471 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1472 val8 &= ~SYS_FUNC_BBRSTB;
1473 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1474
1475 udelay(2);
1476
1477 /* Reset whole BB */
1478 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1479 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1480 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1481
1482 /* Reset MAC TRX */
1483 val16 = rtl8xxxu_read16(priv, REG_CR);
1484 val16 &= 0xff00;
1485 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
1486 rtl8xxxu_write16(priv, REG_CR, val16);
1487
1488 val16 = rtl8xxxu_read16(priv, REG_CR);
1489 val16 &= ~CR_SECURITY_ENABLE;
1490 rtl8xxxu_write16(priv, REG_CR, val16);
1491
1492 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1493 val8 |= DUAL_TSF_TX_OK;
1494 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1495
1496 out:
1497 return retval;
1498 }
1499
rtl8192eu_active_to_emu(struct rtl8xxxu_priv * priv)1500 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
1501 {
1502 u8 val8;
1503 int count, ret = 0;
1504
1505 /* Turn off RF */
1506 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1507 val8 &= ~RF_ENABLE;
1508 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1509
1510 /* Switch DPDT_SEL_P output from register 0x65[2] */
1511 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1512 val8 &= ~LEDCFG2_DPDT_SELECT;
1513 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1514
1515 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1516 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1517 val8 |= BIT(1);
1518 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1519
1520 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1521 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1522 if ((val8 & BIT(1)) == 0)
1523 break;
1524 udelay(10);
1525 }
1526
1527 if (!count) {
1528 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1529 __func__);
1530 ret = -EBUSY;
1531 goto exit;
1532 }
1533
1534 exit:
1535 return ret;
1536 }
1537
rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv * priv)1538 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1539 {
1540 u8 val8;
1541
1542 /* 0x04[12:11] = 01 enable WL suspend */
1543 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1544 val8 &= ~(BIT(3) | BIT(4));
1545 val8 |= BIT(3);
1546 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1547
1548 return 0;
1549 }
1550
rtl8192eu_power_on(struct rtl8xxxu_priv * priv)1551 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
1552 {
1553 u16 val16;
1554 u32 val32;
1555 int ret;
1556
1557 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1558 if (val32 & SYS_CFG_SPS_LDO_SEL) {
1559 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
1560 } else {
1561 /*
1562 * Raise 1.2V voltage
1563 */
1564 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
1565 val32 &= 0xff0fffff;
1566 val32 |= 0x00500000;
1567 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
1568 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
1569 }
1570
1571 /*
1572 * Adjust AFE before enabling PLL
1573 */
1574 rtl8192e_crystal_afe_adjust(priv);
1575 rtl8192e_disabled_to_emu(priv);
1576
1577 ret = rtl8192e_emu_to_active(priv);
1578 if (ret)
1579 goto exit;
1580
1581 rtl8xxxu_write16(priv, REG_CR, 0x0000);
1582
1583 /*
1584 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1585 * Set CR bit10 to enable 32k calibration.
1586 */
1587 val16 = rtl8xxxu_read16(priv, REG_CR);
1588 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1589 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1590 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1591 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1592 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1593 rtl8xxxu_write16(priv, REG_CR, val16);
1594
1595 exit:
1596 return ret;
1597 }
1598
rtl8192eu_power_off(struct rtl8xxxu_priv * priv)1599 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
1600 {
1601 u8 val8;
1602 u16 val16;
1603
1604 rtl8xxxu_flush_fifo(priv);
1605
1606 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1607 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1608 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1609
1610 /* Turn off RF */
1611 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
1612
1613 rtl8192eu_active_to_lps(priv);
1614
1615 /* Reset Firmware if running in RAM */
1616 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1617 rtl8xxxu_firmware_self_reset(priv);
1618
1619 /* Reset MCU */
1620 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1621 val16 &= ~SYS_FUNC_CPU_ENABLE;
1622 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1623
1624 /* Reset MCU ready status */
1625 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1626
1627 rtl8xxxu_reset_8051(priv);
1628
1629 rtl8192eu_active_to_emu(priv);
1630 rtl8192eu_emu_to_disabled(priv);
1631 }
1632
rtl8192e_enable_rf(struct rtl8xxxu_priv * priv)1633 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
1634 {
1635 u32 val32;
1636 u8 val8;
1637
1638 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1639 val32 |= (BIT(22) | BIT(23));
1640 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1641
1642 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1643 val8 |= BIT(5);
1644 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1645
1646 /*
1647 * WLAN action by PTA
1648 */
1649 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1650
1651 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1652 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1653 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1654
1655 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1656 val32 |= (BIT(0) | BIT(1));
1657 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1658
1659 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1660
1661 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1662 val32 &= ~BIT(24);
1663 val32 |= BIT(23);
1664 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1665
1666 /*
1667 * Fix external switch Main->S1, Aux->S0
1668 */
1669 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1670 val8 &= ~BIT(0);
1671 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1672
1673 /*
1674 * Fix transmission failure of rtl8192e.
1675 */
1676 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1677 }
1678
1679 struct rtl8xxxu_fileops rtl8192eu_fops = {
1680 .parse_efuse = rtl8192eu_parse_efuse,
1681 .load_firmware = rtl8192eu_load_firmware,
1682 .power_on = rtl8192eu_power_on,
1683 .power_off = rtl8192eu_power_off,
1684 .reset_8051 = rtl8xxxu_reset_8051,
1685 .llt_init = rtl8xxxu_auto_llt_table,
1686 .init_phy_bb = rtl8192eu_init_phy_bb,
1687 .init_phy_rf = rtl8192eu_init_phy_rf,
1688 .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
1689 .config_channel = rtl8xxxu_gen2_config_channel,
1690 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1691 .enable_rf = rtl8192e_enable_rf,
1692 .disable_rf = rtl8xxxu_gen2_disable_rf,
1693 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1694 .set_tx_power = rtl8192e_set_tx_power,
1695 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1696 .report_connect = rtl8xxxu_gen2_report_connect,
1697 .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1698 .writeN_block_size = 128,
1699 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1700 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1701 .has_s0s1 = 0,
1702 .gen2_thermal_meter = 1,
1703 .needs_full_init = 1,
1704 .adda_1t_init = 0x0fc01616,
1705 .adda_1t_path_on = 0x0fc01616,
1706 .adda_2t_path_on_a = 0x0fc01616,
1707 .adda_2t_path_on_b = 0x0fc01616,
1708 .trxff_boundary = 0x3cff,
1709 .mactable = rtl8192e_mac_init_table,
1710 .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
1711 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
1712 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
1713 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
1714 };
1715