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1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/irq.h>
12 #include <linux/pci.h>
13 #include <linux/sysfs.h>
14 
15 #include "cgx.h"
16 #include "rvu.h"
17 #include "rvu_reg.h"
18 #include "ptp.h"
19 
20 #include "rvu_trace.h"
21 
22 #define DRV_NAME	"rvu_af"
23 #define DRV_STRING      "Marvell OcteonTX2 RVU Admin Function Driver"
24 
25 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
26 
27 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
28 				struct rvu_block *block, int lf);
29 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
30 				  struct rvu_block *block, int lf);
31 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
32 
33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
34 			 int type, int num,
35 			 void (mbox_handler)(struct work_struct *),
36 			 void (mbox_up_handler)(struct work_struct *));
37 enum {
38 	TYPE_AFVF,
39 	TYPE_AFPF,
40 };
41 
42 /* Supported devices */
43 static const struct pci_device_id rvu_id_table[] = {
44 	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
45 	{ 0, }  /* end of table */
46 };
47 
48 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
49 MODULE_DESCRIPTION(DRV_STRING);
50 MODULE_LICENSE("GPL v2");
51 MODULE_DEVICE_TABLE(pci, rvu_id_table);
52 
53 static char *mkex_profile; /* MKEX profile name */
54 module_param(mkex_profile, charp, 0000);
55 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
56 
57 static char *kpu_profile; /* KPU profile name */
58 module_param(kpu_profile, charp, 0000);
59 MODULE_PARM_DESC(kpu_profile, "KPU profile name string");
60 
rvu_setup_hw_capabilities(struct rvu * rvu)61 static void rvu_setup_hw_capabilities(struct rvu *rvu)
62 {
63 	struct rvu_hwinfo *hw = rvu->hw;
64 
65 	hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
66 	hw->cap.nix_fixed_txschq_mapping = false;
67 	hw->cap.nix_shaping = true;
68 	hw->cap.nix_tx_link_bp = true;
69 	hw->cap.nix_rx_multicast = true;
70 	hw->cap.nix_shaper_toggle_wait = false;
71 	hw->rvu = rvu;
72 
73 	if (is_rvu_pre_96xx_C0(rvu)) {
74 		hw->cap.nix_fixed_txschq_mapping = true;
75 		hw->cap.nix_txsch_per_cgx_lmac = 4;
76 		hw->cap.nix_txsch_per_lbk_lmac = 132;
77 		hw->cap.nix_txsch_per_sdp_lmac = 76;
78 		hw->cap.nix_shaping = false;
79 		hw->cap.nix_tx_link_bp = false;
80 		if (is_rvu_96xx_A0(rvu) || is_rvu_95xx_A0(rvu))
81 			hw->cap.nix_rx_multicast = false;
82 	}
83 	if (!is_rvu_pre_96xx_C0(rvu))
84 		hw->cap.nix_shaper_toggle_wait = true;
85 
86 	if (!is_rvu_otx2(rvu))
87 		hw->cap.per_pf_mbox_regs = true;
88 }
89 
90 /* Poll a RVU block's register 'offset', for a 'zero'
91  * or 'nonzero' at bits specified by 'mask'
92  */
rvu_poll_reg(struct rvu * rvu,u64 block,u64 offset,u64 mask,bool zero)93 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
94 {
95 	unsigned long timeout = jiffies + usecs_to_jiffies(20000);
96 	bool twice = false;
97 	void __iomem *reg;
98 	u64 reg_val;
99 
100 	reg = rvu->afreg_base + ((block << 28) | offset);
101 again:
102 	reg_val = readq(reg);
103 	if (zero && !(reg_val & mask))
104 		return 0;
105 	if (!zero && (reg_val & mask))
106 		return 0;
107 	if (time_before(jiffies, timeout)) {
108 		usleep_range(1, 5);
109 		goto again;
110 	}
111 	/* In scenarios where CPU is scheduled out before checking
112 	 * 'time_before' (above) and gets scheduled in such that
113 	 * jiffies are beyond timeout value, then check again if HW is
114 	 * done with the operation in the meantime.
115 	 */
116 	if (!twice) {
117 		twice = true;
118 		goto again;
119 	}
120 	return -EBUSY;
121 }
122 
rvu_alloc_rsrc(struct rsrc_bmap * rsrc)123 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
124 {
125 	int id;
126 
127 	if (!rsrc->bmap)
128 		return -EINVAL;
129 
130 	id = find_first_zero_bit(rsrc->bmap, rsrc->max);
131 	if (id >= rsrc->max)
132 		return -ENOSPC;
133 
134 	__set_bit(id, rsrc->bmap);
135 
136 	return id;
137 }
138 
rvu_alloc_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc)139 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
140 {
141 	int start;
142 
143 	if (!rsrc->bmap)
144 		return -EINVAL;
145 
146 	start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
147 	if (start >= rsrc->max)
148 		return -ENOSPC;
149 
150 	bitmap_set(rsrc->bmap, start, nrsrc);
151 	return start;
152 }
153 
rvu_free_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc,int start)154 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
155 {
156 	if (!rsrc->bmap)
157 		return;
158 	if (start >= rsrc->max)
159 		return;
160 
161 	bitmap_clear(rsrc->bmap, start, nrsrc);
162 }
163 
rvu_rsrc_check_contig(struct rsrc_bmap * rsrc,int nrsrc)164 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
165 {
166 	int start;
167 
168 	if (!rsrc->bmap)
169 		return false;
170 
171 	start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
172 	if (start >= rsrc->max)
173 		return false;
174 
175 	return true;
176 }
177 
rvu_free_rsrc(struct rsrc_bmap * rsrc,int id)178 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
179 {
180 	if (!rsrc->bmap)
181 		return;
182 
183 	__clear_bit(id, rsrc->bmap);
184 }
185 
rvu_rsrc_free_count(struct rsrc_bmap * rsrc)186 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
187 {
188 	int used;
189 
190 	if (!rsrc->bmap)
191 		return 0;
192 
193 	used = bitmap_weight(rsrc->bmap, rsrc->max);
194 	return (rsrc->max - used);
195 }
196 
is_rsrc_free(struct rsrc_bmap * rsrc,int id)197 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id)
198 {
199 	if (!rsrc->bmap)
200 		return false;
201 
202 	return !test_bit(id, rsrc->bmap);
203 }
204 
rvu_alloc_bitmap(struct rsrc_bmap * rsrc)205 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
206 {
207 	rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
208 			     sizeof(long), GFP_KERNEL);
209 	if (!rsrc->bmap)
210 		return -ENOMEM;
211 	return 0;
212 }
213 
rvu_free_bitmap(struct rsrc_bmap * rsrc)214 void rvu_free_bitmap(struct rsrc_bmap *rsrc)
215 {
216 	kfree(rsrc->bmap);
217 }
218 
219 /* Get block LF's HW index from a PF_FUNC's block slot number */
rvu_get_lf(struct rvu * rvu,struct rvu_block * block,u16 pcifunc,u16 slot)220 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
221 {
222 	u16 match = 0;
223 	int lf;
224 
225 	mutex_lock(&rvu->rsrc_lock);
226 	for (lf = 0; lf < block->lf.max; lf++) {
227 		if (block->fn_map[lf] == pcifunc) {
228 			if (slot == match) {
229 				mutex_unlock(&rvu->rsrc_lock);
230 				return lf;
231 			}
232 			match++;
233 		}
234 	}
235 	mutex_unlock(&rvu->rsrc_lock);
236 	return -ENODEV;
237 }
238 
239 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
240  * Some silicon variants of OcteonTX2 supports
241  * multiple blocks of same type.
242  *
243  * @pcifunc has to be zero when no LF is yet attached.
244  *
245  * For a pcifunc if LFs are attached from multiple blocks of same type, then
246  * return blkaddr of first encountered block.
247  */
rvu_get_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc)248 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
249 {
250 	int devnum, blkaddr = -ENODEV;
251 	u64 cfg, reg;
252 	bool is_pf;
253 
254 	switch (blktype) {
255 	case BLKTYPE_NPC:
256 		blkaddr = BLKADDR_NPC;
257 		goto exit;
258 	case BLKTYPE_NPA:
259 		blkaddr = BLKADDR_NPA;
260 		goto exit;
261 	case BLKTYPE_NIX:
262 		/* For now assume NIX0 */
263 		if (!pcifunc) {
264 			blkaddr = BLKADDR_NIX0;
265 			goto exit;
266 		}
267 		break;
268 	case BLKTYPE_SSO:
269 		blkaddr = BLKADDR_SSO;
270 		goto exit;
271 	case BLKTYPE_SSOW:
272 		blkaddr = BLKADDR_SSOW;
273 		goto exit;
274 	case BLKTYPE_TIM:
275 		blkaddr = BLKADDR_TIM;
276 		goto exit;
277 	case BLKTYPE_CPT:
278 		/* For now assume CPT0 */
279 		if (!pcifunc) {
280 			blkaddr = BLKADDR_CPT0;
281 			goto exit;
282 		}
283 		break;
284 	}
285 
286 	/* Check if this is a RVU PF or VF */
287 	if (pcifunc & RVU_PFVF_FUNC_MASK) {
288 		is_pf = false;
289 		devnum = rvu_get_hwvf(rvu, pcifunc);
290 	} else {
291 		is_pf = true;
292 		devnum = rvu_get_pf(pcifunc);
293 	}
294 
295 	/* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' or
296 	 * 'BLKADDR_NIX1'.
297 	 */
298 	if (blktype == BLKTYPE_NIX) {
299 		reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(0) :
300 			RVU_PRIV_HWVFX_NIXX_CFG(0);
301 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
302 		if (cfg) {
303 			blkaddr = BLKADDR_NIX0;
304 			goto exit;
305 		}
306 
307 		reg = is_pf ? RVU_PRIV_PFX_NIXX_CFG(1) :
308 			RVU_PRIV_HWVFX_NIXX_CFG(1);
309 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
310 		if (cfg)
311 			blkaddr = BLKADDR_NIX1;
312 	}
313 
314 	if (blktype == BLKTYPE_CPT) {
315 		reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(0) :
316 			RVU_PRIV_HWVFX_CPTX_CFG(0);
317 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
318 		if (cfg) {
319 			blkaddr = BLKADDR_CPT0;
320 			goto exit;
321 		}
322 
323 		reg = is_pf ? RVU_PRIV_PFX_CPTX_CFG(1) :
324 			RVU_PRIV_HWVFX_CPTX_CFG(1);
325 		cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
326 		if (cfg)
327 			blkaddr = BLKADDR_CPT1;
328 	}
329 
330 exit:
331 	if (is_block_implemented(rvu->hw, blkaddr))
332 		return blkaddr;
333 	return -ENODEV;
334 }
335 
rvu_update_rsrc_map(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,u16 pcifunc,u16 lf,bool attach)336 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
337 				struct rvu_block *block, u16 pcifunc,
338 				u16 lf, bool attach)
339 {
340 	int devnum, num_lfs = 0;
341 	bool is_pf;
342 	u64 reg;
343 
344 	if (lf >= block->lf.max) {
345 		dev_err(&rvu->pdev->dev,
346 			"%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
347 			__func__, lf, block->name, block->lf.max);
348 		return;
349 	}
350 
351 	/* Check if this is for a RVU PF or VF */
352 	if (pcifunc & RVU_PFVF_FUNC_MASK) {
353 		is_pf = false;
354 		devnum = rvu_get_hwvf(rvu, pcifunc);
355 	} else {
356 		is_pf = true;
357 		devnum = rvu_get_pf(pcifunc);
358 	}
359 
360 	block->fn_map[lf] = attach ? pcifunc : 0;
361 
362 	switch (block->addr) {
363 	case BLKADDR_NPA:
364 		pfvf->npalf = attach ? true : false;
365 		num_lfs = pfvf->npalf;
366 		break;
367 	case BLKADDR_NIX0:
368 	case BLKADDR_NIX1:
369 		pfvf->nixlf = attach ? true : false;
370 		num_lfs = pfvf->nixlf;
371 		break;
372 	case BLKADDR_SSO:
373 		attach ? pfvf->sso++ : pfvf->sso--;
374 		num_lfs = pfvf->sso;
375 		break;
376 	case BLKADDR_SSOW:
377 		attach ? pfvf->ssow++ : pfvf->ssow--;
378 		num_lfs = pfvf->ssow;
379 		break;
380 	case BLKADDR_TIM:
381 		attach ? pfvf->timlfs++ : pfvf->timlfs--;
382 		num_lfs = pfvf->timlfs;
383 		break;
384 	case BLKADDR_CPT0:
385 		attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
386 		num_lfs = pfvf->cptlfs;
387 		break;
388 	case BLKADDR_CPT1:
389 		attach ? pfvf->cpt1_lfs++ : pfvf->cpt1_lfs--;
390 		num_lfs = pfvf->cpt1_lfs;
391 		break;
392 	}
393 
394 	reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
395 	rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
396 }
397 
rvu_get_pf(u16 pcifunc)398 inline int rvu_get_pf(u16 pcifunc)
399 {
400 	return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
401 }
402 
rvu_get_pf_numvfs(struct rvu * rvu,int pf,int * numvfs,int * hwvf)403 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
404 {
405 	u64 cfg;
406 
407 	/* Get numVFs attached to this PF and first HWVF */
408 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
409 	if (numvfs)
410 		*numvfs = (cfg >> 12) & 0xFF;
411 	if (hwvf)
412 		*hwvf = cfg & 0xFFF;
413 }
414 
rvu_get_hwvf(struct rvu * rvu,int pcifunc)415 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
416 {
417 	int pf, func;
418 	u64 cfg;
419 
420 	pf = rvu_get_pf(pcifunc);
421 	func = pcifunc & RVU_PFVF_FUNC_MASK;
422 
423 	/* Get first HWVF attached to this PF */
424 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
425 
426 	return ((cfg & 0xFFF) + func - 1);
427 }
428 
rvu_get_pfvf(struct rvu * rvu,int pcifunc)429 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
430 {
431 	/* Check if it is a PF or VF */
432 	if (pcifunc & RVU_PFVF_FUNC_MASK)
433 		return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
434 	else
435 		return &rvu->pf[rvu_get_pf(pcifunc)];
436 }
437 
is_pf_func_valid(struct rvu * rvu,u16 pcifunc)438 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
439 {
440 	int pf, vf, nvfs;
441 	u64 cfg;
442 
443 	pf = rvu_get_pf(pcifunc);
444 	if (pf >= rvu->hw->total_pfs)
445 		return false;
446 
447 	if (!(pcifunc & RVU_PFVF_FUNC_MASK))
448 		return true;
449 
450 	/* Check if VF is within number of VFs attached to this PF */
451 	vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
452 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
453 	nvfs = (cfg >> 12) & 0xFF;
454 	if (vf >= nvfs)
455 		return false;
456 
457 	return true;
458 }
459 
is_block_implemented(struct rvu_hwinfo * hw,int blkaddr)460 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
461 {
462 	struct rvu_block *block;
463 
464 	if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
465 		return false;
466 
467 	block = &hw->block[blkaddr];
468 	return block->implemented;
469 }
470 
rvu_check_block_implemented(struct rvu * rvu)471 static void rvu_check_block_implemented(struct rvu *rvu)
472 {
473 	struct rvu_hwinfo *hw = rvu->hw;
474 	struct rvu_block *block;
475 	int blkid;
476 	u64 cfg;
477 
478 	/* For each block check if 'implemented' bit is set */
479 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
480 		block = &hw->block[blkid];
481 		cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
482 		if (cfg & BIT_ULL(11))
483 			block->implemented = true;
484 	}
485 }
486 
rvu_setup_rvum_blk_revid(struct rvu * rvu)487 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
488 {
489 	rvu_write64(rvu, BLKADDR_RVUM,
490 		    RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
491 		    RVU_BLK_RVUM_REVID);
492 }
493 
rvu_clear_rvum_blk_revid(struct rvu * rvu)494 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
495 {
496 	rvu_write64(rvu, BLKADDR_RVUM,
497 		    RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
498 }
499 
rvu_lf_reset(struct rvu * rvu,struct rvu_block * block,int lf)500 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
501 {
502 	int err;
503 
504 	if (!block->implemented)
505 		return 0;
506 
507 	rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
508 	err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
509 			   true);
510 	return err;
511 }
512 
rvu_block_reset(struct rvu * rvu,int blkaddr,u64 rst_reg)513 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
514 {
515 	struct rvu_block *block = &rvu->hw->block[blkaddr];
516 	int err;
517 
518 	if (!block->implemented)
519 		return;
520 
521 	rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
522 	err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
523 	if (err) {
524 		dev_err(rvu->dev, "HW block:%d reset timeout retrying again\n", blkaddr);
525 		while (rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true) == -EBUSY)
526 			;
527 	}
528 }
529 
rvu_reset_all_blocks(struct rvu * rvu)530 static void rvu_reset_all_blocks(struct rvu *rvu)
531 {
532 	/* Do a HW reset of all RVU blocks */
533 	rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
534 	rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
535 	rvu_block_reset(rvu, BLKADDR_NIX1, NIX_AF_BLK_RST);
536 	rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
537 	rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
538 	rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
539 	rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
540 	rvu_block_reset(rvu, BLKADDR_CPT1, CPT_AF_BLK_RST);
541 	rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
542 	rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
543 	rvu_block_reset(rvu, BLKADDR_NDC_NIX1_RX, NDC_AF_BLK_RST);
544 	rvu_block_reset(rvu, BLKADDR_NDC_NIX1_TX, NDC_AF_BLK_RST);
545 	rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
546 }
547 
rvu_scan_block(struct rvu * rvu,struct rvu_block * block)548 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
549 {
550 	struct rvu_pfvf *pfvf;
551 	u64 cfg;
552 	int lf;
553 
554 	for (lf = 0; lf < block->lf.max; lf++) {
555 		cfg = rvu_read64(rvu, block->addr,
556 				 block->lfcfg_reg | (lf << block->lfshift));
557 		if (!(cfg & BIT_ULL(63)))
558 			continue;
559 
560 		/* Set this resource as being used */
561 		__set_bit(lf, block->lf.bmap);
562 
563 		/* Get, to whom this LF is attached */
564 		pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
565 		rvu_update_rsrc_map(rvu, pfvf, block,
566 				    (cfg >> 8) & 0xFFFF, lf, true);
567 
568 		/* Set start MSIX vector for this LF within this PF/VF */
569 		rvu_set_msix_offset(rvu, pfvf, block, lf);
570 	}
571 }
572 
rvu_check_min_msix_vec(struct rvu * rvu,int nvecs,int pf,int vf)573 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
574 {
575 	int min_vecs;
576 
577 	if (!vf)
578 		goto check_pf;
579 
580 	if (!nvecs) {
581 		dev_warn(rvu->dev,
582 			 "PF%d:VF%d is configured with zero msix vectors, %d\n",
583 			 pf, vf - 1, nvecs);
584 	}
585 	return;
586 
587 check_pf:
588 	if (pf == 0)
589 		min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
590 	else
591 		min_vecs = RVU_PF_INT_VEC_CNT;
592 
593 	if (!(nvecs < min_vecs))
594 		return;
595 	dev_warn(rvu->dev,
596 		 "PF%d is configured with too few vectors, %d, min is %d\n",
597 		 pf, nvecs, min_vecs);
598 }
599 
rvu_setup_msix_resources(struct rvu * rvu)600 static int rvu_setup_msix_resources(struct rvu *rvu)
601 {
602 	struct rvu_hwinfo *hw = rvu->hw;
603 	int pf, vf, numvfs, hwvf, err;
604 	int nvecs, offset, max_msix;
605 	struct rvu_pfvf *pfvf;
606 	u64 cfg, phy_addr;
607 	dma_addr_t iova;
608 
609 	for (pf = 0; pf < hw->total_pfs; pf++) {
610 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
611 		/* If PF is not enabled, nothing to do */
612 		if (!((cfg >> 20) & 0x01))
613 			continue;
614 
615 		rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
616 
617 		pfvf = &rvu->pf[pf];
618 		/* Get num of MSIX vectors attached to this PF */
619 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
620 		pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
621 		rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
622 
623 		/* Alloc msix bitmap for this PF */
624 		err = rvu_alloc_bitmap(&pfvf->msix);
625 		if (err)
626 			return err;
627 
628 		/* Allocate memory for MSIX vector to RVU block LF mapping */
629 		pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
630 						sizeof(u16), GFP_KERNEL);
631 		if (!pfvf->msix_lfmap)
632 			return -ENOMEM;
633 
634 		/* For PF0 (AF) firmware will set msix vector offsets for
635 		 * AF, block AF and PF0_INT vectors, so jump to VFs.
636 		 */
637 		if (!pf)
638 			goto setup_vfmsix;
639 
640 		/* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
641 		 * These are allocated on driver init and never freed,
642 		 * so no need to set 'msix_lfmap' for these.
643 		 */
644 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
645 		nvecs = (cfg >> 12) & 0xFF;
646 		cfg &= ~0x7FFULL;
647 		offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
648 		rvu_write64(rvu, BLKADDR_RVUM,
649 			    RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
650 setup_vfmsix:
651 		/* Alloc msix bitmap for VFs */
652 		for (vf = 0; vf < numvfs; vf++) {
653 			pfvf =  &rvu->hwvf[hwvf + vf];
654 			/* Get num of MSIX vectors attached to this VF */
655 			cfg = rvu_read64(rvu, BLKADDR_RVUM,
656 					 RVU_PRIV_PFX_MSIX_CFG(pf));
657 			pfvf->msix.max = (cfg & 0xFFF) + 1;
658 			rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
659 
660 			/* Alloc msix bitmap for this VF */
661 			err = rvu_alloc_bitmap(&pfvf->msix);
662 			if (err)
663 				return err;
664 
665 			pfvf->msix_lfmap =
666 				devm_kcalloc(rvu->dev, pfvf->msix.max,
667 					     sizeof(u16), GFP_KERNEL);
668 			if (!pfvf->msix_lfmap)
669 				return -ENOMEM;
670 
671 			/* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
672 			 * These are allocated on driver init and never freed,
673 			 * so no need to set 'msix_lfmap' for these.
674 			 */
675 			cfg = rvu_read64(rvu, BLKADDR_RVUM,
676 					 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
677 			nvecs = (cfg >> 12) & 0xFF;
678 			cfg &= ~0x7FFULL;
679 			offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
680 			rvu_write64(rvu, BLKADDR_RVUM,
681 				    RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
682 				    cfg | offset);
683 		}
684 	}
685 
686 	/* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
687 	 * create an IOMMU mapping for the physical address configured by
688 	 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
689 	 */
690 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
691 	max_msix = cfg & 0xFFFFF;
692 	if (rvu->fwdata && rvu->fwdata->msixtr_base)
693 		phy_addr = rvu->fwdata->msixtr_base;
694 	else
695 		phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
696 
697 	iova = dma_map_resource(rvu->dev, phy_addr,
698 				max_msix * PCI_MSIX_ENTRY_SIZE,
699 				DMA_BIDIRECTIONAL, 0);
700 
701 	if (dma_mapping_error(rvu->dev, iova))
702 		return -ENOMEM;
703 
704 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
705 	rvu->msix_base_iova = iova;
706 	rvu->msixtr_base_phy = phy_addr;
707 
708 	return 0;
709 }
710 
rvu_reset_msix(struct rvu * rvu)711 static void rvu_reset_msix(struct rvu *rvu)
712 {
713 	/* Restore msixtr base register */
714 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
715 		    rvu->msixtr_base_phy);
716 }
717 
rvu_free_hw_resources(struct rvu * rvu)718 static void rvu_free_hw_resources(struct rvu *rvu)
719 {
720 	struct rvu_hwinfo *hw = rvu->hw;
721 	struct rvu_block *block;
722 	struct rvu_pfvf  *pfvf;
723 	int id, max_msix;
724 	u64 cfg;
725 
726 	rvu_npa_freemem(rvu);
727 	rvu_npc_freemem(rvu);
728 	rvu_nix_freemem(rvu);
729 
730 	/* Free block LF bitmaps */
731 	for (id = 0; id < BLK_COUNT; id++) {
732 		block = &hw->block[id];
733 		kfree(block->lf.bmap);
734 	}
735 
736 	/* Free MSIX bitmaps */
737 	for (id = 0; id < hw->total_pfs; id++) {
738 		pfvf = &rvu->pf[id];
739 		kfree(pfvf->msix.bmap);
740 	}
741 
742 	for (id = 0; id < hw->total_vfs; id++) {
743 		pfvf = &rvu->hwvf[id];
744 		kfree(pfvf->msix.bmap);
745 	}
746 
747 	/* Unmap MSIX vector base IOVA mapping */
748 	if (!rvu->msix_base_iova)
749 		return;
750 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
751 	max_msix = cfg & 0xFFFFF;
752 	dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
753 			   max_msix * PCI_MSIX_ENTRY_SIZE,
754 			   DMA_BIDIRECTIONAL, 0);
755 
756 	rvu_reset_msix(rvu);
757 	mutex_destroy(&rvu->rsrc_lock);
758 }
759 
rvu_setup_pfvf_macaddress(struct rvu * rvu)760 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
761 {
762 	struct rvu_hwinfo *hw = rvu->hw;
763 	int pf, vf, numvfs, hwvf;
764 	struct rvu_pfvf *pfvf;
765 	u64 *mac;
766 
767 	for (pf = 0; pf < hw->total_pfs; pf++) {
768 		/* For PF0(AF), Assign MAC address to only VFs (LBKVFs) */
769 		if (!pf)
770 			goto lbkvf;
771 
772 		if (!is_pf_cgxmapped(rvu, pf))
773 			continue;
774 		/* Assign MAC address to PF */
775 		pfvf = &rvu->pf[pf];
776 		if (rvu->fwdata && pf < PF_MACNUM_MAX) {
777 			mac = &rvu->fwdata->pf_macs[pf];
778 			if (*mac)
779 				u64_to_ether_addr(*mac, pfvf->mac_addr);
780 			else
781 				eth_random_addr(pfvf->mac_addr);
782 		} else {
783 			eth_random_addr(pfvf->mac_addr);
784 		}
785 		ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
786 
787 lbkvf:
788 		/* Assign MAC address to VFs*/
789 		rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
790 		for (vf = 0; vf < numvfs; vf++, hwvf++) {
791 			pfvf = &rvu->hwvf[hwvf];
792 			if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
793 				mac = &rvu->fwdata->vf_macs[hwvf];
794 				if (*mac)
795 					u64_to_ether_addr(*mac, pfvf->mac_addr);
796 				else
797 					eth_random_addr(pfvf->mac_addr);
798 			} else {
799 				eth_random_addr(pfvf->mac_addr);
800 			}
801 			ether_addr_copy(pfvf->default_mac, pfvf->mac_addr);
802 		}
803 	}
804 }
805 
rvu_fwdata_init(struct rvu * rvu)806 static int rvu_fwdata_init(struct rvu *rvu)
807 {
808 	u64 fwdbase;
809 	int err;
810 
811 	/* Get firmware data base address */
812 	err = cgx_get_fwdata_base(&fwdbase);
813 	if (err)
814 		goto fail;
815 	rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
816 	if (!rvu->fwdata)
817 		goto fail;
818 	if (!is_rvu_fwdata_valid(rvu)) {
819 		dev_err(rvu->dev,
820 			"Mismatch in 'fwdata' struct btw kernel and firmware\n");
821 		iounmap(rvu->fwdata);
822 		rvu->fwdata = NULL;
823 		return -EINVAL;
824 	}
825 	return 0;
826 fail:
827 	dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
828 	return -EIO;
829 }
830 
rvu_fwdata_exit(struct rvu * rvu)831 static void rvu_fwdata_exit(struct rvu *rvu)
832 {
833 	if (rvu->fwdata)
834 		iounmap(rvu->fwdata);
835 }
836 
rvu_setup_nix_hw_resource(struct rvu * rvu,int blkaddr)837 static int rvu_setup_nix_hw_resource(struct rvu *rvu, int blkaddr)
838 {
839 	struct rvu_hwinfo *hw = rvu->hw;
840 	struct rvu_block *block;
841 	int blkid;
842 	u64 cfg;
843 
844 	/* Init NIX LF's bitmap */
845 	block = &hw->block[blkaddr];
846 	if (!block->implemented)
847 		return 0;
848 	blkid = (blkaddr == BLKADDR_NIX0) ? 0 : 1;
849 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);
850 	block->lf.max = cfg & 0xFFF;
851 	block->addr = blkaddr;
852 	block->type = BLKTYPE_NIX;
853 	block->lfshift = 8;
854 	block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
855 	block->pf_lfcnt_reg = RVU_PRIV_PFX_NIXX_CFG(blkid);
856 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIXX_CFG(blkid);
857 	block->lfcfg_reg = NIX_PRIV_LFX_CFG;
858 	block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
859 	block->lfreset_reg = NIX_AF_LF_RST;
860 	sprintf(block->name, "NIX%d", blkid);
861 	rvu->nix_blkaddr[blkid] = blkaddr;
862 	return rvu_alloc_bitmap(&block->lf);
863 }
864 
rvu_setup_cpt_hw_resource(struct rvu * rvu,int blkaddr)865 static int rvu_setup_cpt_hw_resource(struct rvu *rvu, int blkaddr)
866 {
867 	struct rvu_hwinfo *hw = rvu->hw;
868 	struct rvu_block *block;
869 	int blkid;
870 	u64 cfg;
871 
872 	/* Init CPT LF's bitmap */
873 	block = &hw->block[blkaddr];
874 	if (!block->implemented)
875 		return 0;
876 	blkid = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
877 	cfg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
878 	block->lf.max = cfg & 0xFF;
879 	block->addr = blkaddr;
880 	block->type = BLKTYPE_CPT;
881 	block->multislot = true;
882 	block->lfshift = 3;
883 	block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
884 	block->pf_lfcnt_reg = RVU_PRIV_PFX_CPTX_CFG(blkid);
885 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPTX_CFG(blkid);
886 	block->lfcfg_reg = CPT_PRIV_LFX_CFG;
887 	block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
888 	block->lfreset_reg = CPT_AF_LF_RST;
889 	sprintf(block->name, "CPT%d", blkid);
890 	return rvu_alloc_bitmap(&block->lf);
891 }
892 
rvu_get_lbk_bufsize(struct rvu * rvu)893 static void rvu_get_lbk_bufsize(struct rvu *rvu)
894 {
895 	struct pci_dev *pdev = NULL;
896 	void __iomem *base;
897 	u64 lbk_const;
898 
899 	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
900 			      PCI_DEVID_OCTEONTX2_LBK, pdev);
901 	if (!pdev)
902 		return;
903 
904 	base = pci_ioremap_bar(pdev, 0);
905 	if (!base)
906 		goto err_put;
907 
908 	lbk_const = readq(base + LBK_CONST);
909 
910 	/* cache fifo size */
911 	rvu->hw->lbk_bufsize = FIELD_GET(LBK_CONST_BUF_SIZE, lbk_const);
912 
913 	iounmap(base);
914 err_put:
915 	pci_dev_put(pdev);
916 }
917 
rvu_setup_hw_resources(struct rvu * rvu)918 static int rvu_setup_hw_resources(struct rvu *rvu)
919 {
920 	struct rvu_hwinfo *hw = rvu->hw;
921 	struct rvu_block *block;
922 	int blkid, err;
923 	u64 cfg;
924 
925 	/* Get HW supported max RVU PF & VF count */
926 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
927 	hw->total_pfs = (cfg >> 32) & 0xFF;
928 	hw->total_vfs = (cfg >> 20) & 0xFFF;
929 	hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
930 
931 	/* Init NPA LF's bitmap */
932 	block = &hw->block[BLKADDR_NPA];
933 	if (!block->implemented)
934 		goto nix;
935 	cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
936 	block->lf.max = (cfg >> 16) & 0xFFF;
937 	block->addr = BLKADDR_NPA;
938 	block->type = BLKTYPE_NPA;
939 	block->lfshift = 8;
940 	block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
941 	block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
942 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
943 	block->lfcfg_reg = NPA_PRIV_LFX_CFG;
944 	block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
945 	block->lfreset_reg = NPA_AF_LF_RST;
946 	sprintf(block->name, "NPA");
947 	err = rvu_alloc_bitmap(&block->lf);
948 	if (err) {
949 		dev_err(rvu->dev,
950 			"%s: Failed to allocate NPA LF bitmap\n", __func__);
951 		return err;
952 	}
953 
954 nix:
955 	err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX0);
956 	if (err) {
957 		dev_err(rvu->dev,
958 			"%s: Failed to allocate NIX0 LFs bitmap\n", __func__);
959 		return err;
960 	}
961 
962 	err = rvu_setup_nix_hw_resource(rvu, BLKADDR_NIX1);
963 	if (err) {
964 		dev_err(rvu->dev,
965 			"%s: Failed to allocate NIX1 LFs bitmap\n", __func__);
966 		return err;
967 	}
968 
969 	/* Init SSO group's bitmap */
970 	block = &hw->block[BLKADDR_SSO];
971 	if (!block->implemented)
972 		goto ssow;
973 	cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
974 	block->lf.max = cfg & 0xFFFF;
975 	block->addr = BLKADDR_SSO;
976 	block->type = BLKTYPE_SSO;
977 	block->multislot = true;
978 	block->lfshift = 3;
979 	block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
980 	block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
981 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
982 	block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
983 	block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
984 	block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
985 	sprintf(block->name, "SSO GROUP");
986 	err = rvu_alloc_bitmap(&block->lf);
987 	if (err) {
988 		dev_err(rvu->dev,
989 			"%s: Failed to allocate SSO LF bitmap\n", __func__);
990 		return err;
991 	}
992 
993 ssow:
994 	/* Init SSO workslot's bitmap */
995 	block = &hw->block[BLKADDR_SSOW];
996 	if (!block->implemented)
997 		goto tim;
998 	block->lf.max = (cfg >> 56) & 0xFF;
999 	block->addr = BLKADDR_SSOW;
1000 	block->type = BLKTYPE_SSOW;
1001 	block->multislot = true;
1002 	block->lfshift = 3;
1003 	block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
1004 	block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
1005 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
1006 	block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
1007 	block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
1008 	block->lfreset_reg = SSOW_AF_LF_HWS_RST;
1009 	sprintf(block->name, "SSOWS");
1010 	err = rvu_alloc_bitmap(&block->lf);
1011 	if (err) {
1012 		dev_err(rvu->dev,
1013 			"%s: Failed to allocate SSOW LF bitmap\n", __func__);
1014 		return err;
1015 	}
1016 
1017 tim:
1018 	/* Init TIM LF's bitmap */
1019 	block = &hw->block[BLKADDR_TIM];
1020 	if (!block->implemented)
1021 		goto cpt;
1022 	cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
1023 	block->lf.max = cfg & 0xFFFF;
1024 	block->addr = BLKADDR_TIM;
1025 	block->type = BLKTYPE_TIM;
1026 	block->multislot = true;
1027 	block->lfshift = 3;
1028 	block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
1029 	block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
1030 	block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
1031 	block->lfcfg_reg = TIM_PRIV_LFX_CFG;
1032 	block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
1033 	block->lfreset_reg = TIM_AF_LF_RST;
1034 	sprintf(block->name, "TIM");
1035 	err = rvu_alloc_bitmap(&block->lf);
1036 	if (err) {
1037 		dev_err(rvu->dev,
1038 			"%s: Failed to allocate TIM LF bitmap\n", __func__);
1039 		return err;
1040 	}
1041 
1042 cpt:
1043 	err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT0);
1044 	if (err) {
1045 		dev_err(rvu->dev,
1046 			"%s: Failed to allocate CPT0 LF bitmap\n", __func__);
1047 		return err;
1048 	}
1049 	err = rvu_setup_cpt_hw_resource(rvu, BLKADDR_CPT1);
1050 	if (err) {
1051 		dev_err(rvu->dev,
1052 			"%s: Failed to allocate CPT1 LF bitmap\n", __func__);
1053 		return err;
1054 	}
1055 
1056 	/* Allocate memory for PFVF data */
1057 	rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
1058 			       sizeof(struct rvu_pfvf), GFP_KERNEL);
1059 	if (!rvu->pf) {
1060 		dev_err(rvu->dev,
1061 			"%s: Failed to allocate memory for PF's rvu_pfvf struct\n", __func__);
1062 		return -ENOMEM;
1063 	}
1064 
1065 	rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
1066 				 sizeof(struct rvu_pfvf), GFP_KERNEL);
1067 	if (!rvu->hwvf) {
1068 		dev_err(rvu->dev,
1069 			"%s: Failed to allocate memory for VF's rvu_pfvf struct\n", __func__);
1070 		return -ENOMEM;
1071 	}
1072 
1073 	mutex_init(&rvu->rsrc_lock);
1074 
1075 	rvu_fwdata_init(rvu);
1076 
1077 	err = rvu_setup_msix_resources(rvu);
1078 	if (err) {
1079 		dev_err(rvu->dev,
1080 			"%s: Failed to setup MSIX resources\n", __func__);
1081 		return err;
1082 	}
1083 
1084 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1085 		block = &hw->block[blkid];
1086 		if (!block->lf.bmap)
1087 			continue;
1088 
1089 		/* Allocate memory for block LF/slot to pcifunc mapping info */
1090 		block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
1091 					     sizeof(u16), GFP_KERNEL);
1092 		if (!block->fn_map) {
1093 			err = -ENOMEM;
1094 			goto msix_err;
1095 		}
1096 
1097 		/* Scan all blocks to check if low level firmware has
1098 		 * already provisioned any of the resources to a PF/VF.
1099 		 */
1100 		rvu_scan_block(rvu, block);
1101 	}
1102 
1103 	err = rvu_set_channels_base(rvu);
1104 	if (err)
1105 		goto msix_err;
1106 
1107 	err = rvu_npc_init(rvu);
1108 	if (err) {
1109 		dev_err(rvu->dev, "%s: Failed to initialize npc\n", __func__);
1110 		goto npc_err;
1111 	}
1112 
1113 	err = rvu_cgx_init(rvu);
1114 	if (err) {
1115 		dev_err(rvu->dev, "%s: Failed to initialize cgx\n", __func__);
1116 		goto cgx_err;
1117 	}
1118 
1119 	/* Assign MACs for CGX mapped functions */
1120 	rvu_setup_pfvf_macaddress(rvu);
1121 
1122 	err = rvu_npa_init(rvu);
1123 	if (err) {
1124 		dev_err(rvu->dev, "%s: Failed to initialize npa\n", __func__);
1125 		goto npa_err;
1126 	}
1127 
1128 	rvu_get_lbk_bufsize(rvu);
1129 
1130 	err = rvu_nix_init(rvu);
1131 	if (err) {
1132 		dev_err(rvu->dev, "%s: Failed to initialize nix\n", __func__);
1133 		goto nix_err;
1134 	}
1135 
1136 	err = rvu_sdp_init(rvu);
1137 	if (err) {
1138 		dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
1139 		goto nix_err;
1140 	}
1141 
1142 	rvu_program_channels(rvu);
1143 
1144 	return 0;
1145 
1146 nix_err:
1147 	rvu_nix_freemem(rvu);
1148 npa_err:
1149 	rvu_npa_freemem(rvu);
1150 cgx_err:
1151 	rvu_cgx_exit(rvu);
1152 npc_err:
1153 	rvu_npc_freemem(rvu);
1154 	rvu_fwdata_exit(rvu);
1155 msix_err:
1156 	rvu_reset_msix(rvu);
1157 	return err;
1158 }
1159 
1160 /* NPA and NIX admin queue APIs */
rvu_aq_free(struct rvu * rvu,struct admin_queue * aq)1161 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
1162 {
1163 	if (!aq)
1164 		return;
1165 
1166 	qmem_free(rvu->dev, aq->inst);
1167 	qmem_free(rvu->dev, aq->res);
1168 	devm_kfree(rvu->dev, aq);
1169 }
1170 
rvu_aq_alloc(struct rvu * rvu,struct admin_queue ** ad_queue,int qsize,int inst_size,int res_size)1171 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
1172 		 int qsize, int inst_size, int res_size)
1173 {
1174 	struct admin_queue *aq;
1175 	int err;
1176 
1177 	*ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
1178 	if (!*ad_queue)
1179 		return -ENOMEM;
1180 	aq = *ad_queue;
1181 
1182 	/* Alloc memory for instructions i.e AQ */
1183 	err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
1184 	if (err) {
1185 		devm_kfree(rvu->dev, aq);
1186 		return err;
1187 	}
1188 
1189 	/* Alloc memory for results */
1190 	err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1191 	if (err) {
1192 		rvu_aq_free(rvu, aq);
1193 		return err;
1194 	}
1195 
1196 	spin_lock_init(&aq->lock);
1197 	return 0;
1198 }
1199 
rvu_mbox_handler_ready(struct rvu * rvu,struct msg_req * req,struct ready_msg_rsp * rsp)1200 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1201 			   struct ready_msg_rsp *rsp)
1202 {
1203 	if (rvu->fwdata) {
1204 		rsp->rclk_freq = rvu->fwdata->rclk;
1205 		rsp->sclk_freq = rvu->fwdata->sclk;
1206 	}
1207 	return 0;
1208 }
1209 
1210 /* Get current count of a RVU block's LF/slots
1211  * provisioned to a given RVU func.
1212  */
rvu_get_rsrc_mapcount(struct rvu_pfvf * pfvf,int blkaddr)1213 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr)
1214 {
1215 	switch (blkaddr) {
1216 	case BLKADDR_NPA:
1217 		return pfvf->npalf ? 1 : 0;
1218 	case BLKADDR_NIX0:
1219 	case BLKADDR_NIX1:
1220 		return pfvf->nixlf ? 1 : 0;
1221 	case BLKADDR_SSO:
1222 		return pfvf->sso;
1223 	case BLKADDR_SSOW:
1224 		return pfvf->ssow;
1225 	case BLKADDR_TIM:
1226 		return pfvf->timlfs;
1227 	case BLKADDR_CPT0:
1228 		return pfvf->cptlfs;
1229 	case BLKADDR_CPT1:
1230 		return pfvf->cpt1_lfs;
1231 	}
1232 	return 0;
1233 }
1234 
1235 /* Return true if LFs of block type are attached to pcifunc */
is_blktype_attached(struct rvu_pfvf * pfvf,int blktype)1236 static bool is_blktype_attached(struct rvu_pfvf *pfvf, int blktype)
1237 {
1238 	switch (blktype) {
1239 	case BLKTYPE_NPA:
1240 		return pfvf->npalf ? 1 : 0;
1241 	case BLKTYPE_NIX:
1242 		return pfvf->nixlf ? 1 : 0;
1243 	case BLKTYPE_SSO:
1244 		return !!pfvf->sso;
1245 	case BLKTYPE_SSOW:
1246 		return !!pfvf->ssow;
1247 	case BLKTYPE_TIM:
1248 		return !!pfvf->timlfs;
1249 	case BLKTYPE_CPT:
1250 		return pfvf->cptlfs || pfvf->cpt1_lfs;
1251 	}
1252 
1253 	return false;
1254 }
1255 
is_pffunc_map_valid(struct rvu * rvu,u16 pcifunc,int blktype)1256 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1257 {
1258 	struct rvu_pfvf *pfvf;
1259 
1260 	if (!is_pf_func_valid(rvu, pcifunc))
1261 		return false;
1262 
1263 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1264 
1265 	/* Check if this PFFUNC has a LF of type blktype attached */
1266 	if (!is_blktype_attached(pfvf, blktype))
1267 		return false;
1268 
1269 	return true;
1270 }
1271 
rvu_lookup_rsrc(struct rvu * rvu,struct rvu_block * block,int pcifunc,int slot)1272 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1273 			   int pcifunc, int slot)
1274 {
1275 	u64 val;
1276 
1277 	val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1278 	rvu_write64(rvu, block->addr, block->lookup_reg, val);
1279 	/* Wait for the lookup to finish */
1280 	/* TODO: put some timeout here */
1281 	while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1282 		;
1283 
1284 	val = rvu_read64(rvu, block->addr, block->lookup_reg);
1285 
1286 	/* Check LF valid bit */
1287 	if (!(val & (1ULL << 12)))
1288 		return -1;
1289 
1290 	return (val & 0xFFF);
1291 }
1292 
rvu_detach_block(struct rvu * rvu,int pcifunc,int blktype)1293 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1294 {
1295 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1296 	struct rvu_hwinfo *hw = rvu->hw;
1297 	struct rvu_block *block;
1298 	int slot, lf, num_lfs;
1299 	int blkaddr;
1300 
1301 	blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1302 	if (blkaddr < 0)
1303 		return;
1304 
1305 	if (blktype == BLKTYPE_NIX)
1306 		rvu_nix_reset_mac(pfvf, pcifunc);
1307 
1308 	block = &hw->block[blkaddr];
1309 
1310 	num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1311 	if (!num_lfs)
1312 		return;
1313 
1314 	for (slot = 0; slot < num_lfs; slot++) {
1315 		lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1316 		if (lf < 0) /* This should never happen */
1317 			continue;
1318 
1319 		/* Disable the LF */
1320 		rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1321 			    (lf << block->lfshift), 0x00ULL);
1322 
1323 		/* Update SW maintained mapping info as well */
1324 		rvu_update_rsrc_map(rvu, pfvf, block,
1325 				    pcifunc, lf, false);
1326 
1327 		/* Free the resource */
1328 		rvu_free_rsrc(&block->lf, lf);
1329 
1330 		/* Clear MSIX vector offset for this LF */
1331 		rvu_clear_msix_offset(rvu, pfvf, block, lf);
1332 	}
1333 }
1334 
rvu_detach_rsrcs(struct rvu * rvu,struct rsrc_detach * detach,u16 pcifunc)1335 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1336 			    u16 pcifunc)
1337 {
1338 	struct rvu_hwinfo *hw = rvu->hw;
1339 	bool detach_all = true;
1340 	struct rvu_block *block;
1341 	int blkid;
1342 
1343 	mutex_lock(&rvu->rsrc_lock);
1344 
1345 	/* Check for partial resource detach */
1346 	if (detach && detach->partial)
1347 		detach_all = false;
1348 
1349 	/* Check for RVU block's LFs attached to this func,
1350 	 * if so, detach them.
1351 	 */
1352 	for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1353 		block = &hw->block[blkid];
1354 		if (!block->lf.bmap)
1355 			continue;
1356 		if (!detach_all && detach) {
1357 			if (blkid == BLKADDR_NPA && !detach->npalf)
1358 				continue;
1359 			else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1360 				continue;
1361 			else if ((blkid == BLKADDR_NIX1) && !detach->nixlf)
1362 				continue;
1363 			else if ((blkid == BLKADDR_SSO) && !detach->sso)
1364 				continue;
1365 			else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1366 				continue;
1367 			else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1368 				continue;
1369 			else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1370 				continue;
1371 			else if ((blkid == BLKADDR_CPT1) && !detach->cptlfs)
1372 				continue;
1373 		}
1374 		rvu_detach_block(rvu, pcifunc, block->type);
1375 	}
1376 
1377 	mutex_unlock(&rvu->rsrc_lock);
1378 	return 0;
1379 }
1380 
rvu_mbox_handler_detach_resources(struct rvu * rvu,struct rsrc_detach * detach,struct msg_rsp * rsp)1381 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1382 				      struct rsrc_detach *detach,
1383 				      struct msg_rsp *rsp)
1384 {
1385 	return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1386 }
1387 
rvu_get_nix_blkaddr(struct rvu * rvu,u16 pcifunc)1388 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
1389 {
1390 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1391 	int blkaddr = BLKADDR_NIX0, vf;
1392 	struct rvu_pfvf *pf;
1393 
1394 	pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
1395 
1396 	/* All CGX mapped PFs are set with assigned NIX block during init */
1397 	if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
1398 		blkaddr = pf->nix_blkaddr;
1399 	} else if (is_afvf(pcifunc)) {
1400 		vf = pcifunc - 1;
1401 		/* Assign NIX based on VF number. All even numbered VFs get
1402 		 * NIX0 and odd numbered gets NIX1
1403 		 */
1404 		blkaddr = (vf & 1) ? BLKADDR_NIX1 : BLKADDR_NIX0;
1405 		/* NIX1 is not present on all silicons */
1406 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1407 			blkaddr = BLKADDR_NIX0;
1408 	}
1409 
1410 	/* if SDP1 then the blkaddr is NIX1 */
1411 	if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)
1412 		blkaddr = BLKADDR_NIX1;
1413 
1414 	switch (blkaddr) {
1415 	case BLKADDR_NIX1:
1416 		pfvf->nix_blkaddr = BLKADDR_NIX1;
1417 		pfvf->nix_rx_intf = NIX_INTFX_RX(1);
1418 		pfvf->nix_tx_intf = NIX_INTFX_TX(1);
1419 		break;
1420 	case BLKADDR_NIX0:
1421 	default:
1422 		pfvf->nix_blkaddr = BLKADDR_NIX0;
1423 		pfvf->nix_rx_intf = NIX_INTFX_RX(0);
1424 		pfvf->nix_tx_intf = NIX_INTFX_TX(0);
1425 		break;
1426 	}
1427 
1428 	return pfvf->nix_blkaddr;
1429 }
1430 
rvu_get_attach_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc,struct rsrc_attach * attach)1431 static int rvu_get_attach_blkaddr(struct rvu *rvu, int blktype,
1432 				  u16 pcifunc, struct rsrc_attach *attach)
1433 {
1434 	int blkaddr;
1435 
1436 	switch (blktype) {
1437 	case BLKTYPE_NIX:
1438 		blkaddr = rvu_get_nix_blkaddr(rvu, pcifunc);
1439 		break;
1440 	case BLKTYPE_CPT:
1441 		if (attach->hdr.ver < RVU_MULTI_BLK_VER)
1442 			return rvu_get_blkaddr(rvu, blktype, 0);
1443 		blkaddr = attach->cpt_blkaddr ? attach->cpt_blkaddr :
1444 			  BLKADDR_CPT0;
1445 		if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
1446 			return -ENODEV;
1447 		break;
1448 	default:
1449 		return rvu_get_blkaddr(rvu, blktype, 0);
1450 	}
1451 
1452 	if (is_block_implemented(rvu->hw, blkaddr))
1453 		return blkaddr;
1454 
1455 	return -ENODEV;
1456 }
1457 
rvu_attach_block(struct rvu * rvu,int pcifunc,int blktype,int num_lfs,struct rsrc_attach * attach)1458 static void rvu_attach_block(struct rvu *rvu, int pcifunc, int blktype,
1459 			     int num_lfs, struct rsrc_attach *attach)
1460 {
1461 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1462 	struct rvu_hwinfo *hw = rvu->hw;
1463 	struct rvu_block *block;
1464 	int slot, lf;
1465 	int blkaddr;
1466 	u64 cfg;
1467 
1468 	if (!num_lfs)
1469 		return;
1470 
1471 	blkaddr = rvu_get_attach_blkaddr(rvu, blktype, pcifunc, attach);
1472 	if (blkaddr < 0)
1473 		return;
1474 
1475 	block = &hw->block[blkaddr];
1476 	if (!block->lf.bmap)
1477 		return;
1478 
1479 	for (slot = 0; slot < num_lfs; slot++) {
1480 		/* Allocate the resource */
1481 		lf = rvu_alloc_rsrc(&block->lf);
1482 		if (lf < 0)
1483 			return;
1484 
1485 		cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1486 		rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1487 			    (lf << block->lfshift), cfg);
1488 		rvu_update_rsrc_map(rvu, pfvf, block,
1489 				    pcifunc, lf, true);
1490 
1491 		/* Set start MSIX vector for this LF within this PF/VF */
1492 		rvu_set_msix_offset(rvu, pfvf, block, lf);
1493 	}
1494 }
1495 
rvu_check_rsrc_availability(struct rvu * rvu,struct rsrc_attach * req,u16 pcifunc)1496 static int rvu_check_rsrc_availability(struct rvu *rvu,
1497 				       struct rsrc_attach *req, u16 pcifunc)
1498 {
1499 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1500 	int free_lfs, mappedlfs, blkaddr;
1501 	struct rvu_hwinfo *hw = rvu->hw;
1502 	struct rvu_block *block;
1503 
1504 	/* Only one NPA LF can be attached */
1505 	if (req->npalf && !is_blktype_attached(pfvf, BLKTYPE_NPA)) {
1506 		block = &hw->block[BLKADDR_NPA];
1507 		free_lfs = rvu_rsrc_free_count(&block->lf);
1508 		if (!free_lfs)
1509 			goto fail;
1510 	} else if (req->npalf) {
1511 		dev_err(&rvu->pdev->dev,
1512 			"Func 0x%x: Invalid req, already has NPA\n",
1513 			 pcifunc);
1514 		return -EINVAL;
1515 	}
1516 
1517 	/* Only one NIX LF can be attached */
1518 	if (req->nixlf && !is_blktype_attached(pfvf, BLKTYPE_NIX)) {
1519 		blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_NIX,
1520 						 pcifunc, req);
1521 		if (blkaddr < 0)
1522 			return blkaddr;
1523 		block = &hw->block[blkaddr];
1524 		free_lfs = rvu_rsrc_free_count(&block->lf);
1525 		if (!free_lfs)
1526 			goto fail;
1527 	} else if (req->nixlf) {
1528 		dev_err(&rvu->pdev->dev,
1529 			"Func 0x%x: Invalid req, already has NIX\n",
1530 			pcifunc);
1531 		return -EINVAL;
1532 	}
1533 
1534 	if (req->sso) {
1535 		block = &hw->block[BLKADDR_SSO];
1536 		/* Is request within limits ? */
1537 		if (req->sso > block->lf.max) {
1538 			dev_err(&rvu->pdev->dev,
1539 				"Func 0x%x: Invalid SSO req, %d > max %d\n",
1540 				 pcifunc, req->sso, block->lf.max);
1541 			return -EINVAL;
1542 		}
1543 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1544 		free_lfs = rvu_rsrc_free_count(&block->lf);
1545 		/* Check if additional resources are available */
1546 		if (req->sso > mappedlfs &&
1547 		    ((req->sso - mappedlfs) > free_lfs))
1548 			goto fail;
1549 	}
1550 
1551 	if (req->ssow) {
1552 		block = &hw->block[BLKADDR_SSOW];
1553 		if (req->ssow > block->lf.max) {
1554 			dev_err(&rvu->pdev->dev,
1555 				"Func 0x%x: Invalid SSOW req, %d > max %d\n",
1556 				 pcifunc, req->sso, block->lf.max);
1557 			return -EINVAL;
1558 		}
1559 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1560 		free_lfs = rvu_rsrc_free_count(&block->lf);
1561 		if (req->ssow > mappedlfs &&
1562 		    ((req->ssow - mappedlfs) > free_lfs))
1563 			goto fail;
1564 	}
1565 
1566 	if (req->timlfs) {
1567 		block = &hw->block[BLKADDR_TIM];
1568 		if (req->timlfs > block->lf.max) {
1569 			dev_err(&rvu->pdev->dev,
1570 				"Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1571 				 pcifunc, req->timlfs, block->lf.max);
1572 			return -EINVAL;
1573 		}
1574 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1575 		free_lfs = rvu_rsrc_free_count(&block->lf);
1576 		if (req->timlfs > mappedlfs &&
1577 		    ((req->timlfs - mappedlfs) > free_lfs))
1578 			goto fail;
1579 	}
1580 
1581 	if (req->cptlfs) {
1582 		blkaddr = rvu_get_attach_blkaddr(rvu, BLKTYPE_CPT,
1583 						 pcifunc, req);
1584 		if (blkaddr < 0)
1585 			return blkaddr;
1586 		block = &hw->block[blkaddr];
1587 		if (req->cptlfs > block->lf.max) {
1588 			dev_err(&rvu->pdev->dev,
1589 				"Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1590 				 pcifunc, req->cptlfs, block->lf.max);
1591 			return -EINVAL;
1592 		}
1593 		mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
1594 		free_lfs = rvu_rsrc_free_count(&block->lf);
1595 		if (req->cptlfs > mappedlfs &&
1596 		    ((req->cptlfs - mappedlfs) > free_lfs))
1597 			goto fail;
1598 	}
1599 
1600 	return 0;
1601 
1602 fail:
1603 	dev_info(rvu->dev, "Request for %s failed\n", block->name);
1604 	return -ENOSPC;
1605 }
1606 
rvu_attach_from_same_block(struct rvu * rvu,int blktype,struct rsrc_attach * attach)1607 static bool rvu_attach_from_same_block(struct rvu *rvu, int blktype,
1608 				       struct rsrc_attach *attach)
1609 {
1610 	int blkaddr, num_lfs;
1611 
1612 	blkaddr = rvu_get_attach_blkaddr(rvu, blktype,
1613 					 attach->hdr.pcifunc, attach);
1614 	if (blkaddr < 0)
1615 		return false;
1616 
1617 	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, attach->hdr.pcifunc),
1618 					blkaddr);
1619 	/* Requester already has LFs from given block ? */
1620 	return !!num_lfs;
1621 }
1622 
rvu_mbox_handler_attach_resources(struct rvu * rvu,struct rsrc_attach * attach,struct msg_rsp * rsp)1623 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1624 				      struct rsrc_attach *attach,
1625 				      struct msg_rsp *rsp)
1626 {
1627 	u16 pcifunc = attach->hdr.pcifunc;
1628 	int err;
1629 
1630 	/* If first request, detach all existing attached resources */
1631 	if (!attach->modify)
1632 		rvu_detach_rsrcs(rvu, NULL, pcifunc);
1633 
1634 	mutex_lock(&rvu->rsrc_lock);
1635 
1636 	/* Check if the request can be accommodated */
1637 	err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1638 	if (err)
1639 		goto exit;
1640 
1641 	/* Now attach the requested resources */
1642 	if (attach->npalf)
1643 		rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1, attach);
1644 
1645 	if (attach->nixlf)
1646 		rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1, attach);
1647 
1648 	if (attach->sso) {
1649 		/* RVU func doesn't know which exact LF or slot is attached
1650 		 * to it, it always sees as slot 0,1,2. So for a 'modify'
1651 		 * request, simply detach all existing attached LFs/slots
1652 		 * and attach a fresh.
1653 		 */
1654 		if (attach->modify)
1655 			rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1656 		rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO,
1657 				 attach->sso, attach);
1658 	}
1659 
1660 	if (attach->ssow) {
1661 		if (attach->modify)
1662 			rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1663 		rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW,
1664 				 attach->ssow, attach);
1665 	}
1666 
1667 	if (attach->timlfs) {
1668 		if (attach->modify)
1669 			rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1670 		rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM,
1671 				 attach->timlfs, attach);
1672 	}
1673 
1674 	if (attach->cptlfs) {
1675 		if (attach->modify &&
1676 		    rvu_attach_from_same_block(rvu, BLKTYPE_CPT, attach))
1677 			rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1678 		rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT,
1679 				 attach->cptlfs, attach);
1680 	}
1681 
1682 exit:
1683 	mutex_unlock(&rvu->rsrc_lock);
1684 	return err;
1685 }
1686 
rvu_get_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,int blkaddr,int lf)1687 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1688 			       int blkaddr, int lf)
1689 {
1690 	u16 vec;
1691 
1692 	if (lf < 0)
1693 		return MSIX_VECTOR_INVALID;
1694 
1695 	for (vec = 0; vec < pfvf->msix.max; vec++) {
1696 		if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1697 			return vec;
1698 	}
1699 	return MSIX_VECTOR_INVALID;
1700 }
1701 
rvu_set_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1702 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1703 				struct rvu_block *block, int lf)
1704 {
1705 	u16 nvecs, vec, offset;
1706 	u64 cfg;
1707 
1708 	cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1709 			 (lf << block->lfshift));
1710 	nvecs = (cfg >> 12) & 0xFF;
1711 
1712 	/* Check and alloc MSIX vectors, must be contiguous */
1713 	if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1714 		return;
1715 
1716 	offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1717 
1718 	/* Config MSIX offset in LF */
1719 	rvu_write64(rvu, block->addr, block->msixcfg_reg |
1720 		    (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1721 
1722 	/* Update the bitmap as well */
1723 	for (vec = 0; vec < nvecs; vec++)
1724 		pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1725 }
1726 
rvu_clear_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1727 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1728 				  struct rvu_block *block, int lf)
1729 {
1730 	u16 nvecs, vec, offset;
1731 	u64 cfg;
1732 
1733 	cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1734 			 (lf << block->lfshift));
1735 	nvecs = (cfg >> 12) & 0xFF;
1736 
1737 	/* Clear MSIX offset in LF */
1738 	rvu_write64(rvu, block->addr, block->msixcfg_reg |
1739 		    (lf << block->lfshift), cfg & ~0x7FFULL);
1740 
1741 	offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1742 
1743 	/* Update the mapping */
1744 	for (vec = 0; vec < nvecs; vec++)
1745 		pfvf->msix_lfmap[offset + vec] = 0;
1746 
1747 	/* Free the same in MSIX bitmap */
1748 	rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1749 }
1750 
rvu_mbox_handler_msix_offset(struct rvu * rvu,struct msg_req * req,struct msix_offset_rsp * rsp)1751 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1752 				 struct msix_offset_rsp *rsp)
1753 {
1754 	struct rvu_hwinfo *hw = rvu->hw;
1755 	u16 pcifunc = req->hdr.pcifunc;
1756 	struct rvu_pfvf *pfvf;
1757 	int lf, slot, blkaddr;
1758 
1759 	pfvf = rvu_get_pfvf(rvu, pcifunc);
1760 	if (!pfvf->msix.bmap)
1761 		return 0;
1762 
1763 	/* Set MSIX offsets for each block's LFs attached to this PF/VF */
1764 	lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1765 	rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1766 
1767 	/* Get BLKADDR from which LFs are attached to pcifunc */
1768 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1769 	if (blkaddr < 0) {
1770 		rsp->nix_msixoff = MSIX_VECTOR_INVALID;
1771 	} else {
1772 		lf = rvu_get_lf(rvu, &hw->block[blkaddr], pcifunc, 0);
1773 		rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, blkaddr, lf);
1774 	}
1775 
1776 	rsp->sso = pfvf->sso;
1777 	for (slot = 0; slot < rsp->sso; slot++) {
1778 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1779 		rsp->sso_msixoff[slot] =
1780 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1781 	}
1782 
1783 	rsp->ssow = pfvf->ssow;
1784 	for (slot = 0; slot < rsp->ssow; slot++) {
1785 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1786 		rsp->ssow_msixoff[slot] =
1787 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1788 	}
1789 
1790 	rsp->timlfs = pfvf->timlfs;
1791 	for (slot = 0; slot < rsp->timlfs; slot++) {
1792 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1793 		rsp->timlf_msixoff[slot] =
1794 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1795 	}
1796 
1797 	rsp->cptlfs = pfvf->cptlfs;
1798 	for (slot = 0; slot < rsp->cptlfs; slot++) {
1799 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1800 		rsp->cptlf_msixoff[slot] =
1801 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1802 	}
1803 
1804 	rsp->cpt1_lfs = pfvf->cpt1_lfs;
1805 	for (slot = 0; slot < rsp->cpt1_lfs; slot++) {
1806 		lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT1], pcifunc, slot);
1807 		rsp->cpt1_lf_msixoff[slot] =
1808 			rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT1, lf);
1809 	}
1810 
1811 	return 0;
1812 }
1813 
rvu_mbox_handler_free_rsrc_cnt(struct rvu * rvu,struct msg_req * req,struct free_rsrcs_rsp * rsp)1814 int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req,
1815 				   struct free_rsrcs_rsp *rsp)
1816 {
1817 	struct rvu_hwinfo *hw = rvu->hw;
1818 	struct rvu_block *block;
1819 	struct nix_txsch *txsch;
1820 	struct nix_hw *nix_hw;
1821 
1822 	mutex_lock(&rvu->rsrc_lock);
1823 
1824 	block = &hw->block[BLKADDR_NPA];
1825 	rsp->npa = rvu_rsrc_free_count(&block->lf);
1826 
1827 	block = &hw->block[BLKADDR_NIX0];
1828 	rsp->nix = rvu_rsrc_free_count(&block->lf);
1829 
1830 	block = &hw->block[BLKADDR_NIX1];
1831 	rsp->nix1 = rvu_rsrc_free_count(&block->lf);
1832 
1833 	block = &hw->block[BLKADDR_SSO];
1834 	rsp->sso = rvu_rsrc_free_count(&block->lf);
1835 
1836 	block = &hw->block[BLKADDR_SSOW];
1837 	rsp->ssow = rvu_rsrc_free_count(&block->lf);
1838 
1839 	block = &hw->block[BLKADDR_TIM];
1840 	rsp->tim = rvu_rsrc_free_count(&block->lf);
1841 
1842 	block = &hw->block[BLKADDR_CPT0];
1843 	rsp->cpt = rvu_rsrc_free_count(&block->lf);
1844 
1845 	block = &hw->block[BLKADDR_CPT1];
1846 	rsp->cpt1 = rvu_rsrc_free_count(&block->lf);
1847 
1848 	if (rvu->hw->cap.nix_fixed_txschq_mapping) {
1849 		rsp->schq[NIX_TXSCH_LVL_SMQ] = 1;
1850 		rsp->schq[NIX_TXSCH_LVL_TL4] = 1;
1851 		rsp->schq[NIX_TXSCH_LVL_TL3] = 1;
1852 		rsp->schq[NIX_TXSCH_LVL_TL2] = 1;
1853 		/* NIX1 */
1854 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1855 			goto out;
1856 		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] = 1;
1857 		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] = 1;
1858 		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] = 1;
1859 		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] = 1;
1860 	} else {
1861 		nix_hw = get_nix_hw(hw, BLKADDR_NIX0);
1862 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1863 		rsp->schq[NIX_TXSCH_LVL_SMQ] =
1864 				rvu_rsrc_free_count(&txsch->schq);
1865 
1866 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1867 		rsp->schq[NIX_TXSCH_LVL_TL4] =
1868 				rvu_rsrc_free_count(&txsch->schq);
1869 
1870 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1871 		rsp->schq[NIX_TXSCH_LVL_TL3] =
1872 				rvu_rsrc_free_count(&txsch->schq);
1873 
1874 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1875 		rsp->schq[NIX_TXSCH_LVL_TL2] =
1876 				rvu_rsrc_free_count(&txsch->schq);
1877 
1878 		if (!is_block_implemented(rvu->hw, BLKADDR_NIX1))
1879 			goto out;
1880 
1881 		nix_hw = get_nix_hw(hw, BLKADDR_NIX1);
1882 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
1883 		rsp->schq_nix1[NIX_TXSCH_LVL_SMQ] =
1884 				rvu_rsrc_free_count(&txsch->schq);
1885 
1886 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL4];
1887 		rsp->schq_nix1[NIX_TXSCH_LVL_TL4] =
1888 				rvu_rsrc_free_count(&txsch->schq);
1889 
1890 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL3];
1891 		rsp->schq_nix1[NIX_TXSCH_LVL_TL3] =
1892 				rvu_rsrc_free_count(&txsch->schq);
1893 
1894 		txsch = &nix_hw->txsch[NIX_TXSCH_LVL_TL2];
1895 		rsp->schq_nix1[NIX_TXSCH_LVL_TL2] =
1896 				rvu_rsrc_free_count(&txsch->schq);
1897 	}
1898 
1899 	rsp->schq_nix1[NIX_TXSCH_LVL_TL1] = 1;
1900 out:
1901 	rsp->schq[NIX_TXSCH_LVL_TL1] = 1;
1902 	mutex_unlock(&rvu->rsrc_lock);
1903 
1904 	return 0;
1905 }
1906 
rvu_mbox_handler_vf_flr(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1907 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1908 			    struct msg_rsp *rsp)
1909 {
1910 	u16 pcifunc = req->hdr.pcifunc;
1911 	u16 vf, numvfs;
1912 	u64 cfg;
1913 
1914 	vf = pcifunc & RVU_PFVF_FUNC_MASK;
1915 	cfg = rvu_read64(rvu, BLKADDR_RVUM,
1916 			 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
1917 	numvfs = (cfg >> 12) & 0xFF;
1918 
1919 	if (vf && vf <= numvfs)
1920 		__rvu_flr_handler(rvu, pcifunc);
1921 	else
1922 		return RVU_INVALID_VF_ID;
1923 
1924 	return 0;
1925 }
1926 
rvu_mbox_handler_get_hw_cap(struct rvu * rvu,struct msg_req * req,struct get_hw_cap_rsp * rsp)1927 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
1928 				struct get_hw_cap_rsp *rsp)
1929 {
1930 	struct rvu_hwinfo *hw = rvu->hw;
1931 
1932 	rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
1933 	rsp->nix_shaping = hw->cap.nix_shaping;
1934 
1935 	return 0;
1936 }
1937 
rvu_mbox_handler_set_vf_perm(struct rvu * rvu,struct set_vf_perm * req,struct msg_rsp * rsp)1938 int rvu_mbox_handler_set_vf_perm(struct rvu *rvu, struct set_vf_perm *req,
1939 				 struct msg_rsp *rsp)
1940 {
1941 	struct rvu_hwinfo *hw = rvu->hw;
1942 	u16 pcifunc = req->hdr.pcifunc;
1943 	struct rvu_pfvf *pfvf;
1944 	int blkaddr, nixlf;
1945 	u16 target;
1946 
1947 	/* Only PF can add VF permissions */
1948 	if ((pcifunc & RVU_PFVF_FUNC_MASK) || is_afvf(pcifunc))
1949 		return -EOPNOTSUPP;
1950 
1951 	target = (pcifunc & ~RVU_PFVF_FUNC_MASK) | (req->vf + 1);
1952 	pfvf = rvu_get_pfvf(rvu, target);
1953 
1954 	if (req->flags & RESET_VF_PERM) {
1955 		pfvf->flags &= RVU_CLEAR_VF_PERM;
1956 	} else if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) ^
1957 		 (req->flags & VF_TRUSTED)) {
1958 		change_bit(PF_SET_VF_TRUSTED, &pfvf->flags);
1959 		/* disable multicast and promisc entries */
1960 		if (!test_bit(PF_SET_VF_TRUSTED, &pfvf->flags)) {
1961 			blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, target);
1962 			if (blkaddr < 0)
1963 				return 0;
1964 			nixlf = rvu_get_lf(rvu, &hw->block[blkaddr],
1965 					   target, 0);
1966 			if (nixlf < 0)
1967 				return 0;
1968 			npc_enadis_default_mce_entry(rvu, target, nixlf,
1969 						     NIXLF_ALLMULTI_ENTRY,
1970 						     false);
1971 			npc_enadis_default_mce_entry(rvu, target, nixlf,
1972 						     NIXLF_PROMISC_ENTRY,
1973 						     false);
1974 		}
1975 	}
1976 
1977 	return 0;
1978 }
1979 
rvu_process_mbox_msg(struct otx2_mbox * mbox,int devid,struct mbox_msghdr * req)1980 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
1981 				struct mbox_msghdr *req)
1982 {
1983 	struct rvu *rvu = pci_get_drvdata(mbox->pdev);
1984 
1985 	/* Check if valid, if not reply with a invalid msg */
1986 	if (req->sig != OTX2_MBOX_REQ_SIG)
1987 		goto bad_message;
1988 
1989 	switch (req->id) {
1990 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
1991 	case _id: {							\
1992 		struct _rsp_type *rsp;					\
1993 		int err;						\
1994 									\
1995 		rsp = (struct _rsp_type *)otx2_mbox_alloc_msg(		\
1996 			mbox, devid,					\
1997 			sizeof(struct _rsp_type));			\
1998 		/* some handlers should complete even if reply */	\
1999 		/* could not be allocated */				\
2000 		if (!rsp &&						\
2001 		    _id != MBOX_MSG_DETACH_RESOURCES &&			\
2002 		    _id != MBOX_MSG_NIX_TXSCH_FREE &&			\
2003 		    _id != MBOX_MSG_VF_FLR)				\
2004 			return -ENOMEM;					\
2005 		if (rsp) {						\
2006 			rsp->hdr.id = _id;				\
2007 			rsp->hdr.sig = OTX2_MBOX_RSP_SIG;		\
2008 			rsp->hdr.pcifunc = req->pcifunc;		\
2009 			rsp->hdr.rc = 0;				\
2010 		}							\
2011 									\
2012 		err = rvu_mbox_handler_ ## _fn_name(rvu,		\
2013 						    (struct _req_type *)req, \
2014 						    rsp);		\
2015 		if (rsp && err)						\
2016 			rsp->hdr.rc = err;				\
2017 									\
2018 		trace_otx2_msg_process(mbox->pdev, _id, err);		\
2019 		return rsp ? err : -ENOMEM;				\
2020 	}
2021 MBOX_MESSAGES
2022 #undef M
2023 
2024 bad_message:
2025 	default:
2026 		otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
2027 		return -ENODEV;
2028 	}
2029 }
2030 
__rvu_mbox_handler(struct rvu_work * mwork,int type)2031 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
2032 {
2033 	struct rvu *rvu = mwork->rvu;
2034 	int offset, err, id, devid;
2035 	struct otx2_mbox_dev *mdev;
2036 	struct mbox_hdr *req_hdr;
2037 	struct mbox_msghdr *msg;
2038 	struct mbox_wq_info *mw;
2039 	struct otx2_mbox *mbox;
2040 
2041 	switch (type) {
2042 	case TYPE_AFPF:
2043 		mw = &rvu->afpf_wq_info;
2044 		break;
2045 	case TYPE_AFVF:
2046 		mw = &rvu->afvf_wq_info;
2047 		break;
2048 	default:
2049 		return;
2050 	}
2051 
2052 	devid = mwork - mw->mbox_wrk;
2053 	mbox = &mw->mbox;
2054 	mdev = &mbox->dev[devid];
2055 
2056 	/* Process received mbox messages */
2057 	req_hdr = mdev->mbase + mbox->rx_start;
2058 	if (mw->mbox_wrk[devid].num_msgs == 0)
2059 		return;
2060 
2061 	offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
2062 
2063 	for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
2064 		msg = mdev->mbase + offset;
2065 
2066 		/* Set which PF/VF sent this message based on mbox IRQ */
2067 		switch (type) {
2068 		case TYPE_AFPF:
2069 			msg->pcifunc &=
2070 				~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
2071 			msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
2072 			break;
2073 		case TYPE_AFVF:
2074 			msg->pcifunc &=
2075 				~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
2076 			msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
2077 			break;
2078 		}
2079 
2080 		err = rvu_process_mbox_msg(mbox, devid, msg);
2081 		if (!err) {
2082 			offset = mbox->rx_start + msg->next_msgoff;
2083 			continue;
2084 		}
2085 
2086 		if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
2087 			dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
2088 				 err, otx2_mbox_id2name(msg->id),
2089 				 msg->id, rvu_get_pf(msg->pcifunc),
2090 				 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
2091 		else
2092 			dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
2093 				 err, otx2_mbox_id2name(msg->id),
2094 				 msg->id, devid);
2095 	}
2096 	mw->mbox_wrk[devid].num_msgs = 0;
2097 
2098 	/* Send mbox responses to VF/PF */
2099 	otx2_mbox_msg_send(mbox, devid);
2100 }
2101 
rvu_afpf_mbox_handler(struct work_struct * work)2102 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
2103 {
2104 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2105 
2106 	__rvu_mbox_handler(mwork, TYPE_AFPF);
2107 }
2108 
rvu_afvf_mbox_handler(struct work_struct * work)2109 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
2110 {
2111 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2112 
2113 	__rvu_mbox_handler(mwork, TYPE_AFVF);
2114 }
2115 
__rvu_mbox_up_handler(struct rvu_work * mwork,int type)2116 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
2117 {
2118 	struct rvu *rvu = mwork->rvu;
2119 	struct otx2_mbox_dev *mdev;
2120 	struct mbox_hdr *rsp_hdr;
2121 	struct mbox_msghdr *msg;
2122 	struct mbox_wq_info *mw;
2123 	struct otx2_mbox *mbox;
2124 	int offset, id, devid;
2125 
2126 	switch (type) {
2127 	case TYPE_AFPF:
2128 		mw = &rvu->afpf_wq_info;
2129 		break;
2130 	case TYPE_AFVF:
2131 		mw = &rvu->afvf_wq_info;
2132 		break;
2133 	default:
2134 		return;
2135 	}
2136 
2137 	devid = mwork - mw->mbox_wrk_up;
2138 	mbox = &mw->mbox_up;
2139 	mdev = &mbox->dev[devid];
2140 
2141 	rsp_hdr = mdev->mbase + mbox->rx_start;
2142 	if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
2143 		dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
2144 		return;
2145 	}
2146 
2147 	offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
2148 
2149 	for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
2150 		msg = mdev->mbase + offset;
2151 
2152 		if (msg->id >= MBOX_MSG_MAX) {
2153 			dev_err(rvu->dev,
2154 				"Mbox msg with unknown ID 0x%x\n", msg->id);
2155 			goto end;
2156 		}
2157 
2158 		if (msg->sig != OTX2_MBOX_RSP_SIG) {
2159 			dev_err(rvu->dev,
2160 				"Mbox msg with wrong signature %x, ID 0x%x\n",
2161 				msg->sig, msg->id);
2162 			goto end;
2163 		}
2164 
2165 		switch (msg->id) {
2166 		case MBOX_MSG_CGX_LINK_EVENT:
2167 			break;
2168 		default:
2169 			if (msg->rc)
2170 				dev_err(rvu->dev,
2171 					"Mbox msg response has err %d, ID 0x%x\n",
2172 					msg->rc, msg->id);
2173 			break;
2174 		}
2175 end:
2176 		offset = mbox->rx_start + msg->next_msgoff;
2177 		mdev->msgs_acked++;
2178 	}
2179 	mw->mbox_wrk_up[devid].up_num_msgs = 0;
2180 
2181 	otx2_mbox_reset(mbox, devid);
2182 }
2183 
rvu_afpf_mbox_up_handler(struct work_struct * work)2184 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
2185 {
2186 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2187 
2188 	__rvu_mbox_up_handler(mwork, TYPE_AFPF);
2189 }
2190 
rvu_afvf_mbox_up_handler(struct work_struct * work)2191 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
2192 {
2193 	struct rvu_work *mwork = container_of(work, struct rvu_work, work);
2194 
2195 	__rvu_mbox_up_handler(mwork, TYPE_AFVF);
2196 }
2197 
rvu_get_mbox_regions(struct rvu * rvu,void ** mbox_addr,int num,int type,unsigned long * pf_bmap)2198 static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr,
2199 				int num, int type, unsigned long *pf_bmap)
2200 {
2201 	struct rvu_hwinfo *hw = rvu->hw;
2202 	int region;
2203 	u64 bar4;
2204 
2205 	/* For cn10k platform VF mailbox regions of a PF follows after the
2206 	 * PF <-> AF mailbox region. Whereas for Octeontx2 it is read from
2207 	 * RVU_PF_VF_BAR4_ADDR register.
2208 	 */
2209 	if (type == TYPE_AFVF) {
2210 		for (region = 0; region < num; region++) {
2211 			if (!test_bit(region, pf_bmap))
2212 				continue;
2213 
2214 			if (hw->cap.per_pf_mbox_regs) {
2215 				bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2216 						  RVU_AF_PFX_BAR4_ADDR(0)) +
2217 						  MBOX_SIZE;
2218 				bar4 += region * MBOX_SIZE;
2219 			} else {
2220 				bar4 = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
2221 				bar4 += region * MBOX_SIZE;
2222 			}
2223 			mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2224 			if (!mbox_addr[region])
2225 				goto error;
2226 		}
2227 		return 0;
2228 	}
2229 
2230 	/* For cn10k platform AF <-> PF mailbox region of a PF is read from per
2231 	 * PF registers. Whereas for Octeontx2 it is read from
2232 	 * RVU_AF_PF_BAR4_ADDR register.
2233 	 */
2234 	for (region = 0; region < num; region++) {
2235 		if (!test_bit(region, pf_bmap))
2236 			continue;
2237 
2238 		if (hw->cap.per_pf_mbox_regs) {
2239 			bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2240 					  RVU_AF_PFX_BAR4_ADDR(region));
2241 		} else {
2242 			bar4 = rvu_read64(rvu, BLKADDR_RVUM,
2243 					  RVU_AF_PF_BAR4_ADDR);
2244 			bar4 += region * MBOX_SIZE;
2245 		}
2246 		mbox_addr[region] = (void *)ioremap_wc(bar4, MBOX_SIZE);
2247 		if (!mbox_addr[region])
2248 			goto error;
2249 	}
2250 	return 0;
2251 
2252 error:
2253 	while (region--)
2254 		iounmap((void __iomem *)mbox_addr[region]);
2255 	return -ENOMEM;
2256 }
2257 
rvu_mbox_init(struct rvu * rvu,struct mbox_wq_info * mw,int type,int num,void (mbox_handler)(struct work_struct *),void (mbox_up_handler)(struct work_struct *))2258 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2259 			 int type, int num,
2260 			 void (mbox_handler)(struct work_struct *),
2261 			 void (mbox_up_handler)(struct work_struct *))
2262 {
2263 	int err = -EINVAL, i, dir, dir_up;
2264 	void __iomem *reg_base;
2265 	struct rvu_work *mwork;
2266 	unsigned long *pf_bmap;
2267 	void **mbox_regions;
2268 	const char *name;
2269 	u64 cfg;
2270 
2271 	pf_bmap = bitmap_zalloc(num, GFP_KERNEL);
2272 	if (!pf_bmap)
2273 		return -ENOMEM;
2274 
2275 	/* RVU VFs */
2276 	if (type == TYPE_AFVF)
2277 		bitmap_set(pf_bmap, 0, num);
2278 
2279 	if (type == TYPE_AFPF) {
2280 		/* Mark enabled PFs in bitmap */
2281 		for (i = 0; i < num; i++) {
2282 			cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(i));
2283 			if (cfg & BIT_ULL(20))
2284 				set_bit(i, pf_bmap);
2285 		}
2286 	}
2287 
2288 	mbox_regions = kcalloc(num, sizeof(void *), GFP_KERNEL);
2289 	if (!mbox_regions) {
2290 		err = -ENOMEM;
2291 		goto free_bitmap;
2292 	}
2293 
2294 	switch (type) {
2295 	case TYPE_AFPF:
2296 		name = "rvu_afpf_mailbox";
2297 		dir = MBOX_DIR_AFPF;
2298 		dir_up = MBOX_DIR_AFPF_UP;
2299 		reg_base = rvu->afreg_base;
2300 		err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFPF, pf_bmap);
2301 		if (err)
2302 			goto free_regions;
2303 		break;
2304 	case TYPE_AFVF:
2305 		name = "rvu_afvf_mailbox";
2306 		dir = MBOX_DIR_PFVF;
2307 		dir_up = MBOX_DIR_PFVF_UP;
2308 		reg_base = rvu->pfreg_base;
2309 		err = rvu_get_mbox_regions(rvu, mbox_regions, num, TYPE_AFVF, pf_bmap);
2310 		if (err)
2311 			goto free_regions;
2312 		break;
2313 	default:
2314 		goto free_regions;
2315 	}
2316 
2317 	mw->mbox_wq = alloc_workqueue(name,
2318 				      WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2319 				      num);
2320 	if (!mw->mbox_wq) {
2321 		err = -ENOMEM;
2322 		goto unmap_regions;
2323 	}
2324 
2325 	mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
2326 				    sizeof(struct rvu_work), GFP_KERNEL);
2327 	if (!mw->mbox_wrk) {
2328 		err = -ENOMEM;
2329 		goto exit;
2330 	}
2331 
2332 	mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
2333 				       sizeof(struct rvu_work), GFP_KERNEL);
2334 	if (!mw->mbox_wrk_up) {
2335 		err = -ENOMEM;
2336 		goto exit;
2337 	}
2338 
2339 	err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev,
2340 				     reg_base, dir, num, pf_bmap);
2341 	if (err)
2342 		goto exit;
2343 
2344 	err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev,
2345 				     reg_base, dir_up, num, pf_bmap);
2346 	if (err)
2347 		goto exit;
2348 
2349 	for (i = 0; i < num; i++) {
2350 		if (!test_bit(i, pf_bmap))
2351 			continue;
2352 
2353 		mwork = &mw->mbox_wrk[i];
2354 		mwork->rvu = rvu;
2355 		INIT_WORK(&mwork->work, mbox_handler);
2356 
2357 		mwork = &mw->mbox_wrk_up[i];
2358 		mwork->rvu = rvu;
2359 		INIT_WORK(&mwork->work, mbox_up_handler);
2360 	}
2361 	goto free_regions;
2362 
2363 exit:
2364 	destroy_workqueue(mw->mbox_wq);
2365 unmap_regions:
2366 	while (num--)
2367 		iounmap((void __iomem *)mbox_regions[num]);
2368 free_regions:
2369 	kfree(mbox_regions);
2370 free_bitmap:
2371 	bitmap_free(pf_bmap);
2372 	return err;
2373 }
2374 
rvu_mbox_destroy(struct mbox_wq_info * mw)2375 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
2376 {
2377 	struct otx2_mbox *mbox = &mw->mbox;
2378 	struct otx2_mbox_dev *mdev;
2379 	int devid;
2380 
2381 	if (mw->mbox_wq) {
2382 		flush_workqueue(mw->mbox_wq);
2383 		destroy_workqueue(mw->mbox_wq);
2384 		mw->mbox_wq = NULL;
2385 	}
2386 
2387 	for (devid = 0; devid < mbox->ndevs; devid++) {
2388 		mdev = &mbox->dev[devid];
2389 		if (mdev->hwbase)
2390 			iounmap((void __iomem *)mdev->hwbase);
2391 	}
2392 
2393 	otx2_mbox_destroy(&mw->mbox);
2394 	otx2_mbox_destroy(&mw->mbox_up);
2395 }
2396 
rvu_queue_work(struct mbox_wq_info * mw,int first,int mdevs,u64 intr)2397 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
2398 			   int mdevs, u64 intr)
2399 {
2400 	struct otx2_mbox_dev *mdev;
2401 	struct otx2_mbox *mbox;
2402 	struct mbox_hdr *hdr;
2403 	int i;
2404 
2405 	for (i = first; i < mdevs; i++) {
2406 		/* start from 0 */
2407 		if (!(intr & BIT_ULL(i - first)))
2408 			continue;
2409 
2410 		mbox = &mw->mbox;
2411 		mdev = &mbox->dev[i];
2412 		hdr = mdev->mbase + mbox->rx_start;
2413 
2414 		/*The hdr->num_msgs is set to zero immediately in the interrupt
2415 		 * handler to  ensure that it holds a correct value next time
2416 		 * when the interrupt handler is called.
2417 		 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
2418 		 * pf>mbox.up_num_msgs holds the data for use in
2419 		 * pfaf_mbox_up_handler.
2420 		 */
2421 
2422 		if (hdr->num_msgs) {
2423 			mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
2424 			hdr->num_msgs = 0;
2425 			queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
2426 		}
2427 		mbox = &mw->mbox_up;
2428 		mdev = &mbox->dev[i];
2429 		hdr = mdev->mbase + mbox->rx_start;
2430 		if (hdr->num_msgs) {
2431 			mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
2432 			hdr->num_msgs = 0;
2433 			queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
2434 		}
2435 	}
2436 }
2437 
rvu_mbox_intr_handler(int irq,void * rvu_irq)2438 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
2439 {
2440 	struct rvu *rvu = (struct rvu *)rvu_irq;
2441 	int vfs = rvu->vfs;
2442 	u64 intr;
2443 
2444 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
2445 	/* Clear interrupts */
2446 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
2447 	if (intr)
2448 		trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
2449 
2450 	/* Sync with mbox memory region */
2451 	rmb();
2452 
2453 	rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
2454 
2455 	/* Handle VF interrupts */
2456 	if (vfs > 64) {
2457 		intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
2458 		rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
2459 
2460 		rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
2461 		vfs -= 64;
2462 	}
2463 
2464 	intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
2465 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
2466 	if (intr)
2467 		trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
2468 
2469 	rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
2470 
2471 	return IRQ_HANDLED;
2472 }
2473 
rvu_enable_mbox_intr(struct rvu * rvu)2474 static void rvu_enable_mbox_intr(struct rvu *rvu)
2475 {
2476 	struct rvu_hwinfo *hw = rvu->hw;
2477 
2478 	/* Clear spurious irqs, if any */
2479 	rvu_write64(rvu, BLKADDR_RVUM,
2480 		    RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
2481 
2482 	/* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
2483 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
2484 		    INTR_MASK(hw->total_pfs) & ~1ULL);
2485 }
2486 
rvu_blklf_teardown(struct rvu * rvu,u16 pcifunc,u8 blkaddr)2487 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
2488 {
2489 	struct rvu_block *block;
2490 	int slot, lf, num_lfs;
2491 	int err;
2492 
2493 	block = &rvu->hw->block[blkaddr];
2494 	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
2495 					block->addr);
2496 	if (!num_lfs)
2497 		return;
2498 	for (slot = 0; slot < num_lfs; slot++) {
2499 		lf = rvu_get_lf(rvu, block, pcifunc, slot);
2500 		if (lf < 0)
2501 			continue;
2502 
2503 		/* Cleanup LF and reset it */
2504 		if (block->addr == BLKADDR_NIX0 || block->addr == BLKADDR_NIX1)
2505 			rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
2506 		else if (block->addr == BLKADDR_NPA)
2507 			rvu_npa_lf_teardown(rvu, pcifunc, lf);
2508 		else if ((block->addr == BLKADDR_CPT0) ||
2509 			 (block->addr == BLKADDR_CPT1))
2510 			rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot);
2511 
2512 		err = rvu_lf_reset(rvu, block, lf);
2513 		if (err) {
2514 			dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
2515 				block->addr, lf);
2516 		}
2517 	}
2518 }
2519 
__rvu_flr_handler(struct rvu * rvu,u16 pcifunc)2520 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
2521 {
2522 	mutex_lock(&rvu->flr_lock);
2523 	/* Reset order should reflect inter-block dependencies:
2524 	 * 1. Reset any packet/work sources (NIX, CPT, TIM)
2525 	 * 2. Flush and reset SSO/SSOW
2526 	 * 3. Cleanup pools (NPA)
2527 	 */
2528 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
2529 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX1);
2530 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
2531 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT1);
2532 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
2533 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
2534 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
2535 	rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
2536 	rvu_reset_lmt_map_tbl(rvu, pcifunc);
2537 	rvu_detach_rsrcs(rvu, NULL, pcifunc);
2538 	/* In scenarios where PF/VF drivers detach NIXLF without freeing MCAM
2539 	 * entries, check and free the MCAM entries explicitly to avoid leak.
2540 	 * Since LF is detached use LF number as -1.
2541 	 */
2542 	rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
2543 
2544 	mutex_unlock(&rvu->flr_lock);
2545 }
2546 
rvu_afvf_flr_handler(struct rvu * rvu,int vf)2547 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
2548 {
2549 	int reg = 0;
2550 
2551 	/* pcifunc = 0(PF0) | (vf + 1) */
2552 	__rvu_flr_handler(rvu, vf + 1);
2553 
2554 	if (vf >= 64) {
2555 		reg = 1;
2556 		vf = vf - 64;
2557 	}
2558 
2559 	/* Signal FLR finish and enable IRQ */
2560 	rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
2561 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
2562 }
2563 
rvu_flr_handler(struct work_struct * work)2564 static void rvu_flr_handler(struct work_struct *work)
2565 {
2566 	struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
2567 	struct rvu *rvu = flrwork->rvu;
2568 	u16 pcifunc, numvfs, vf;
2569 	u64 cfg;
2570 	int pf;
2571 
2572 	pf = flrwork - rvu->flr_wrk;
2573 	if (pf >= rvu->hw->total_pfs) {
2574 		rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2575 		return;
2576 	}
2577 
2578 	cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2579 	numvfs = (cfg >> 12) & 0xFF;
2580 	pcifunc  = pf << RVU_PFVF_PF_SHIFT;
2581 
2582 	for (vf = 0; vf < numvfs; vf++)
2583 		__rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2584 
2585 	__rvu_flr_handler(rvu, pcifunc);
2586 
2587 	/* Signal FLR finish */
2588 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2589 
2590 	/* Enable interrupt */
2591 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,  BIT_ULL(pf));
2592 }
2593 
rvu_afvf_queue_flr_work(struct rvu * rvu,int start_vf,int numvfs)2594 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2595 {
2596 	int dev, vf, reg = 0;
2597 	u64 intr;
2598 
2599 	if (start_vf >= 64)
2600 		reg = 1;
2601 
2602 	intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2603 	if (!intr)
2604 		return;
2605 
2606 	for (vf = 0; vf < numvfs; vf++) {
2607 		if (!(intr & BIT_ULL(vf)))
2608 			continue;
2609 		/* Clear and disable the interrupt */
2610 		rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2611 		rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2612 
2613 		dev = vf + start_vf + rvu->hw->total_pfs;
2614 		queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2615 	}
2616 }
2617 
rvu_flr_intr_handler(int irq,void * rvu_irq)2618 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2619 {
2620 	struct rvu *rvu = (struct rvu *)rvu_irq;
2621 	u64 intr;
2622 	u8  pf;
2623 
2624 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2625 	if (!intr)
2626 		goto afvf_flr;
2627 
2628 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2629 		if (intr & (1ULL << pf)) {
2630 			/* clear interrupt */
2631 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2632 				    BIT_ULL(pf));
2633 			/* Disable the interrupt */
2634 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2635 				    BIT_ULL(pf));
2636 			/* PF is already dead do only AF related operations */
2637 			queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2638 		}
2639 	}
2640 
2641 afvf_flr:
2642 	rvu_afvf_queue_flr_work(rvu, 0, 64);
2643 	if (rvu->vfs > 64)
2644 		rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2645 
2646 	return IRQ_HANDLED;
2647 }
2648 
rvu_me_handle_vfset(struct rvu * rvu,int idx,u64 intr)2649 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2650 {
2651 	int vf;
2652 
2653 	/* Nothing to be done here other than clearing the
2654 	 * TRPEND bit.
2655 	 */
2656 	for (vf = 0; vf < 64; vf++) {
2657 		if (intr & (1ULL << vf)) {
2658 			/* clear the trpend due to ME(master enable) */
2659 			rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2660 			/* clear interrupt */
2661 			rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2662 		}
2663 	}
2664 }
2665 
2666 /* Handles ME interrupts from VFs of AF */
rvu_me_vf_intr_handler(int irq,void * rvu_irq)2667 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2668 {
2669 	struct rvu *rvu = (struct rvu *)rvu_irq;
2670 	int vfset;
2671 	u64 intr;
2672 
2673 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2674 
2675 	for (vfset = 0; vfset <= 1; vfset++) {
2676 		intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2677 		if (intr)
2678 			rvu_me_handle_vfset(rvu, vfset, intr);
2679 	}
2680 
2681 	return IRQ_HANDLED;
2682 }
2683 
2684 /* Handles ME interrupts from PFs */
rvu_me_pf_intr_handler(int irq,void * rvu_irq)2685 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2686 {
2687 	struct rvu *rvu = (struct rvu *)rvu_irq;
2688 	u64 intr;
2689 	u8  pf;
2690 
2691 	intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2692 
2693 	/* Nothing to be done here other than clearing the
2694 	 * TRPEND bit.
2695 	 */
2696 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2697 		if (intr & (1ULL << pf)) {
2698 			/* clear the trpend due to ME(master enable) */
2699 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2700 				    BIT_ULL(pf));
2701 			/* clear interrupt */
2702 			rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2703 				    BIT_ULL(pf));
2704 		}
2705 	}
2706 
2707 	return IRQ_HANDLED;
2708 }
2709 
rvu_unregister_interrupts(struct rvu * rvu)2710 static void rvu_unregister_interrupts(struct rvu *rvu)
2711 {
2712 	int irq;
2713 
2714 	/* Disable the Mbox interrupt */
2715 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2716 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2717 
2718 	/* Disable the PF FLR interrupt */
2719 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2720 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2721 
2722 	/* Disable the PF ME interrupt */
2723 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2724 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2725 
2726 	for (irq = 0; irq < rvu->num_vec; irq++) {
2727 		if (rvu->irq_allocated[irq]) {
2728 			free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2729 			rvu->irq_allocated[irq] = false;
2730 		}
2731 	}
2732 
2733 	pci_free_irq_vectors(rvu->pdev);
2734 	rvu->num_vec = 0;
2735 }
2736 
rvu_afvf_msix_vectors_num_ok(struct rvu * rvu)2737 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2738 {
2739 	struct rvu_pfvf *pfvf = &rvu->pf[0];
2740 	int offset;
2741 
2742 	pfvf = &rvu->pf[0];
2743 	offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2744 
2745 	/* Make sure there are enough MSIX vectors configured so that
2746 	 * VF interrupts can be handled. Offset equal to zero means
2747 	 * that PF vectors are not configured and overlapping AF vectors.
2748 	 */
2749 	return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2750 	       offset;
2751 }
2752 
rvu_register_interrupts(struct rvu * rvu)2753 static int rvu_register_interrupts(struct rvu *rvu)
2754 {
2755 	int ret, offset, pf_vec_start;
2756 
2757 	rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2758 
2759 	rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2760 					   NAME_SIZE, GFP_KERNEL);
2761 	if (!rvu->irq_name)
2762 		return -ENOMEM;
2763 
2764 	rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2765 					  sizeof(bool), GFP_KERNEL);
2766 	if (!rvu->irq_allocated)
2767 		return -ENOMEM;
2768 
2769 	/* Enable MSI-X */
2770 	ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2771 				    rvu->num_vec, PCI_IRQ_MSIX);
2772 	if (ret < 0) {
2773 		dev_err(rvu->dev,
2774 			"RVUAF: Request for %d msix vectors failed, ret %d\n",
2775 			rvu->num_vec, ret);
2776 		return ret;
2777 	}
2778 
2779 	/* Register mailbox interrupt handler */
2780 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2781 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2782 			  rvu_mbox_intr_handler, 0,
2783 			  &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2784 	if (ret) {
2785 		dev_err(rvu->dev,
2786 			"RVUAF: IRQ registration failed for mbox irq\n");
2787 		goto fail;
2788 	}
2789 
2790 	rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2791 
2792 	/* Enable mailbox interrupts from all PFs */
2793 	rvu_enable_mbox_intr(rvu);
2794 
2795 	/* Register FLR interrupt handler */
2796 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2797 		"RVUAF FLR");
2798 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2799 			  rvu_flr_intr_handler, 0,
2800 			  &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2801 			  rvu);
2802 	if (ret) {
2803 		dev_err(rvu->dev,
2804 			"RVUAF: IRQ registration failed for FLR\n");
2805 		goto fail;
2806 	}
2807 	rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2808 
2809 	/* Enable FLR interrupt for all PFs*/
2810 	rvu_write64(rvu, BLKADDR_RVUM,
2811 		    RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2812 
2813 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2814 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2815 
2816 	/* Register ME interrupt handler */
2817 	sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2818 		"RVUAF ME");
2819 	ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2820 			  rvu_me_pf_intr_handler, 0,
2821 			  &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2822 			  rvu);
2823 	if (ret) {
2824 		dev_err(rvu->dev,
2825 			"RVUAF: IRQ registration failed for ME\n");
2826 	}
2827 	rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2828 
2829 	/* Clear TRPEND bit for all PF */
2830 	rvu_write64(rvu, BLKADDR_RVUM,
2831 		    RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2832 	/* Enable ME interrupt for all PFs*/
2833 	rvu_write64(rvu, BLKADDR_RVUM,
2834 		    RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2835 
2836 	rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2837 		    INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2838 
2839 	if (!rvu_afvf_msix_vectors_num_ok(rvu))
2840 		return 0;
2841 
2842 	/* Get PF MSIX vectors offset. */
2843 	pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2844 				  RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2845 
2846 	/* Register MBOX0 interrupt. */
2847 	offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2848 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2849 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2850 			  rvu_mbox_intr_handler, 0,
2851 			  &rvu->irq_name[offset * NAME_SIZE],
2852 			  rvu);
2853 	if (ret)
2854 		dev_err(rvu->dev,
2855 			"RVUAF: IRQ registration failed for Mbox0\n");
2856 
2857 	rvu->irq_allocated[offset] = true;
2858 
2859 	/* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2860 	 * simply increment current offset by 1.
2861 	 */
2862 	offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2863 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2864 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2865 			  rvu_mbox_intr_handler, 0,
2866 			  &rvu->irq_name[offset * NAME_SIZE],
2867 			  rvu);
2868 	if (ret)
2869 		dev_err(rvu->dev,
2870 			"RVUAF: IRQ registration failed for Mbox1\n");
2871 
2872 	rvu->irq_allocated[offset] = true;
2873 
2874 	/* Register FLR interrupt handler for AF's VFs */
2875 	offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2876 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2877 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2878 			  rvu_flr_intr_handler, 0,
2879 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2880 	if (ret) {
2881 		dev_err(rvu->dev,
2882 			"RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2883 		goto fail;
2884 	}
2885 	rvu->irq_allocated[offset] = true;
2886 
2887 	offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2888 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2889 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2890 			  rvu_flr_intr_handler, 0,
2891 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2892 	if (ret) {
2893 		dev_err(rvu->dev,
2894 			"RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2895 		goto fail;
2896 	}
2897 	rvu->irq_allocated[offset] = true;
2898 
2899 	/* Register ME interrupt handler for AF's VFs */
2900 	offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
2901 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
2902 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2903 			  rvu_me_vf_intr_handler, 0,
2904 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2905 	if (ret) {
2906 		dev_err(rvu->dev,
2907 			"RVUAF: IRQ registration failed for RVUAFVF ME0\n");
2908 		goto fail;
2909 	}
2910 	rvu->irq_allocated[offset] = true;
2911 
2912 	offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
2913 	sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
2914 	ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2915 			  rvu_me_vf_intr_handler, 0,
2916 			  &rvu->irq_name[offset * NAME_SIZE], rvu);
2917 	if (ret) {
2918 		dev_err(rvu->dev,
2919 			"RVUAF: IRQ registration failed for RVUAFVF ME1\n");
2920 		goto fail;
2921 	}
2922 	rvu->irq_allocated[offset] = true;
2923 	return 0;
2924 
2925 fail:
2926 	rvu_unregister_interrupts(rvu);
2927 	return ret;
2928 }
2929 
rvu_flr_wq_destroy(struct rvu * rvu)2930 static void rvu_flr_wq_destroy(struct rvu *rvu)
2931 {
2932 	if (rvu->flr_wq) {
2933 		flush_workqueue(rvu->flr_wq);
2934 		destroy_workqueue(rvu->flr_wq);
2935 		rvu->flr_wq = NULL;
2936 	}
2937 }
2938 
rvu_flr_init(struct rvu * rvu)2939 static int rvu_flr_init(struct rvu *rvu)
2940 {
2941 	int dev, num_devs;
2942 	u64 cfg;
2943 	int pf;
2944 
2945 	/* Enable FLR for all PFs*/
2946 	for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2947 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2948 		rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
2949 			    cfg | BIT_ULL(22));
2950 	}
2951 
2952 	rvu->flr_wq = alloc_workqueue("rvu_afpf_flr",
2953 				      WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2954 				       1);
2955 	if (!rvu->flr_wq)
2956 		return -ENOMEM;
2957 
2958 	num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
2959 	rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
2960 				    sizeof(struct rvu_work), GFP_KERNEL);
2961 	if (!rvu->flr_wrk) {
2962 		destroy_workqueue(rvu->flr_wq);
2963 		return -ENOMEM;
2964 	}
2965 
2966 	for (dev = 0; dev < num_devs; dev++) {
2967 		rvu->flr_wrk[dev].rvu = rvu;
2968 		INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
2969 	}
2970 
2971 	mutex_init(&rvu->flr_lock);
2972 
2973 	return 0;
2974 }
2975 
rvu_disable_afvf_intr(struct rvu * rvu)2976 static void rvu_disable_afvf_intr(struct rvu *rvu)
2977 {
2978 	int vfs = rvu->vfs;
2979 
2980 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
2981 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
2982 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
2983 	if (vfs <= 64)
2984 		return;
2985 
2986 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
2987 		      INTR_MASK(vfs - 64));
2988 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2989 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2990 }
2991 
rvu_enable_afvf_intr(struct rvu * rvu)2992 static void rvu_enable_afvf_intr(struct rvu *rvu)
2993 {
2994 	int vfs = rvu->vfs;
2995 
2996 	/* Clear any pending interrupts and enable AF VF interrupts for
2997 	 * the first 64 VFs.
2998 	 */
2999 	/* Mbox */
3000 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
3001 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
3002 
3003 	/* FLR */
3004 	rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
3005 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
3006 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
3007 
3008 	/* Same for remaining VFs, if any. */
3009 	if (vfs <= 64)
3010 		return;
3011 
3012 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
3013 	rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
3014 		      INTR_MASK(vfs - 64));
3015 
3016 	rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
3017 	rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3018 	rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
3019 }
3020 
rvu_get_num_lbk_chans(void)3021 int rvu_get_num_lbk_chans(void)
3022 {
3023 	struct pci_dev *pdev;
3024 	void __iomem *base;
3025 	int ret = -EIO;
3026 
3027 	pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
3028 			      NULL);
3029 	if (!pdev)
3030 		goto err;
3031 
3032 	base = pci_ioremap_bar(pdev, 0);
3033 	if (!base)
3034 		goto err_put;
3035 
3036 	/* Read number of available LBK channels from LBK(0)_CONST register. */
3037 	ret = (readq(base + 0x10) >> 32) & 0xffff;
3038 	iounmap(base);
3039 err_put:
3040 	pci_dev_put(pdev);
3041 err:
3042 	return ret;
3043 }
3044 
rvu_enable_sriov(struct rvu * rvu)3045 static int rvu_enable_sriov(struct rvu *rvu)
3046 {
3047 	struct pci_dev *pdev = rvu->pdev;
3048 	int err, chans, vfs;
3049 
3050 	if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
3051 		dev_warn(&pdev->dev,
3052 			 "Skipping SRIOV enablement since not enough IRQs are available\n");
3053 		return 0;
3054 	}
3055 
3056 	chans = rvu_get_num_lbk_chans();
3057 	if (chans < 0)
3058 		return chans;
3059 
3060 	vfs = pci_sriov_get_totalvfs(pdev);
3061 
3062 	/* Limit VFs in case we have more VFs than LBK channels available. */
3063 	if (vfs > chans)
3064 		vfs = chans;
3065 
3066 	if (!vfs)
3067 		return 0;
3068 
3069 	/* LBK channel number 63 is used for switching packets between
3070 	 * CGX mapped VFs. Hence limit LBK pairs till 62 only.
3071 	 */
3072 	if (vfs > 62)
3073 		vfs = 62;
3074 
3075 	/* Save VFs number for reference in VF interrupts handlers.
3076 	 * Since interrupts might start arriving during SRIOV enablement
3077 	 * ordinary API cannot be used to get number of enabled VFs.
3078 	 */
3079 	rvu->vfs = vfs;
3080 
3081 	err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
3082 			    rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
3083 	if (err)
3084 		return err;
3085 
3086 	rvu_enable_afvf_intr(rvu);
3087 	/* Make sure IRQs are enabled before SRIOV. */
3088 	mb();
3089 
3090 	err = pci_enable_sriov(pdev, vfs);
3091 	if (err) {
3092 		rvu_disable_afvf_intr(rvu);
3093 		rvu_mbox_destroy(&rvu->afvf_wq_info);
3094 		return err;
3095 	}
3096 
3097 	return 0;
3098 }
3099 
rvu_disable_sriov(struct rvu * rvu)3100 static void rvu_disable_sriov(struct rvu *rvu)
3101 {
3102 	rvu_disable_afvf_intr(rvu);
3103 	rvu_mbox_destroy(&rvu->afvf_wq_info);
3104 	pci_disable_sriov(rvu->pdev);
3105 }
3106 
rvu_update_module_params(struct rvu * rvu)3107 static void rvu_update_module_params(struct rvu *rvu)
3108 {
3109 	const char *default_pfl_name = "default";
3110 
3111 	strscpy(rvu->mkex_pfl_name,
3112 		mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
3113 	strscpy(rvu->kpu_pfl_name,
3114 		kpu_profile ? kpu_profile : default_pfl_name, KPU_NAME_LEN);
3115 }
3116 
rvu_probe(struct pci_dev * pdev,const struct pci_device_id * id)3117 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3118 {
3119 	struct device *dev = &pdev->dev;
3120 	struct rvu *rvu;
3121 	int    err;
3122 
3123 	rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
3124 	if (!rvu)
3125 		return -ENOMEM;
3126 
3127 	rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
3128 	if (!rvu->hw) {
3129 		devm_kfree(dev, rvu);
3130 		return -ENOMEM;
3131 	}
3132 
3133 	pci_set_drvdata(pdev, rvu);
3134 	rvu->pdev = pdev;
3135 	rvu->dev = &pdev->dev;
3136 
3137 	err = pci_enable_device(pdev);
3138 	if (err) {
3139 		dev_err(dev, "Failed to enable PCI device\n");
3140 		goto err_freemem;
3141 	}
3142 
3143 	err = pci_request_regions(pdev, DRV_NAME);
3144 	if (err) {
3145 		dev_err(dev, "PCI request regions failed 0x%x\n", err);
3146 		goto err_disable_device;
3147 	}
3148 
3149 	err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
3150 	if (err) {
3151 		dev_err(dev, "DMA mask config failed, abort\n");
3152 		goto err_release_regions;
3153 	}
3154 
3155 	pci_set_master(pdev);
3156 
3157 	rvu->ptp = ptp_get();
3158 	if (IS_ERR(rvu->ptp)) {
3159 		err = PTR_ERR(rvu->ptp);
3160 		if (err == -EPROBE_DEFER)
3161 			goto err_release_regions;
3162 		rvu->ptp = NULL;
3163 	}
3164 
3165 	/* Map Admin function CSRs */
3166 	rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
3167 	rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
3168 	if (!rvu->afreg_base || !rvu->pfreg_base) {
3169 		dev_err(dev, "Unable to map admin function CSRs, aborting\n");
3170 		err = -ENOMEM;
3171 		goto err_put_ptp;
3172 	}
3173 
3174 	/* Store module params in rvu structure */
3175 	rvu_update_module_params(rvu);
3176 
3177 	/* Check which blocks the HW supports */
3178 	rvu_check_block_implemented(rvu);
3179 
3180 	rvu_reset_all_blocks(rvu);
3181 
3182 	rvu_setup_hw_capabilities(rvu);
3183 
3184 	err = rvu_setup_hw_resources(rvu);
3185 	if (err)
3186 		goto err_put_ptp;
3187 
3188 	/* Init mailbox btw AF and PFs */
3189 	err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
3190 			    rvu->hw->total_pfs, rvu_afpf_mbox_handler,
3191 			    rvu_afpf_mbox_up_handler);
3192 	if (err) {
3193 		dev_err(dev, "%s: Failed to initialize mbox\n", __func__);
3194 		goto err_hwsetup;
3195 	}
3196 
3197 	err = rvu_flr_init(rvu);
3198 	if (err) {
3199 		dev_err(dev, "%s: Failed to initialize flr\n", __func__);
3200 		goto err_mbox;
3201 	}
3202 
3203 	err = rvu_register_interrupts(rvu);
3204 	if (err) {
3205 		dev_err(dev, "%s: Failed to register interrupts\n", __func__);
3206 		goto err_flr;
3207 	}
3208 
3209 	err = rvu_register_dl(rvu);
3210 	if (err) {
3211 		dev_err(dev, "%s: Failed to register devlink\n", __func__);
3212 		goto err_irq;
3213 	}
3214 
3215 	rvu_setup_rvum_blk_revid(rvu);
3216 
3217 	/* Enable AF's VFs (if any) */
3218 	err = rvu_enable_sriov(rvu);
3219 	if (err) {
3220 		dev_err(dev, "%s: Failed to enable sriov\n", __func__);
3221 		goto err_dl;
3222 	}
3223 
3224 	/* Initialize debugfs */
3225 	rvu_dbg_init(rvu);
3226 
3227 	mutex_init(&rvu->rswitch.switch_lock);
3228 
3229 	return 0;
3230 err_dl:
3231 	rvu_unregister_dl(rvu);
3232 err_irq:
3233 	rvu_unregister_interrupts(rvu);
3234 err_flr:
3235 	rvu_flr_wq_destroy(rvu);
3236 err_mbox:
3237 	rvu_mbox_destroy(&rvu->afpf_wq_info);
3238 err_hwsetup:
3239 	rvu_cgx_exit(rvu);
3240 	rvu_fwdata_exit(rvu);
3241 	rvu_reset_all_blocks(rvu);
3242 	rvu_free_hw_resources(rvu);
3243 	rvu_clear_rvum_blk_revid(rvu);
3244 err_put_ptp:
3245 	ptp_put(rvu->ptp);
3246 err_release_regions:
3247 	pci_release_regions(pdev);
3248 err_disable_device:
3249 	pci_disable_device(pdev);
3250 err_freemem:
3251 	pci_set_drvdata(pdev, NULL);
3252 	devm_kfree(&pdev->dev, rvu->hw);
3253 	devm_kfree(dev, rvu);
3254 	return err;
3255 }
3256 
rvu_remove(struct pci_dev * pdev)3257 static void rvu_remove(struct pci_dev *pdev)
3258 {
3259 	struct rvu *rvu = pci_get_drvdata(pdev);
3260 
3261 	rvu_dbg_exit(rvu);
3262 	rvu_unregister_dl(rvu);
3263 	rvu_unregister_interrupts(rvu);
3264 	rvu_flr_wq_destroy(rvu);
3265 	rvu_cgx_exit(rvu);
3266 	rvu_fwdata_exit(rvu);
3267 	rvu_mbox_destroy(&rvu->afpf_wq_info);
3268 	rvu_disable_sriov(rvu);
3269 	rvu_reset_all_blocks(rvu);
3270 	rvu_free_hw_resources(rvu);
3271 	rvu_clear_rvum_blk_revid(rvu);
3272 	ptp_put(rvu->ptp);
3273 	pci_release_regions(pdev);
3274 	pci_disable_device(pdev);
3275 	pci_set_drvdata(pdev, NULL);
3276 
3277 	devm_kfree(&pdev->dev, rvu->hw);
3278 	devm_kfree(&pdev->dev, rvu);
3279 }
3280 
3281 static struct pci_driver rvu_driver = {
3282 	.name = DRV_NAME,
3283 	.id_table = rvu_id_table,
3284 	.probe = rvu_probe,
3285 	.remove = rvu_remove,
3286 };
3287 
rvu_init_module(void)3288 static int __init rvu_init_module(void)
3289 {
3290 	int err;
3291 
3292 	pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
3293 
3294 	err = pci_register_driver(&cgx_driver);
3295 	if (err < 0)
3296 		return err;
3297 
3298 	err = pci_register_driver(&ptp_driver);
3299 	if (err < 0)
3300 		goto ptp_err;
3301 
3302 	err =  pci_register_driver(&rvu_driver);
3303 	if (err < 0)
3304 		goto rvu_err;
3305 
3306 	return 0;
3307 rvu_err:
3308 	pci_unregister_driver(&ptp_driver);
3309 ptp_err:
3310 	pci_unregister_driver(&cgx_driver);
3311 
3312 	return err;
3313 }
3314 
rvu_cleanup_module(void)3315 static void __exit rvu_cleanup_module(void)
3316 {
3317 	pci_unregister_driver(&rvu_driver);
3318 	pci_unregister_driver(&ptp_driver);
3319 	pci_unregister_driver(&cgx_driver);
3320 }
3321 
3322 module_init(rvu_init_module);
3323 module_exit(rvu_cleanup_module);
3324