1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62
63 extern const struct net_device_ops mlx5e_netdev_ops;
64 struct page_pool;
65
66 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
67 #define MLX5E_METADATA_ETHER_LEN 8
68
69 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
70
71 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
72 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
73
74 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
76
77 #define MLX5_RX_HEADROOM NET_SKB_PAD
78 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
79 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80
81 #define MLX5E_RX_MAX_HEAD (256)
82
83 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
84 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
85 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
86 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
87 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
88 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
89
90 #define MLX5_MPWRQ_LOG_WQE_SZ 18
91 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
92 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
93 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94
95 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
96 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
97 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
98 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
99 * WQEs, This page will absorb write overflow by the hardware, when
100 * receiving packets larger than MTU. These oversize packets are
101 * dropped by the driver at a later stage.
102 */
103 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
104 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
105 #define MLX5E_MAX_RQ_NUM_MTTS \
106 (ALIGN_DOWN(U16_MAX, 4) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
107 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
108 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
109 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
110 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
111 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
112 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
113
114 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
115 #define MLX5E_LOG_MAX_RX_WQE_BULK \
116 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
117
118 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
119 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
120 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
121
122 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
123 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
124 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
125 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
126
127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
128
129 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
130 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
131
132 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
135 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
138 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
140
141 #define MLX5E_MIN_NUM_CHANNELS 0x1
142 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2)
143 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
144 #define MLX5E_TX_CQ_POLL_BUDGET 128
145 #define MLX5E_TX_XSK_POLL_BUDGET 64
146 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
147
148 #define MLX5E_UMR_WQE_INLINE_SZ \
149 (sizeof(struct mlx5e_umr_wqe) + \
150 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
151 MLX5_UMR_MTT_ALIGNMENT))
152 #define MLX5E_UMR_WQEBBS \
153 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
154
155 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
156
157 #define mlx5e_dbg(mlevel, priv, format, ...) \
158 do { \
159 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
160 netdev_warn(priv->netdev, format, \
161 ##__VA_ARGS__); \
162 } while (0)
163
164 #define mlx5e_state_dereference(priv, p) \
165 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
166
167 enum mlx5e_rq_group {
168 MLX5E_RQ_GROUP_REGULAR,
169 MLX5E_RQ_GROUP_XSK,
170 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
171 };
172
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)173 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
174 {
175 if (mlx5_lag_is_lacp_owner(mdev))
176 return 1;
177
178 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
179 }
180
mlx5_min_rx_wqes(int wq_type,u32 wq_size)181 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
182 {
183 switch (wq_type) {
184 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
185 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
186 wq_size / 2);
187 default:
188 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
189 wq_size / 2);
190 }
191 }
192
193 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)194 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
195 {
196 return is_kdump_kernel() ?
197 MLX5E_MIN_NUM_CHANNELS :
198 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
199 }
200
201 struct mlx5e_tx_wqe {
202 struct mlx5_wqe_ctrl_seg ctrl;
203 struct mlx5_wqe_eth_seg eth;
204 struct mlx5_wqe_data_seg data[0];
205 };
206
207 struct mlx5e_rx_wqe_ll {
208 struct mlx5_wqe_srq_next_seg next;
209 struct mlx5_wqe_data_seg data[];
210 };
211
212 struct mlx5e_rx_wqe_cyc {
213 struct mlx5_wqe_data_seg data[0];
214 };
215
216 struct mlx5e_umr_wqe {
217 struct mlx5_wqe_ctrl_seg ctrl;
218 struct mlx5_wqe_umr_ctrl_seg uctrl;
219 struct mlx5_mkey_seg mkc;
220 struct mlx5_mtt inline_mtts[0];
221 };
222
223 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
224
225 enum mlx5e_priv_flag {
226 MLX5E_PFLAG_RX_CQE_BASED_MODER,
227 MLX5E_PFLAG_TX_CQE_BASED_MODER,
228 MLX5E_PFLAG_RX_CQE_COMPRESS,
229 MLX5E_PFLAG_RX_STRIDING_RQ,
230 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
231 MLX5E_PFLAG_XDP_TX_MPWQE,
232 MLX5E_PFLAG_SKB_TX_MPWQE,
233 MLX5E_PFLAG_TX_PORT_TS,
234 MLX5E_NUM_PFLAGS, /* Keep last */
235 };
236
237 #define MLX5E_SET_PFLAG(params, pflag, enable) \
238 do { \
239 if (enable) \
240 (params)->pflags |= BIT(pflag); \
241 else \
242 (params)->pflags &= ~(BIT(pflag)); \
243 } while (0)
244
245 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
246
247 enum packet_merge {
248 MLX5E_PACKET_MERGE_NONE,
249 MLX5E_PACKET_MERGE_LRO,
250 MLX5E_PACKET_MERGE_SHAMPO,
251 };
252
253 struct mlx5e_packet_merge_param {
254 enum packet_merge type;
255 u32 timeout;
256 };
257
258 struct mlx5e_params {
259 u8 log_sq_size;
260 u8 rq_wq_type;
261 u8 log_rq_mtu_frames;
262 u16 num_channels;
263 struct {
264 u16 mode;
265 u8 num_tc;
266 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
267 } mqprio;
268 bool rx_cqe_compress_def;
269 bool tunneled_offload_en;
270 struct dim_cq_moder rx_cq_moderation;
271 struct dim_cq_moder tx_cq_moderation;
272 struct mlx5e_packet_merge_param packet_merge;
273 u8 tx_min_inline_mode;
274 bool vlan_strip_disable;
275 bool scatter_fcs_en;
276 bool rx_dim_enabled;
277 bool tx_dim_enabled;
278 u32 pflags;
279 struct bpf_prog *xdp_prog;
280 struct mlx5e_xsk *xsk;
281 unsigned int sw_mtu;
282 int hard_mtu;
283 bool ptp_rx;
284 };
285
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)286 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
287 {
288 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
289 params->mqprio.num_tc : 1;
290 }
291
292 enum {
293 MLX5E_RQ_STATE_ENABLED,
294 MLX5E_RQ_STATE_RECOVERING,
295 MLX5E_RQ_STATE_AM,
296 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
297 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
298 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
299 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
300 };
301
302 struct mlx5e_cq {
303 /* data path - accessed per cqe */
304 struct mlx5_cqwq wq;
305
306 /* data path - accessed per napi poll */
307 u16 event_ctr;
308 struct napi_struct *napi;
309 struct mlx5_core_cq mcq;
310 struct mlx5e_ch_stats *ch_stats;
311
312 /* control */
313 struct net_device *netdev;
314 struct mlx5_core_dev *mdev;
315 struct mlx5e_priv *priv;
316 struct mlx5_wq_ctrl wq_ctrl;
317 } ____cacheline_aligned_in_smp;
318
319 struct mlx5e_cq_decomp {
320 /* cqe decompression */
321 struct mlx5_cqe64 title;
322 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
323 u8 mini_arr_idx;
324 u16 left;
325 u16 wqe_counter;
326 } ____cacheline_aligned_in_smp;
327
328 enum mlx5e_dma_map_type {
329 MLX5E_DMA_MAP_SINGLE,
330 MLX5E_DMA_MAP_PAGE
331 };
332
333 struct mlx5e_sq_dma {
334 dma_addr_t addr;
335 u32 size;
336 enum mlx5e_dma_map_type type;
337 };
338
339 enum {
340 MLX5E_SQ_STATE_ENABLED,
341 MLX5E_SQ_STATE_MPWQE,
342 MLX5E_SQ_STATE_RECOVERING,
343 MLX5E_SQ_STATE_IPSEC,
344 MLX5E_SQ_STATE_AM,
345 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
346 MLX5E_SQ_STATE_PENDING_XSK_TX,
347 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
348 };
349
350 struct mlx5e_tx_mpwqe {
351 /* Current MPWQE session */
352 struct mlx5e_tx_wqe *wqe;
353 u32 bytes_count;
354 u8 ds_count;
355 u8 pkt_count;
356 u8 inline_on;
357 };
358
359 struct mlx5e_skb_fifo {
360 struct sk_buff **fifo;
361 u16 *pc;
362 u16 *cc;
363 u16 mask;
364 };
365
366 struct mlx5e_ptpsq;
367
368 struct mlx5e_txqsq {
369 /* data path */
370
371 /* dirtied @completion */
372 u16 cc;
373 u16 skb_fifo_cc;
374 u32 dma_fifo_cc;
375 struct dim dim; /* Adaptive Moderation */
376
377 /* dirtied @xmit */
378 u16 pc ____cacheline_aligned_in_smp;
379 u16 skb_fifo_pc;
380 u32 dma_fifo_pc;
381 struct mlx5e_tx_mpwqe mpwqe;
382
383 struct mlx5e_cq cq;
384
385 /* read only */
386 struct mlx5_wq_cyc wq;
387 u32 dma_fifo_mask;
388 struct mlx5e_sq_stats *stats;
389 struct {
390 struct mlx5e_sq_dma *dma_fifo;
391 struct mlx5e_skb_fifo skb_fifo;
392 struct mlx5e_tx_wqe_info *wqe_info;
393 } db;
394 void __iomem *uar_map;
395 struct netdev_queue *txq;
396 u32 sqn;
397 u16 stop_room;
398 u8 min_inline_mode;
399 struct device *pdev;
400 __be32 mkey_be;
401 unsigned long state;
402 unsigned int hw_mtu;
403 struct hwtstamp_config *tstamp;
404 struct mlx5_clock *clock;
405 struct net_device *netdev;
406 struct mlx5_core_dev *mdev;
407 struct mlx5e_priv *priv;
408
409 /* control path */
410 struct mlx5_wq_ctrl wq_ctrl;
411 int ch_ix;
412 int txq_ix;
413 u32 rate_limit;
414 struct work_struct recover_work;
415 struct mlx5e_ptpsq *ptpsq;
416 cqe_ts_to_ns ptp_cyc2time;
417 } ____cacheline_aligned_in_smp;
418
419 struct mlx5e_dma_info {
420 dma_addr_t addr;
421 union {
422 struct page *page;
423 struct xdp_buff *xsk;
424 };
425 };
426
427 /* XDP packets can be transmitted in different ways. On completion, we need to
428 * distinguish between them to clean up things in a proper way.
429 */
430 enum mlx5e_xdp_xmit_mode {
431 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
432 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
433 * returned.
434 */
435 MLX5E_XDP_XMIT_MODE_FRAME,
436
437 /* The xdp_frame was created in place as a result of XDP_TX from a
438 * regular RQ. No DMA remapping happened, and the page belongs to us.
439 */
440 MLX5E_XDP_XMIT_MODE_PAGE,
441
442 /* No xdp_frame was created at all, the transmit happened from a UMEM
443 * page. The UMEM Completion Ring producer pointer has to be increased.
444 */
445 MLX5E_XDP_XMIT_MODE_XSK,
446 };
447
448 struct mlx5e_xdp_info {
449 enum mlx5e_xdp_xmit_mode mode;
450 union {
451 struct {
452 struct xdp_frame *xdpf;
453 dma_addr_t dma_addr;
454 } frame;
455 struct {
456 struct mlx5e_rq *rq;
457 struct mlx5e_dma_info di;
458 } page;
459 };
460 };
461
462 struct mlx5e_xmit_data {
463 dma_addr_t dma_addr;
464 void *data;
465 u32 len;
466 };
467
468 struct mlx5e_xdp_info_fifo {
469 struct mlx5e_xdp_info *xi;
470 u32 *cc;
471 u32 *pc;
472 u32 mask;
473 };
474
475 struct mlx5e_xdpsq;
476 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
477 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
478 struct mlx5e_xmit_data *,
479 struct mlx5e_xdp_info *,
480 int);
481
482 struct mlx5e_xdpsq {
483 /* data path */
484
485 /* dirtied @completion */
486 u32 xdpi_fifo_cc;
487 u16 cc;
488
489 /* dirtied @xmit */
490 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
491 u16 pc;
492 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
493 struct mlx5e_tx_mpwqe mpwqe;
494
495 struct mlx5e_cq cq;
496
497 /* read only */
498 struct xsk_buff_pool *xsk_pool;
499 struct mlx5_wq_cyc wq;
500 struct mlx5e_xdpsq_stats *stats;
501 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
502 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
503 struct {
504 struct mlx5e_xdp_wqe_info *wqe_info;
505 struct mlx5e_xdp_info_fifo xdpi_fifo;
506 } db;
507 void __iomem *uar_map;
508 u32 sqn;
509 struct device *pdev;
510 __be32 mkey_be;
511 u8 min_inline_mode;
512 unsigned long state;
513 unsigned int hw_mtu;
514
515 /* control path */
516 struct mlx5_wq_ctrl wq_ctrl;
517 struct mlx5e_channel *channel;
518 } ____cacheline_aligned_in_smp;
519
520 struct mlx5e_ktls_resync_resp;
521
522 struct mlx5e_icosq {
523 /* data path */
524 u16 cc;
525 u16 pc;
526
527 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
528 struct mlx5e_cq cq;
529
530 /* write@xmit, read@completion */
531 struct {
532 struct mlx5e_icosq_wqe_info *wqe_info;
533 } db;
534
535 /* read only */
536 struct mlx5_wq_cyc wq;
537 void __iomem *uar_map;
538 u32 sqn;
539 u16 reserved_room;
540 unsigned long state;
541 struct mlx5e_ktls_resync_resp *ktls_resync;
542
543 /* control path */
544 struct mlx5_wq_ctrl wq_ctrl;
545 struct mlx5e_channel *channel;
546
547 struct work_struct recover_work;
548 } ____cacheline_aligned_in_smp;
549
550 struct mlx5e_wqe_frag_info {
551 struct mlx5e_dma_info *di;
552 u32 offset;
553 bool last_in_page;
554 };
555
556 struct mlx5e_umr_dma_info {
557 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
558 };
559
560 struct mlx5e_mpw_info {
561 struct mlx5e_umr_dma_info umr;
562 u16 consumed_strides;
563 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
564 };
565
566 #define MLX5E_MAX_RX_FRAGS 4
567
568 /* a single cache unit is capable to serve one napi call (for non-striding rq)
569 * or a MPWQE (for striding rq).
570 */
571 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
572 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
573 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
574 struct mlx5e_page_cache {
575 u32 head;
576 u32 tail;
577 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
578 };
579
580 struct mlx5e_rq;
581 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
582 typedef struct sk_buff *
583 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
584 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
585 typedef struct sk_buff *
586 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
587 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
588 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
589 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
590
591 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
592 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
593
594 enum mlx5e_rq_flag {
595 MLX5E_RQ_FLAG_XDP_XMIT,
596 MLX5E_RQ_FLAG_XDP_REDIRECT,
597 };
598
599 struct mlx5e_rq_frag_info {
600 int frag_size;
601 int frag_stride;
602 };
603
604 struct mlx5e_rq_frags_info {
605 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
606 u8 num_frags;
607 u8 log_num_frags;
608 u8 wqe_bulk;
609 };
610
611 struct mlx5e_rq {
612 /* data path */
613 union {
614 struct {
615 struct mlx5_wq_cyc wq;
616 struct mlx5e_wqe_frag_info *frags;
617 struct mlx5e_dma_info *di;
618 struct mlx5e_rq_frags_info info;
619 mlx5e_fp_skb_from_cqe skb_from_cqe;
620 } wqe;
621 struct {
622 struct mlx5_wq_ll wq;
623 struct mlx5e_umr_wqe umr_wqe;
624 struct mlx5e_mpw_info *info;
625 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
626 u16 num_strides;
627 u16 actual_wq_head;
628 u8 log_stride_sz;
629 u8 umr_in_progress;
630 u8 umr_last_bulk;
631 u8 umr_completed;
632 } mpwqe;
633 };
634 struct {
635 u16 headroom;
636 u32 frame0_sz;
637 u8 map_dir; /* dma map direction */
638 } buff;
639
640 struct device *pdev;
641 struct net_device *netdev;
642 struct mlx5e_rq_stats *stats;
643 struct mlx5e_cq cq;
644 struct mlx5e_cq_decomp cqd;
645 struct mlx5e_page_cache page_cache;
646 struct hwtstamp_config *tstamp;
647 struct mlx5_clock *clock;
648 struct mlx5e_icosq *icosq;
649 struct mlx5e_priv *priv;
650
651 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
652 mlx5e_fp_post_rx_wqes post_wqes;
653 mlx5e_fp_dealloc_wqe dealloc_wqe;
654
655 unsigned long state;
656 int ix;
657 unsigned int hw_mtu;
658
659 struct dim dim; /* Dynamic Interrupt Moderation */
660
661 /* XDP */
662 struct bpf_prog __rcu *xdp_prog;
663 struct mlx5e_xdpsq *xdpsq;
664 DECLARE_BITMAP(flags, 8);
665 struct page_pool *page_pool;
666
667 /* AF_XDP zero-copy */
668 struct xsk_buff_pool *xsk_pool;
669
670 struct work_struct recover_work;
671
672 /* control */
673 struct mlx5_wq_ctrl wq_ctrl;
674 __be32 mkey_be;
675 u8 wq_type;
676 u32 rqn;
677 struct mlx5_core_dev *mdev;
678 struct mlx5_core_mkey umr_mkey;
679 struct mlx5e_dma_info wqe_overflow;
680
681 /* XDP read-mostly */
682 struct xdp_rxq_info xdp_rxq;
683 cqe_ts_to_ns ptp_cyc2time;
684 } ____cacheline_aligned_in_smp;
685
686 enum mlx5e_channel_state {
687 MLX5E_CHANNEL_STATE_XSK,
688 MLX5E_CHANNEL_NUM_STATES
689 };
690
691 struct mlx5e_channel {
692 /* data path */
693 struct mlx5e_rq rq;
694 struct mlx5e_xdpsq rq_xdpsq;
695 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
696 struct mlx5e_icosq icosq; /* internal control operations */
697 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
698 bool xdp;
699 struct napi_struct napi;
700 struct device *pdev;
701 struct net_device *netdev;
702 __be32 mkey_be;
703 u16 qos_sqs_size;
704 u8 num_tc;
705 u8 lag_port;
706
707 /* XDP_REDIRECT */
708 struct mlx5e_xdpsq xdpsq;
709
710 /* AF_XDP zero-copy */
711 struct mlx5e_rq xskrq;
712 struct mlx5e_xdpsq xsksq;
713
714 /* Async ICOSQ */
715 struct mlx5e_icosq async_icosq;
716 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
717 spinlock_t async_icosq_lock;
718
719 /* data path - accessed per napi poll */
720 const struct cpumask *aff_mask;
721 struct mlx5e_ch_stats *stats;
722
723 /* control */
724 struct mlx5e_priv *priv;
725 struct mlx5_core_dev *mdev;
726 struct hwtstamp_config *tstamp;
727 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
728 int ix;
729 int cpu;
730 /* Sync between icosq recovery and XSK enable/disable. */
731 struct mutex icosq_recovery_lock;
732 };
733
734 struct mlx5e_ptp;
735
736 struct mlx5e_channels {
737 struct mlx5e_channel **c;
738 struct mlx5e_ptp *ptp;
739 unsigned int num;
740 struct mlx5e_params params;
741 };
742
743 struct mlx5e_channel_stats {
744 struct mlx5e_ch_stats ch;
745 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
746 struct mlx5e_rq_stats rq;
747 struct mlx5e_rq_stats xskrq;
748 struct mlx5e_xdpsq_stats rq_xdpsq;
749 struct mlx5e_xdpsq_stats xdpsq;
750 struct mlx5e_xdpsq_stats xsksq;
751 } ____cacheline_aligned_in_smp;
752
753 struct mlx5e_ptp_stats {
754 struct mlx5e_ch_stats ch;
755 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
756 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
757 struct mlx5e_rq_stats rq;
758 } ____cacheline_aligned_in_smp;
759
760 enum {
761 MLX5E_STATE_OPENED,
762 MLX5E_STATE_DESTROYING,
763 MLX5E_STATE_XDP_TX_ENABLED,
764 MLX5E_STATE_XDP_ACTIVE,
765 };
766
767 enum {
768 MLX5E_TC_PRIO = 0,
769 MLX5E_NIC_PRIO
770 };
771
772 struct mlx5e_modify_sq_param {
773 int curr_state;
774 int next_state;
775 int rl_update;
776 int rl_index;
777 bool qos_update;
778 u16 qos_queue_group_id;
779 };
780
781 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
782 struct mlx5e_hv_vhca_stats_agent {
783 struct mlx5_hv_vhca_agent *agent;
784 struct delayed_work work;
785 u16 delay;
786 void *buf;
787 };
788 #endif
789
790 struct mlx5e_xsk {
791 /* XSK buffer pools are stored separately from channels,
792 * because we don't want to lose them when channels are
793 * recreated. The kernel also stores buffer pool, but it doesn't
794 * distinguish between zero-copy and non-zero-copy UMEMs, so
795 * rely on our mechanism.
796 */
797 struct xsk_buff_pool **pools;
798 u16 refcnt;
799 bool ever_used;
800 };
801
802 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
803 * initialized, and used where we can't allocate them because that functions
804 * must not fail. Use with care and make sure the same variable is not used
805 * simultaneously by multiple users.
806 */
807 struct mlx5e_scratchpad {
808 cpumask_var_t cpumask;
809 };
810
811 struct mlx5e_htb {
812 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES));
813 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES);
814 struct mlx5e_sq_stats **qos_sq_stats;
815 u16 max_qos_sqs;
816 u16 maj_id;
817 u16 defcls;
818 };
819
820 struct mlx5e_trap;
821
822 struct mlx5e_priv {
823 /* priv data path fields - start */
824 /* +1 for port ptp ts */
825 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC +
826 MLX5E_QOS_MAX_LEAF_NODES];
827 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
828 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
829 #ifdef CONFIG_MLX5_CORE_EN_DCB
830 struct mlx5e_dcbx_dp dcbx_dp;
831 #endif
832 /* priv data path fields - end */
833
834 u32 msglevel;
835 unsigned long state;
836 struct mutex state_lock; /* Protects Interface state */
837 struct mlx5e_rq drop_rq;
838
839 struct mlx5e_channels channels;
840 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
841 struct mlx5e_rx_res *rx_res;
842 u32 tx_rates[MLX5E_MAX_NUM_SQS];
843
844 struct mlx5e_flow_steering fs;
845
846 struct workqueue_struct *wq;
847 struct work_struct update_carrier_work;
848 struct work_struct set_rx_mode_work;
849 struct work_struct tx_timeout_work;
850 struct work_struct update_stats_work;
851 struct work_struct monitor_counters_work;
852 struct mlx5_nb monitor_counters_nb;
853
854 struct mlx5_core_dev *mdev;
855 struct net_device *netdev;
856 struct mlx5e_trap *en_trap;
857 struct mlx5e_stats stats;
858 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
859 struct mlx5e_channel_stats trap_stats;
860 struct mlx5e_ptp_stats ptp_stats;
861 u16 stats_nch;
862 u16 max_nch;
863 u8 max_opened_tc;
864 bool tx_ptp_opened;
865 bool rx_ptp_opened;
866 struct hwtstamp_config tstamp;
867 u16 q_counter;
868 u16 drop_rq_q_counter;
869 struct notifier_block events_nb;
870 struct notifier_block blocking_events_nb;
871 int num_tc_x_num_ch;
872
873 struct udp_tunnel_nic_info nic_info;
874 #ifdef CONFIG_MLX5_CORE_EN_DCB
875 struct mlx5e_dcbx dcbx;
876 #endif
877
878 const struct mlx5e_profile *profile;
879 void *ppriv;
880 #ifdef CONFIG_MLX5_EN_IPSEC
881 struct mlx5e_ipsec *ipsec;
882 #endif
883 #ifdef CONFIG_MLX5_EN_TLS
884 struct mlx5e_tls *tls;
885 #endif
886 struct devlink_health_reporter *tx_reporter;
887 struct devlink_health_reporter *rx_reporter;
888 struct mlx5e_xsk xsk;
889 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
890 struct mlx5e_hv_vhca_stats_agent stats_agent;
891 #endif
892 struct mlx5e_scratchpad scratchpad;
893 struct mlx5e_htb htb;
894 };
895
896 struct mlx5e_rx_handlers {
897 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
898 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
899 };
900
901 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
902
903 struct mlx5e_profile {
904 int (*init)(struct mlx5_core_dev *mdev,
905 struct net_device *netdev);
906 void (*cleanup)(struct mlx5e_priv *priv);
907 int (*init_rx)(struct mlx5e_priv *priv);
908 void (*cleanup_rx)(struct mlx5e_priv *priv);
909 int (*init_tx)(struct mlx5e_priv *priv);
910 void (*cleanup_tx)(struct mlx5e_priv *priv);
911 void (*enable)(struct mlx5e_priv *priv);
912 void (*disable)(struct mlx5e_priv *priv);
913 int (*update_rx)(struct mlx5e_priv *priv);
914 void (*update_stats)(struct mlx5e_priv *priv);
915 void (*update_carrier)(struct mlx5e_priv *priv);
916 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
917 mlx5e_stats_grp_t *stats_grps;
918 const struct mlx5e_rx_handlers *rx_handlers;
919 int max_tc;
920 u8 rq_groups;
921 bool rx_ptp_support;
922 };
923
924 void mlx5e_build_ptys2ethtool_map(void);
925
926 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
927
928 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
929 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
930
931 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
932 int mlx5e_self_test_num(struct mlx5e_priv *priv);
933 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
934 u64 *buf);
935 void mlx5e_set_rx_mode_work(struct work_struct *work);
936
937 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
938 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
939 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
940
941 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
942 u16 vid);
943 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
944 u16 vid);
945 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
946
947 struct mlx5e_xsk_param;
948
949 struct mlx5e_rq_param;
950 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
951 struct mlx5e_xsk_param *xsk, int node,
952 struct mlx5e_rq *rq);
953 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
954 void mlx5e_close_rq(struct mlx5e_rq *rq);
955 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
956 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
957
958 struct mlx5e_sq_param;
959 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
960 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
961 struct mlx5e_xdpsq *sq, bool is_redirect);
962 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
963
964 struct mlx5e_create_cq_param {
965 struct napi_struct *napi;
966 struct mlx5e_ch_stats *ch_stats;
967 int node;
968 int ix;
969 };
970
971 struct mlx5e_cq_param;
972 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
973 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
974 struct mlx5e_cq *cq);
975 void mlx5e_close_cq(struct mlx5e_cq *cq);
976
977 int mlx5e_open_locked(struct net_device *netdev);
978 int mlx5e_close_locked(struct net_device *netdev);
979
980 int mlx5e_open_channels(struct mlx5e_priv *priv,
981 struct mlx5e_channels *chs);
982 void mlx5e_close_channels(struct mlx5e_channels *chs);
983
984 /* Function pointer to be used to modify HW or kernel settings while
985 * switching channels
986 */
987 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
988 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
989 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
990 { \
991 return fn(priv); \
992 }
993 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
994 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
995 struct mlx5e_params *new_params,
996 mlx5e_fp_preactivate preactivate,
997 void *context, bool reset);
998 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
999 int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
1000 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1001 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1002 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1003 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1004
1005 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1006 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1007 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1008 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1009 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1010
1011 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1012 struct mlx5e_modify_sq_param *p);
1013 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1014 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1015 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid);
1016 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1017 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1018 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1019 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1020 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1021 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1022 struct mlx5e_create_sq_param;
1023 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1024 struct mlx5e_sq_param *param,
1025 struct mlx5e_create_sq_param *csp,
1026 u16 qos_queue_group_id,
1027 u32 *sqn);
1028 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1029 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1030
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1031 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1032 {
1033 return MLX5_CAP_ETH(mdev, swp) &&
1034 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1035 }
1036
1037 extern const struct ethtool_ops mlx5e_ethtool_ops;
1038
1039 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1040 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1041 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1042 bool enable_mc_lb);
1043 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1044
1045 /* common netdev helpers */
1046 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1047 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1048 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1049 struct mlx5e_rq *drop_rq);
1050 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1051 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node);
1052 void mlx5e_free_di_list(struct mlx5e_rq *rq);
1053
1054 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1055 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1056
1057 int mlx5e_create_tises(struct mlx5e_priv *priv);
1058 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1059 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1060 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1061 int mlx5e_close(struct net_device *netdev);
1062 int mlx5e_open(struct net_device *netdev);
1063
1064 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1065
1066 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1067 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1068 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1069 mlx5e_fp_preactivate preactivate);
1070 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1071
1072 /* ethtool helpers */
1073 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1074 struct ethtool_drvinfo *drvinfo);
1075 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1076 uint32_t stringset, uint8_t *data);
1077 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1078 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1079 struct ethtool_stats *stats, u64 *data);
1080 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1081 struct ethtool_ringparam *param);
1082 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1083 struct ethtool_ringparam *param);
1084 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1085 struct ethtool_channels *ch);
1086 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1087 struct ethtool_channels *ch);
1088 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1089 struct ethtool_coalesce *coal);
1090 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1091 struct ethtool_coalesce *coal);
1092 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1093 struct ethtool_link_ksettings *link_ksettings);
1094 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1095 const struct ethtool_link_ksettings *link_ksettings);
1096 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
1097 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
1098 const u8 hfunc);
1099 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1100 u32 *rule_locs);
1101 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
1102 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1103 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1104 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1105 struct ethtool_ts_info *info);
1106 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1107 struct ethtool_flash *flash);
1108 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1109 struct ethtool_pauseparam *pauseparam);
1110 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1111 struct ethtool_pauseparam *pauseparam);
1112
1113 /* mlx5e generic netdev management API */
1114 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1115 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1116 {
1117 return !is_kdump_kernel() &&
1118 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1119 }
1120
1121 int mlx5e_priv_init(struct mlx5e_priv *priv,
1122 const struct mlx5e_profile *profile,
1123 struct net_device *netdev,
1124 struct mlx5_core_dev *mdev);
1125 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1126 struct net_device *
1127 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1128 unsigned int txqs, unsigned int rxqs);
1129 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1130 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1131 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1132 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1133 const struct mlx5e_profile *new_profile, void *new_ppriv);
1134 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1135 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1136 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1137 void mlx5e_rx_dim_work(struct work_struct *work);
1138 void mlx5e_tx_dim_work(struct work_struct *work);
1139
1140 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1141 struct net_device *netdev,
1142 netdev_features_t features);
1143 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1144 #ifdef CONFIG_MLX5_ESWITCH
1145 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1146 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1147 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1148 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1149 #endif
1150 #endif /* __MLX5_EN_H__ */
1151