1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2
3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */
4 /* Copyright (c) 2008-2019, IBM Corporation */
5
6 #include <linux/errno.h>
7 #include <linux/types.h>
8 #include <linux/uaccess.h>
9 #include <linux/vmalloc.h>
10 #include <linux/xarray.h>
11
12 #include <rdma/iw_cm.h>
13 #include <rdma/ib_verbs.h>
14 #include <rdma/ib_user_verbs.h>
15 #include <rdma/uverbs_ioctl.h>
16
17 #include "siw.h"
18 #include "siw_verbs.h"
19 #include "siw_mem.h"
20
21 static int ib_qp_state_to_siw_qp_state[IB_QPS_ERR + 1] = {
22 [IB_QPS_RESET] = SIW_QP_STATE_IDLE,
23 [IB_QPS_INIT] = SIW_QP_STATE_IDLE,
24 [IB_QPS_RTR] = SIW_QP_STATE_RTR,
25 [IB_QPS_RTS] = SIW_QP_STATE_RTS,
26 [IB_QPS_SQD] = SIW_QP_STATE_CLOSING,
27 [IB_QPS_SQE] = SIW_QP_STATE_TERMINATE,
28 [IB_QPS_ERR] = SIW_QP_STATE_ERROR
29 };
30
31 static char ib_qp_state_to_string[IB_QPS_ERR + 1][sizeof("RESET")] = {
32 [IB_QPS_RESET] = "RESET", [IB_QPS_INIT] = "INIT", [IB_QPS_RTR] = "RTR",
33 [IB_QPS_RTS] = "RTS", [IB_QPS_SQD] = "SQD", [IB_QPS_SQE] = "SQE",
34 [IB_QPS_ERR] = "ERR"
35 };
36
siw_mmap_free(struct rdma_user_mmap_entry * rdma_entry)37 void siw_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
38 {
39 struct siw_user_mmap_entry *entry = to_siw_mmap_entry(rdma_entry);
40
41 kfree(entry);
42 }
43
siw_mmap(struct ib_ucontext * ctx,struct vm_area_struct * vma)44 int siw_mmap(struct ib_ucontext *ctx, struct vm_area_struct *vma)
45 {
46 struct siw_ucontext *uctx = to_siw_ctx(ctx);
47 size_t size = vma->vm_end - vma->vm_start;
48 struct rdma_user_mmap_entry *rdma_entry;
49 struct siw_user_mmap_entry *entry;
50 int rv = -EINVAL;
51
52 /*
53 * Must be page aligned
54 */
55 if (vma->vm_start & (PAGE_SIZE - 1)) {
56 pr_warn("siw: mmap not page aligned\n");
57 return -EINVAL;
58 }
59 rdma_entry = rdma_user_mmap_entry_get(&uctx->base_ucontext, vma);
60 if (!rdma_entry) {
61 siw_dbg(&uctx->sdev->base_dev, "mmap lookup failed: %lu, %#zx\n",
62 vma->vm_pgoff, size);
63 return -EINVAL;
64 }
65 entry = to_siw_mmap_entry(rdma_entry);
66
67 rv = remap_vmalloc_range(vma, entry->address, 0);
68 if (rv) {
69 pr_warn("remap_vmalloc_range failed: %lu, %zu\n", vma->vm_pgoff,
70 size);
71 goto out;
72 }
73 out:
74 rdma_user_mmap_entry_put(rdma_entry);
75
76 return rv;
77 }
78
siw_alloc_ucontext(struct ib_ucontext * base_ctx,struct ib_udata * udata)79 int siw_alloc_ucontext(struct ib_ucontext *base_ctx, struct ib_udata *udata)
80 {
81 struct siw_device *sdev = to_siw_dev(base_ctx->device);
82 struct siw_ucontext *ctx = to_siw_ctx(base_ctx);
83 struct siw_uresp_alloc_ctx uresp = {};
84 int rv;
85
86 if (atomic_inc_return(&sdev->num_ctx) > SIW_MAX_CONTEXT) {
87 rv = -ENOMEM;
88 goto err_out;
89 }
90 ctx->sdev = sdev;
91
92 uresp.dev_id = sdev->vendor_part_id;
93
94 if (udata->outlen < sizeof(uresp)) {
95 rv = -EINVAL;
96 goto err_out;
97 }
98 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
99 if (rv)
100 goto err_out;
101
102 siw_dbg(base_ctx->device, "success. now %d context(s)\n",
103 atomic_read(&sdev->num_ctx));
104
105 return 0;
106
107 err_out:
108 atomic_dec(&sdev->num_ctx);
109 siw_dbg(base_ctx->device, "failure %d. now %d context(s)\n", rv,
110 atomic_read(&sdev->num_ctx));
111
112 return rv;
113 }
114
siw_dealloc_ucontext(struct ib_ucontext * base_ctx)115 void siw_dealloc_ucontext(struct ib_ucontext *base_ctx)
116 {
117 struct siw_ucontext *uctx = to_siw_ctx(base_ctx);
118
119 atomic_dec(&uctx->sdev->num_ctx);
120 }
121
siw_query_device(struct ib_device * base_dev,struct ib_device_attr * attr,struct ib_udata * udata)122 int siw_query_device(struct ib_device *base_dev, struct ib_device_attr *attr,
123 struct ib_udata *udata)
124 {
125 struct siw_device *sdev = to_siw_dev(base_dev);
126
127 if (udata->inlen || udata->outlen)
128 return -EINVAL;
129
130 memset(attr, 0, sizeof(*attr));
131
132 /* Revisit atomic caps if RFC 7306 gets supported */
133 attr->atomic_cap = 0;
134 attr->device_cap_flags =
135 IB_DEVICE_MEM_MGT_EXTENSIONS | IB_DEVICE_ALLOW_USER_UNREG;
136 attr->max_cq = sdev->attrs.max_cq;
137 attr->max_cqe = sdev->attrs.max_cqe;
138 attr->max_fast_reg_page_list_len = SIW_MAX_SGE_PBL;
139 attr->max_mr = sdev->attrs.max_mr;
140 attr->max_mw = sdev->attrs.max_mw;
141 attr->max_mr_size = ~0ull;
142 attr->max_pd = sdev->attrs.max_pd;
143 attr->max_qp = sdev->attrs.max_qp;
144 attr->max_qp_init_rd_atom = sdev->attrs.max_ird;
145 attr->max_qp_rd_atom = sdev->attrs.max_ord;
146 attr->max_qp_wr = sdev->attrs.max_qp_wr;
147 attr->max_recv_sge = sdev->attrs.max_sge;
148 attr->max_res_rd_atom = sdev->attrs.max_qp * sdev->attrs.max_ird;
149 attr->max_send_sge = sdev->attrs.max_sge;
150 attr->max_sge_rd = sdev->attrs.max_sge_rd;
151 attr->max_srq = sdev->attrs.max_srq;
152 attr->max_srq_sge = sdev->attrs.max_srq_sge;
153 attr->max_srq_wr = sdev->attrs.max_srq_wr;
154 attr->page_size_cap = PAGE_SIZE;
155 attr->vendor_id = SIW_VENDOR_ID;
156 attr->vendor_part_id = sdev->vendor_part_id;
157
158 memcpy(&attr->sys_image_guid, sdev->netdev->dev_addr, 6);
159
160 return 0;
161 }
162
siw_query_port(struct ib_device * base_dev,u32 port,struct ib_port_attr * attr)163 int siw_query_port(struct ib_device *base_dev, u32 port,
164 struct ib_port_attr *attr)
165 {
166 struct siw_device *sdev = to_siw_dev(base_dev);
167 int rv;
168
169 memset(attr, 0, sizeof(*attr));
170
171 rv = ib_get_eth_speed(base_dev, port, &attr->active_speed,
172 &attr->active_width);
173 attr->gid_tbl_len = 1;
174 attr->max_msg_sz = -1;
175 attr->max_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu);
176 attr->active_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu);
177 attr->phys_state = sdev->state == IB_PORT_ACTIVE ?
178 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED;
179 attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_DEVICE_MGMT_SUP;
180 attr->state = sdev->state;
181 /*
182 * All zero
183 *
184 * attr->lid = 0;
185 * attr->bad_pkey_cntr = 0;
186 * attr->qkey_viol_cntr = 0;
187 * attr->sm_lid = 0;
188 * attr->lmc = 0;
189 * attr->max_vl_num = 0;
190 * attr->sm_sl = 0;
191 * attr->subnet_timeout = 0;
192 * attr->init_type_repy = 0;
193 */
194 return rv;
195 }
196
siw_get_port_immutable(struct ib_device * base_dev,u32 port,struct ib_port_immutable * port_immutable)197 int siw_get_port_immutable(struct ib_device *base_dev, u32 port,
198 struct ib_port_immutable *port_immutable)
199 {
200 struct ib_port_attr attr;
201 int rv = siw_query_port(base_dev, port, &attr);
202
203 if (rv)
204 return rv;
205
206 port_immutable->gid_tbl_len = attr.gid_tbl_len;
207 port_immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
208
209 return 0;
210 }
211
siw_query_gid(struct ib_device * base_dev,u32 port,int idx,union ib_gid * gid)212 int siw_query_gid(struct ib_device *base_dev, u32 port, int idx,
213 union ib_gid *gid)
214 {
215 struct siw_device *sdev = to_siw_dev(base_dev);
216
217 /* subnet_prefix == interface_id == 0; */
218 memset(gid, 0, sizeof(*gid));
219 memcpy(&gid->raw[0], sdev->netdev->dev_addr, 6);
220
221 return 0;
222 }
223
siw_alloc_pd(struct ib_pd * pd,struct ib_udata * udata)224 int siw_alloc_pd(struct ib_pd *pd, struct ib_udata *udata)
225 {
226 struct siw_device *sdev = to_siw_dev(pd->device);
227
228 if (atomic_inc_return(&sdev->num_pd) > SIW_MAX_PD) {
229 atomic_dec(&sdev->num_pd);
230 return -ENOMEM;
231 }
232 siw_dbg_pd(pd, "now %d PD's(s)\n", atomic_read(&sdev->num_pd));
233
234 return 0;
235 }
236
siw_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)237 int siw_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
238 {
239 struct siw_device *sdev = to_siw_dev(pd->device);
240
241 siw_dbg_pd(pd, "free PD\n");
242 atomic_dec(&sdev->num_pd);
243 return 0;
244 }
245
siw_qp_get_ref(struct ib_qp * base_qp)246 void siw_qp_get_ref(struct ib_qp *base_qp)
247 {
248 siw_qp_get(to_siw_qp(base_qp));
249 }
250
siw_qp_put_ref(struct ib_qp * base_qp)251 void siw_qp_put_ref(struct ib_qp *base_qp)
252 {
253 siw_qp_put(to_siw_qp(base_qp));
254 }
255
256 static struct rdma_user_mmap_entry *
siw_mmap_entry_insert(struct siw_ucontext * uctx,void * address,size_t length,u64 * offset)257 siw_mmap_entry_insert(struct siw_ucontext *uctx,
258 void *address, size_t length,
259 u64 *offset)
260 {
261 struct siw_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
262 int rv;
263
264 *offset = SIW_INVAL_UOBJ_KEY;
265 if (!entry)
266 return NULL;
267
268 entry->address = address;
269
270 rv = rdma_user_mmap_entry_insert(&uctx->base_ucontext,
271 &entry->rdma_entry,
272 length);
273 if (rv) {
274 kfree(entry);
275 return NULL;
276 }
277
278 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
279
280 return &entry->rdma_entry;
281 }
282
283 /*
284 * siw_create_qp()
285 *
286 * Create QP of requested size on given device.
287 *
288 * @qp: Queue pait
289 * @attrs: Initial QP attributes.
290 * @udata: used to provide QP ID, SQ and RQ size back to user.
291 */
292
siw_create_qp(struct ib_qp * ibqp,struct ib_qp_init_attr * attrs,struct ib_udata * udata)293 int siw_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,
294 struct ib_udata *udata)
295 {
296 struct ib_pd *pd = ibqp->pd;
297 struct siw_qp *qp = to_siw_qp(ibqp);
298 struct ib_device *base_dev = pd->device;
299 struct siw_device *sdev = to_siw_dev(base_dev);
300 struct siw_ucontext *uctx =
301 rdma_udata_to_drv_context(udata, struct siw_ucontext,
302 base_ucontext);
303 unsigned long flags;
304 int num_sqe, num_rqe, rv = 0;
305 size_t length;
306
307 siw_dbg(base_dev, "create new QP\n");
308
309 if (attrs->create_flags)
310 return -EOPNOTSUPP;
311
312 if (atomic_inc_return(&sdev->num_qp) > SIW_MAX_QP) {
313 siw_dbg(base_dev, "too many QP's\n");
314 rv = -ENOMEM;
315 goto err_atomic;
316 }
317 if (attrs->qp_type != IB_QPT_RC) {
318 siw_dbg(base_dev, "only RC QP's supported\n");
319 rv = -EOPNOTSUPP;
320 goto err_atomic;
321 }
322 if ((attrs->cap.max_send_wr > SIW_MAX_QP_WR) ||
323 (attrs->cap.max_recv_wr > SIW_MAX_QP_WR) ||
324 (attrs->cap.max_send_sge > SIW_MAX_SGE) ||
325 (attrs->cap.max_recv_sge > SIW_MAX_SGE)) {
326 siw_dbg(base_dev, "QP size error\n");
327 rv = -EINVAL;
328 goto err_atomic;
329 }
330 if (attrs->cap.max_inline_data > SIW_MAX_INLINE) {
331 siw_dbg(base_dev, "max inline send: %d > %d\n",
332 attrs->cap.max_inline_data, (int)SIW_MAX_INLINE);
333 rv = -EINVAL;
334 goto err_atomic;
335 }
336 /*
337 * NOTE: we allow for zero element SQ and RQ WQE's SGL's
338 * but not for a QP unable to hold any WQE (SQ + RQ)
339 */
340 if (attrs->cap.max_send_wr + attrs->cap.max_recv_wr == 0) {
341 siw_dbg(base_dev, "QP must have send or receive queue\n");
342 rv = -EINVAL;
343 goto err_atomic;
344 }
345
346 if (!attrs->send_cq || (!attrs->recv_cq && !attrs->srq)) {
347 siw_dbg(base_dev, "send CQ or receive CQ invalid\n");
348 rv = -EINVAL;
349 goto err_atomic;
350 }
351
352 init_rwsem(&qp->state_lock);
353 spin_lock_init(&qp->sq_lock);
354 spin_lock_init(&qp->rq_lock);
355 spin_lock_init(&qp->orq_lock);
356
357 rv = siw_qp_add(sdev, qp);
358 if (rv)
359 goto err_atomic;
360
361 num_sqe = attrs->cap.max_send_wr;
362 num_rqe = attrs->cap.max_recv_wr;
363
364 /* All queue indices are derived from modulo operations
365 * on a free running 'get' (consumer) and 'put' (producer)
366 * unsigned counter. Having queue sizes at power of two
367 * avoids handling counter wrap around.
368 */
369 if (num_sqe)
370 num_sqe = roundup_pow_of_two(num_sqe);
371 else {
372 /* Zero sized SQ is not supported */
373 rv = -EINVAL;
374 goto err_out_xa;
375 }
376 if (num_rqe)
377 num_rqe = roundup_pow_of_two(num_rqe);
378
379 if (udata)
380 qp->sendq = vmalloc_user(num_sqe * sizeof(struct siw_sqe));
381 else
382 qp->sendq = vzalloc(num_sqe * sizeof(struct siw_sqe));
383
384 if (qp->sendq == NULL) {
385 rv = -ENOMEM;
386 goto err_out_xa;
387 }
388 if (attrs->sq_sig_type != IB_SIGNAL_REQ_WR) {
389 if (attrs->sq_sig_type == IB_SIGNAL_ALL_WR)
390 qp->attrs.flags |= SIW_SIGNAL_ALL_WR;
391 else {
392 rv = -EINVAL;
393 goto err_out_xa;
394 }
395 }
396 qp->pd = pd;
397 qp->scq = to_siw_cq(attrs->send_cq);
398 qp->rcq = to_siw_cq(attrs->recv_cq);
399
400 if (attrs->srq) {
401 /*
402 * SRQ support.
403 * Verbs 6.3.7: ignore RQ size, if SRQ present
404 * Verbs 6.3.5: do not check PD of SRQ against PD of QP
405 */
406 qp->srq = to_siw_srq(attrs->srq);
407 qp->attrs.rq_size = 0;
408 siw_dbg(base_dev, "QP [%u]: SRQ attached\n",
409 qp->base_qp.qp_num);
410 } else if (num_rqe) {
411 if (udata)
412 qp->recvq =
413 vmalloc_user(num_rqe * sizeof(struct siw_rqe));
414 else
415 qp->recvq = vzalloc(num_rqe * sizeof(struct siw_rqe));
416
417 if (qp->recvq == NULL) {
418 rv = -ENOMEM;
419 goto err_out_xa;
420 }
421 qp->attrs.rq_size = num_rqe;
422 }
423 qp->attrs.sq_size = num_sqe;
424 qp->attrs.sq_max_sges = attrs->cap.max_send_sge;
425 qp->attrs.rq_max_sges = attrs->cap.max_recv_sge;
426
427 /* Make those two tunables fixed for now. */
428 qp->tx_ctx.gso_seg_limit = 1;
429 qp->tx_ctx.zcopy_tx = zcopy_tx;
430
431 qp->attrs.state = SIW_QP_STATE_IDLE;
432
433 if (udata) {
434 struct siw_uresp_create_qp uresp = {};
435
436 uresp.num_sqe = num_sqe;
437 uresp.num_rqe = num_rqe;
438 uresp.qp_id = qp_id(qp);
439
440 if (qp->sendq) {
441 length = num_sqe * sizeof(struct siw_sqe);
442 qp->sq_entry =
443 siw_mmap_entry_insert(uctx, qp->sendq,
444 length, &uresp.sq_key);
445 if (!qp->sq_entry) {
446 rv = -ENOMEM;
447 goto err_out_xa;
448 }
449 }
450
451 if (qp->recvq) {
452 length = num_rqe * sizeof(struct siw_rqe);
453 qp->rq_entry =
454 siw_mmap_entry_insert(uctx, qp->recvq,
455 length, &uresp.rq_key);
456 if (!qp->rq_entry) {
457 uresp.sq_key = SIW_INVAL_UOBJ_KEY;
458 rv = -ENOMEM;
459 goto err_out_xa;
460 }
461 }
462
463 if (udata->outlen < sizeof(uresp)) {
464 rv = -EINVAL;
465 goto err_out_xa;
466 }
467 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
468 if (rv)
469 goto err_out_xa;
470 }
471 qp->tx_cpu = siw_get_tx_cpu(sdev);
472 if (qp->tx_cpu < 0) {
473 rv = -EINVAL;
474 goto err_out_xa;
475 }
476 INIT_LIST_HEAD(&qp->devq);
477 spin_lock_irqsave(&sdev->lock, flags);
478 list_add_tail(&qp->devq, &sdev->qp_list);
479 spin_unlock_irqrestore(&sdev->lock, flags);
480
481 init_completion(&qp->qp_free);
482
483 return 0;
484
485 err_out_xa:
486 xa_erase(&sdev->qp_xa, qp_id(qp));
487 if (uctx) {
488 rdma_user_mmap_entry_remove(qp->sq_entry);
489 rdma_user_mmap_entry_remove(qp->rq_entry);
490 }
491 vfree(qp->sendq);
492 vfree(qp->recvq);
493
494 err_atomic:
495 atomic_dec(&sdev->num_qp);
496 return rv;
497 }
498
499 /*
500 * Minimum siw_query_qp() verb interface.
501 *
502 * @qp_attr_mask is not used but all available information is provided
503 */
siw_query_qp(struct ib_qp * base_qp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)504 int siw_query_qp(struct ib_qp *base_qp, struct ib_qp_attr *qp_attr,
505 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
506 {
507 struct siw_qp *qp;
508 struct siw_device *sdev;
509
510 if (base_qp && qp_attr && qp_init_attr) {
511 qp = to_siw_qp(base_qp);
512 sdev = to_siw_dev(base_qp->device);
513 } else {
514 return -EINVAL;
515 }
516 qp_attr->cap.max_inline_data = SIW_MAX_INLINE;
517 qp_attr->cap.max_send_wr = qp->attrs.sq_size;
518 qp_attr->cap.max_send_sge = qp->attrs.sq_max_sges;
519 qp_attr->cap.max_recv_wr = qp->attrs.rq_size;
520 qp_attr->cap.max_recv_sge = qp->attrs.rq_max_sges;
521 qp_attr->path_mtu = ib_mtu_int_to_enum(sdev->netdev->mtu);
522 qp_attr->max_rd_atomic = qp->attrs.irq_size;
523 qp_attr->max_dest_rd_atomic = qp->attrs.orq_size;
524
525 qp_attr->qp_access_flags = IB_ACCESS_LOCAL_WRITE |
526 IB_ACCESS_REMOTE_WRITE |
527 IB_ACCESS_REMOTE_READ;
528
529 qp_init_attr->qp_type = base_qp->qp_type;
530 qp_init_attr->send_cq = base_qp->send_cq;
531 qp_init_attr->recv_cq = base_qp->recv_cq;
532 qp_init_attr->srq = base_qp->srq;
533
534 qp_init_attr->cap = qp_attr->cap;
535
536 return 0;
537 }
538
siw_verbs_modify_qp(struct ib_qp * base_qp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)539 int siw_verbs_modify_qp(struct ib_qp *base_qp, struct ib_qp_attr *attr,
540 int attr_mask, struct ib_udata *udata)
541 {
542 struct siw_qp_attrs new_attrs;
543 enum siw_qp_attr_mask siw_attr_mask = 0;
544 struct siw_qp *qp = to_siw_qp(base_qp);
545 int rv = 0;
546
547 if (!attr_mask)
548 return 0;
549
550 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
551 return -EOPNOTSUPP;
552
553 memset(&new_attrs, 0, sizeof(new_attrs));
554
555 if (attr_mask & IB_QP_ACCESS_FLAGS) {
556 siw_attr_mask = SIW_QP_ATTR_ACCESS_FLAGS;
557
558 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
559 new_attrs.flags |= SIW_RDMA_READ_ENABLED;
560 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
561 new_attrs.flags |= SIW_RDMA_WRITE_ENABLED;
562 if (attr->qp_access_flags & IB_ACCESS_MW_BIND)
563 new_attrs.flags |= SIW_RDMA_BIND_ENABLED;
564 }
565 if (attr_mask & IB_QP_STATE) {
566 siw_dbg_qp(qp, "desired IB QP state: %s\n",
567 ib_qp_state_to_string[attr->qp_state]);
568
569 new_attrs.state = ib_qp_state_to_siw_qp_state[attr->qp_state];
570
571 if (new_attrs.state > SIW_QP_STATE_RTS)
572 qp->tx_ctx.tx_suspend = 1;
573
574 siw_attr_mask |= SIW_QP_ATTR_STATE;
575 }
576 if (!siw_attr_mask)
577 goto out;
578
579 down_write(&qp->state_lock);
580
581 rv = siw_qp_modify(qp, &new_attrs, siw_attr_mask);
582
583 up_write(&qp->state_lock);
584 out:
585 return rv;
586 }
587
siw_destroy_qp(struct ib_qp * base_qp,struct ib_udata * udata)588 int siw_destroy_qp(struct ib_qp *base_qp, struct ib_udata *udata)
589 {
590 struct siw_qp *qp = to_siw_qp(base_qp);
591 struct siw_ucontext *uctx =
592 rdma_udata_to_drv_context(udata, struct siw_ucontext,
593 base_ucontext);
594 struct siw_qp_attrs qp_attrs;
595
596 siw_dbg_qp(qp, "state %d\n", qp->attrs.state);
597
598 /*
599 * Mark QP as in process of destruction to prevent from
600 * any async callbacks to RDMA core
601 */
602 qp->attrs.flags |= SIW_QP_IN_DESTROY;
603 qp->rx_stream.rx_suspend = 1;
604
605 if (uctx) {
606 rdma_user_mmap_entry_remove(qp->sq_entry);
607 rdma_user_mmap_entry_remove(qp->rq_entry);
608 }
609
610 down_write(&qp->state_lock);
611
612 qp_attrs.state = SIW_QP_STATE_ERROR;
613 siw_qp_modify(qp, &qp_attrs, SIW_QP_ATTR_STATE);
614
615 if (qp->cep) {
616 siw_cep_put(qp->cep);
617 qp->cep = NULL;
618 }
619 up_write(&qp->state_lock);
620
621 kfree(qp->tx_ctx.mpa_crc_hd);
622 kfree(qp->rx_stream.mpa_crc_hd);
623
624 qp->scq = qp->rcq = NULL;
625
626 siw_qp_put(qp);
627 wait_for_completion(&qp->qp_free);
628
629 return 0;
630 }
631
632 /*
633 * siw_copy_inline_sgl()
634 *
635 * Prepare sgl of inlined data for sending. For userland callers
636 * function checks if given buffer addresses and len's are within
637 * process context bounds.
638 * Data from all provided sge's are copied together into the wqe,
639 * referenced by a single sge.
640 */
siw_copy_inline_sgl(const struct ib_send_wr * core_wr,struct siw_sqe * sqe)641 static int siw_copy_inline_sgl(const struct ib_send_wr *core_wr,
642 struct siw_sqe *sqe)
643 {
644 struct ib_sge *core_sge = core_wr->sg_list;
645 void *kbuf = &sqe->sge[1];
646 int num_sge = core_wr->num_sge, bytes = 0;
647
648 sqe->sge[0].laddr = (uintptr_t)kbuf;
649 sqe->sge[0].lkey = 0;
650
651 while (num_sge--) {
652 if (!core_sge->length) {
653 core_sge++;
654 continue;
655 }
656 bytes += core_sge->length;
657 if (bytes > SIW_MAX_INLINE) {
658 bytes = -EINVAL;
659 break;
660 }
661 memcpy(kbuf, (void *)(uintptr_t)core_sge->addr,
662 core_sge->length);
663
664 kbuf += core_sge->length;
665 core_sge++;
666 }
667 sqe->sge[0].length = bytes > 0 ? bytes : 0;
668 sqe->num_sge = bytes > 0 ? 1 : 0;
669
670 return bytes;
671 }
672
673 /* Complete SQ WR's without processing */
siw_sq_flush_wr(struct siw_qp * qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)674 static int siw_sq_flush_wr(struct siw_qp *qp, const struct ib_send_wr *wr,
675 const struct ib_send_wr **bad_wr)
676 {
677 int rv = 0;
678
679 while (wr) {
680 struct siw_sqe sqe = {};
681
682 switch (wr->opcode) {
683 case IB_WR_RDMA_WRITE:
684 sqe.opcode = SIW_OP_WRITE;
685 break;
686 case IB_WR_RDMA_READ:
687 sqe.opcode = SIW_OP_READ;
688 break;
689 case IB_WR_RDMA_READ_WITH_INV:
690 sqe.opcode = SIW_OP_READ_LOCAL_INV;
691 break;
692 case IB_WR_SEND:
693 sqe.opcode = SIW_OP_SEND;
694 break;
695 case IB_WR_SEND_WITH_IMM:
696 sqe.opcode = SIW_OP_SEND_WITH_IMM;
697 break;
698 case IB_WR_SEND_WITH_INV:
699 sqe.opcode = SIW_OP_SEND_REMOTE_INV;
700 break;
701 case IB_WR_LOCAL_INV:
702 sqe.opcode = SIW_OP_INVAL_STAG;
703 break;
704 case IB_WR_REG_MR:
705 sqe.opcode = SIW_OP_REG_MR;
706 break;
707 default:
708 rv = -EINVAL;
709 break;
710 }
711 if (!rv) {
712 sqe.id = wr->wr_id;
713 rv = siw_sqe_complete(qp, &sqe, 0,
714 SIW_WC_WR_FLUSH_ERR);
715 }
716 if (rv) {
717 if (bad_wr)
718 *bad_wr = wr;
719 break;
720 }
721 wr = wr->next;
722 }
723 return rv;
724 }
725
726 /* Complete RQ WR's without processing */
siw_rq_flush_wr(struct siw_qp * qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)727 static int siw_rq_flush_wr(struct siw_qp *qp, const struct ib_recv_wr *wr,
728 const struct ib_recv_wr **bad_wr)
729 {
730 struct siw_rqe rqe = {};
731 int rv = 0;
732
733 while (wr) {
734 rqe.id = wr->wr_id;
735 rv = siw_rqe_complete(qp, &rqe, 0, 0, SIW_WC_WR_FLUSH_ERR);
736 if (rv) {
737 if (bad_wr)
738 *bad_wr = wr;
739 break;
740 }
741 wr = wr->next;
742 }
743 return rv;
744 }
745
746 /*
747 * siw_post_send()
748 *
749 * Post a list of S-WR's to a SQ.
750 *
751 * @base_qp: Base QP contained in siw QP
752 * @wr: Null terminated list of user WR's
753 * @bad_wr: Points to failing WR in case of synchronous failure.
754 */
siw_post_send(struct ib_qp * base_qp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)755 int siw_post_send(struct ib_qp *base_qp, const struct ib_send_wr *wr,
756 const struct ib_send_wr **bad_wr)
757 {
758 struct siw_qp *qp = to_siw_qp(base_qp);
759 struct siw_wqe *wqe = tx_wqe(qp);
760
761 unsigned long flags;
762 int rv = 0;
763
764 if (wr && !rdma_is_kernel_res(&qp->base_qp.res)) {
765 siw_dbg_qp(qp, "wr must be empty for user mapped sq\n");
766 *bad_wr = wr;
767 return -EINVAL;
768 }
769
770 /*
771 * Try to acquire QP state lock. Must be non-blocking
772 * to accommodate kernel clients needs.
773 */
774 if (!down_read_trylock(&qp->state_lock)) {
775 if (qp->attrs.state == SIW_QP_STATE_ERROR) {
776 /*
777 * ERROR state is final, so we can be sure
778 * this state will not change as long as the QP
779 * exists.
780 *
781 * This handles an ib_drain_sq() call with
782 * a concurrent request to set the QP state
783 * to ERROR.
784 */
785 rv = siw_sq_flush_wr(qp, wr, bad_wr);
786 } else {
787 siw_dbg_qp(qp, "QP locked, state %d\n",
788 qp->attrs.state);
789 *bad_wr = wr;
790 rv = -ENOTCONN;
791 }
792 return rv;
793 }
794 if (unlikely(qp->attrs.state != SIW_QP_STATE_RTS)) {
795 if (qp->attrs.state == SIW_QP_STATE_ERROR) {
796 /*
797 * Immediately flush this WR to CQ, if QP
798 * is in ERROR state. SQ is guaranteed to
799 * be empty, so WR complets in-order.
800 *
801 * Typically triggered by ib_drain_sq().
802 */
803 rv = siw_sq_flush_wr(qp, wr, bad_wr);
804 } else {
805 siw_dbg_qp(qp, "QP out of state %d\n",
806 qp->attrs.state);
807 *bad_wr = wr;
808 rv = -ENOTCONN;
809 }
810 up_read(&qp->state_lock);
811 return rv;
812 }
813 spin_lock_irqsave(&qp->sq_lock, flags);
814
815 while (wr) {
816 u32 idx = qp->sq_put % qp->attrs.sq_size;
817 struct siw_sqe *sqe = &qp->sendq[idx];
818
819 if (sqe->flags) {
820 siw_dbg_qp(qp, "sq full\n");
821 rv = -ENOMEM;
822 break;
823 }
824 if (wr->num_sge > qp->attrs.sq_max_sges) {
825 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge);
826 rv = -EINVAL;
827 break;
828 }
829 sqe->id = wr->wr_id;
830
831 if ((wr->send_flags & IB_SEND_SIGNALED) ||
832 (qp->attrs.flags & SIW_SIGNAL_ALL_WR))
833 sqe->flags |= SIW_WQE_SIGNALLED;
834
835 if (wr->send_flags & IB_SEND_FENCE)
836 sqe->flags |= SIW_WQE_READ_FENCE;
837
838 switch (wr->opcode) {
839 case IB_WR_SEND:
840 case IB_WR_SEND_WITH_INV:
841 if (wr->send_flags & IB_SEND_SOLICITED)
842 sqe->flags |= SIW_WQE_SOLICITED;
843
844 if (!(wr->send_flags & IB_SEND_INLINE)) {
845 siw_copy_sgl(wr->sg_list, sqe->sge,
846 wr->num_sge);
847 sqe->num_sge = wr->num_sge;
848 } else {
849 rv = siw_copy_inline_sgl(wr, sqe);
850 if (rv <= 0) {
851 rv = -EINVAL;
852 break;
853 }
854 sqe->flags |= SIW_WQE_INLINE;
855 sqe->num_sge = 1;
856 }
857 if (wr->opcode == IB_WR_SEND)
858 sqe->opcode = SIW_OP_SEND;
859 else {
860 sqe->opcode = SIW_OP_SEND_REMOTE_INV;
861 sqe->rkey = wr->ex.invalidate_rkey;
862 }
863 break;
864
865 case IB_WR_RDMA_READ_WITH_INV:
866 case IB_WR_RDMA_READ:
867 /*
868 * iWarp restricts RREAD sink to SGL containing
869 * 1 SGE only. we could relax to SGL with multiple
870 * elements referring the SAME ltag or even sending
871 * a private per-rreq tag referring to a checked
872 * local sgl with MULTIPLE ltag's.
873 */
874 if (unlikely(wr->num_sge != 1)) {
875 rv = -EINVAL;
876 break;
877 }
878 siw_copy_sgl(wr->sg_list, &sqe->sge[0], 1);
879 /*
880 * NOTE: zero length RREAD is allowed!
881 */
882 sqe->raddr = rdma_wr(wr)->remote_addr;
883 sqe->rkey = rdma_wr(wr)->rkey;
884 sqe->num_sge = 1;
885
886 if (wr->opcode == IB_WR_RDMA_READ)
887 sqe->opcode = SIW_OP_READ;
888 else
889 sqe->opcode = SIW_OP_READ_LOCAL_INV;
890 break;
891
892 case IB_WR_RDMA_WRITE:
893 if (!(wr->send_flags & IB_SEND_INLINE)) {
894 siw_copy_sgl(wr->sg_list, &sqe->sge[0],
895 wr->num_sge);
896 sqe->num_sge = wr->num_sge;
897 } else {
898 rv = siw_copy_inline_sgl(wr, sqe);
899 if (unlikely(rv < 0)) {
900 rv = -EINVAL;
901 break;
902 }
903 sqe->flags |= SIW_WQE_INLINE;
904 sqe->num_sge = 1;
905 }
906 sqe->raddr = rdma_wr(wr)->remote_addr;
907 sqe->rkey = rdma_wr(wr)->rkey;
908 sqe->opcode = SIW_OP_WRITE;
909 break;
910
911 case IB_WR_REG_MR:
912 sqe->base_mr = (uintptr_t)reg_wr(wr)->mr;
913 sqe->rkey = reg_wr(wr)->key;
914 sqe->access = reg_wr(wr)->access & IWARP_ACCESS_MASK;
915 sqe->opcode = SIW_OP_REG_MR;
916 break;
917
918 case IB_WR_LOCAL_INV:
919 sqe->rkey = wr->ex.invalidate_rkey;
920 sqe->opcode = SIW_OP_INVAL_STAG;
921 break;
922
923 default:
924 siw_dbg_qp(qp, "ib wr type %d unsupported\n",
925 wr->opcode);
926 rv = -EINVAL;
927 break;
928 }
929 siw_dbg_qp(qp, "opcode %d, flags 0x%x, wr_id 0x%pK\n",
930 sqe->opcode, sqe->flags,
931 (void *)(uintptr_t)sqe->id);
932
933 if (unlikely(rv < 0))
934 break;
935
936 /* make SQE only valid after completely written */
937 smp_wmb();
938 sqe->flags |= SIW_WQE_VALID;
939
940 qp->sq_put++;
941 wr = wr->next;
942 }
943
944 /*
945 * Send directly if SQ processing is not in progress.
946 * Eventual immediate errors (rv < 0) do not affect the involved
947 * RI resources (Verbs, 8.3.1) and thus do not prevent from SQ
948 * processing, if new work is already pending. But rv must be passed
949 * to caller.
950 */
951 if (wqe->wr_status != SIW_WR_IDLE) {
952 spin_unlock_irqrestore(&qp->sq_lock, flags);
953 goto skip_direct_sending;
954 }
955 rv = siw_activate_tx(qp);
956 spin_unlock_irqrestore(&qp->sq_lock, flags);
957
958 if (rv <= 0)
959 goto skip_direct_sending;
960
961 if (rdma_is_kernel_res(&qp->base_qp.res)) {
962 rv = siw_sq_start(qp);
963 } else {
964 qp->tx_ctx.in_syscall = 1;
965
966 if (siw_qp_sq_process(qp) != 0 && !(qp->tx_ctx.tx_suspend))
967 siw_qp_cm_drop(qp, 0);
968
969 qp->tx_ctx.in_syscall = 0;
970 }
971 skip_direct_sending:
972
973 up_read(&qp->state_lock);
974
975 if (rv >= 0)
976 return 0;
977 /*
978 * Immediate error
979 */
980 siw_dbg_qp(qp, "error %d\n", rv);
981
982 *bad_wr = wr;
983 return rv;
984 }
985
986 /*
987 * siw_post_receive()
988 *
989 * Post a list of R-WR's to a RQ.
990 *
991 * @base_qp: Base QP contained in siw QP
992 * @wr: Null terminated list of user WR's
993 * @bad_wr: Points to failing WR in case of synchronous failure.
994 */
siw_post_receive(struct ib_qp * base_qp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)995 int siw_post_receive(struct ib_qp *base_qp, const struct ib_recv_wr *wr,
996 const struct ib_recv_wr **bad_wr)
997 {
998 struct siw_qp *qp = to_siw_qp(base_qp);
999 unsigned long flags;
1000 int rv = 0;
1001
1002 if (qp->srq || qp->attrs.rq_size == 0) {
1003 *bad_wr = wr;
1004 return -EINVAL;
1005 }
1006 if (!rdma_is_kernel_res(&qp->base_qp.res)) {
1007 siw_dbg_qp(qp, "no kernel post_recv for user mapped rq\n");
1008 *bad_wr = wr;
1009 return -EINVAL;
1010 }
1011
1012 /*
1013 * Try to acquire QP state lock. Must be non-blocking
1014 * to accommodate kernel clients needs.
1015 */
1016 if (!down_read_trylock(&qp->state_lock)) {
1017 if (qp->attrs.state == SIW_QP_STATE_ERROR) {
1018 /*
1019 * ERROR state is final, so we can be sure
1020 * this state will not change as long as the QP
1021 * exists.
1022 *
1023 * This handles an ib_drain_rq() call with
1024 * a concurrent request to set the QP state
1025 * to ERROR.
1026 */
1027 rv = siw_rq_flush_wr(qp, wr, bad_wr);
1028 } else {
1029 siw_dbg_qp(qp, "QP locked, state %d\n",
1030 qp->attrs.state);
1031 *bad_wr = wr;
1032 rv = -ENOTCONN;
1033 }
1034 return rv;
1035 }
1036 if (qp->attrs.state > SIW_QP_STATE_RTS) {
1037 if (qp->attrs.state == SIW_QP_STATE_ERROR) {
1038 /*
1039 * Immediately flush this WR to CQ, if QP
1040 * is in ERROR state. RQ is guaranteed to
1041 * be empty, so WR complets in-order.
1042 *
1043 * Typically triggered by ib_drain_rq().
1044 */
1045 rv = siw_rq_flush_wr(qp, wr, bad_wr);
1046 } else {
1047 siw_dbg_qp(qp, "QP out of state %d\n",
1048 qp->attrs.state);
1049 *bad_wr = wr;
1050 rv = -ENOTCONN;
1051 }
1052 up_read(&qp->state_lock);
1053 return rv;
1054 }
1055 /*
1056 * Serialize potentially multiple producers.
1057 * Not needed for single threaded consumer side.
1058 */
1059 spin_lock_irqsave(&qp->rq_lock, flags);
1060
1061 while (wr) {
1062 u32 idx = qp->rq_put % qp->attrs.rq_size;
1063 struct siw_rqe *rqe = &qp->recvq[idx];
1064
1065 if (rqe->flags) {
1066 siw_dbg_qp(qp, "RQ full\n");
1067 rv = -ENOMEM;
1068 break;
1069 }
1070 if (wr->num_sge > qp->attrs.rq_max_sges) {
1071 siw_dbg_qp(qp, "too many sge's: %d\n", wr->num_sge);
1072 rv = -EINVAL;
1073 break;
1074 }
1075 rqe->id = wr->wr_id;
1076 rqe->num_sge = wr->num_sge;
1077 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge);
1078
1079 /* make sure RQE is completely written before valid */
1080 smp_wmb();
1081
1082 rqe->flags = SIW_WQE_VALID;
1083
1084 qp->rq_put++;
1085 wr = wr->next;
1086 }
1087 spin_unlock_irqrestore(&qp->rq_lock, flags);
1088
1089 up_read(&qp->state_lock);
1090
1091 if (rv < 0) {
1092 siw_dbg_qp(qp, "error %d\n", rv);
1093 *bad_wr = wr;
1094 }
1095 return rv > 0 ? 0 : rv;
1096 }
1097
siw_destroy_cq(struct ib_cq * base_cq,struct ib_udata * udata)1098 int siw_destroy_cq(struct ib_cq *base_cq, struct ib_udata *udata)
1099 {
1100 struct siw_cq *cq = to_siw_cq(base_cq);
1101 struct siw_device *sdev = to_siw_dev(base_cq->device);
1102 struct siw_ucontext *ctx =
1103 rdma_udata_to_drv_context(udata, struct siw_ucontext,
1104 base_ucontext);
1105
1106 siw_dbg_cq(cq, "free CQ resources\n");
1107
1108 siw_cq_flush(cq);
1109
1110 if (ctx)
1111 rdma_user_mmap_entry_remove(cq->cq_entry);
1112
1113 atomic_dec(&sdev->num_cq);
1114
1115 vfree(cq->queue);
1116 return 0;
1117 }
1118
1119 /*
1120 * siw_create_cq()
1121 *
1122 * Populate CQ of requested size
1123 *
1124 * @base_cq: CQ as allocated by RDMA midlayer
1125 * @attr: Initial CQ attributes
1126 * @udata: relates to user context
1127 */
1128
siw_create_cq(struct ib_cq * base_cq,const struct ib_cq_init_attr * attr,struct ib_udata * udata)1129 int siw_create_cq(struct ib_cq *base_cq, const struct ib_cq_init_attr *attr,
1130 struct ib_udata *udata)
1131 {
1132 struct siw_device *sdev = to_siw_dev(base_cq->device);
1133 struct siw_cq *cq = to_siw_cq(base_cq);
1134 int rv, size = attr->cqe;
1135
1136 if (attr->flags)
1137 return -EOPNOTSUPP;
1138
1139 if (atomic_inc_return(&sdev->num_cq) > SIW_MAX_CQ) {
1140 siw_dbg(base_cq->device, "too many CQ's\n");
1141 rv = -ENOMEM;
1142 goto err_out;
1143 }
1144 if (size < 1 || size > sdev->attrs.max_cqe) {
1145 siw_dbg(base_cq->device, "CQ size error: %d\n", size);
1146 rv = -EINVAL;
1147 goto err_out;
1148 }
1149 size = roundup_pow_of_two(size);
1150 cq->base_cq.cqe = size;
1151 cq->num_cqe = size;
1152
1153 if (udata)
1154 cq->queue = vmalloc_user(size * sizeof(struct siw_cqe) +
1155 sizeof(struct siw_cq_ctrl));
1156 else
1157 cq->queue = vzalloc(size * sizeof(struct siw_cqe) +
1158 sizeof(struct siw_cq_ctrl));
1159
1160 if (cq->queue == NULL) {
1161 rv = -ENOMEM;
1162 goto err_out;
1163 }
1164 get_random_bytes(&cq->id, 4);
1165 siw_dbg(base_cq->device, "new CQ [%u]\n", cq->id);
1166
1167 spin_lock_init(&cq->lock);
1168
1169 cq->notify = (struct siw_cq_ctrl *)&cq->queue[size];
1170
1171 if (udata) {
1172 struct siw_uresp_create_cq uresp = {};
1173 struct siw_ucontext *ctx =
1174 rdma_udata_to_drv_context(udata, struct siw_ucontext,
1175 base_ucontext);
1176 size_t length = size * sizeof(struct siw_cqe) +
1177 sizeof(struct siw_cq_ctrl);
1178
1179 cq->cq_entry =
1180 siw_mmap_entry_insert(ctx, cq->queue,
1181 length, &uresp.cq_key);
1182 if (!cq->cq_entry) {
1183 rv = -ENOMEM;
1184 goto err_out;
1185 }
1186
1187 uresp.cq_id = cq->id;
1188 uresp.num_cqe = size;
1189
1190 if (udata->outlen < sizeof(uresp)) {
1191 rv = -EINVAL;
1192 goto err_out;
1193 }
1194 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
1195 if (rv)
1196 goto err_out;
1197 }
1198 return 0;
1199
1200 err_out:
1201 siw_dbg(base_cq->device, "CQ creation failed: %d", rv);
1202
1203 if (cq && cq->queue) {
1204 struct siw_ucontext *ctx =
1205 rdma_udata_to_drv_context(udata, struct siw_ucontext,
1206 base_ucontext);
1207 if (ctx)
1208 rdma_user_mmap_entry_remove(cq->cq_entry);
1209 vfree(cq->queue);
1210 }
1211 atomic_dec(&sdev->num_cq);
1212
1213 return rv;
1214 }
1215
1216 /*
1217 * siw_poll_cq()
1218 *
1219 * Reap CQ entries if available and copy work completion status into
1220 * array of WC's provided by caller. Returns number of reaped CQE's.
1221 *
1222 * @base_cq: Base CQ contained in siw CQ.
1223 * @num_cqe: Maximum number of CQE's to reap.
1224 * @wc: Array of work completions to be filled by siw.
1225 */
siw_poll_cq(struct ib_cq * base_cq,int num_cqe,struct ib_wc * wc)1226 int siw_poll_cq(struct ib_cq *base_cq, int num_cqe, struct ib_wc *wc)
1227 {
1228 struct siw_cq *cq = to_siw_cq(base_cq);
1229 int i;
1230
1231 for (i = 0; i < num_cqe; i++) {
1232 if (!siw_reap_cqe(cq, wc))
1233 break;
1234 wc++;
1235 }
1236 return i;
1237 }
1238
1239 /*
1240 * siw_req_notify_cq()
1241 *
1242 * Request notification for new CQE's added to that CQ.
1243 * Defined flags:
1244 * o SIW_CQ_NOTIFY_SOLICITED lets siw trigger a notification
1245 * event if a WQE with notification flag set enters the CQ
1246 * o SIW_CQ_NOTIFY_NEXT_COMP lets siw trigger a notification
1247 * event if a WQE enters the CQ.
1248 * o IB_CQ_REPORT_MISSED_EVENTS: return value will provide the
1249 * number of not reaped CQE's regardless of its notification
1250 * type and current or new CQ notification settings.
1251 *
1252 * @base_cq: Base CQ contained in siw CQ.
1253 * @flags: Requested notification flags.
1254 */
siw_req_notify_cq(struct ib_cq * base_cq,enum ib_cq_notify_flags flags)1255 int siw_req_notify_cq(struct ib_cq *base_cq, enum ib_cq_notify_flags flags)
1256 {
1257 struct siw_cq *cq = to_siw_cq(base_cq);
1258
1259 siw_dbg_cq(cq, "flags: 0x%02x\n", flags);
1260
1261 if ((flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED)
1262 /*
1263 * Enable CQ event for next solicited completion.
1264 * and make it visible to all associated producers.
1265 */
1266 smp_store_mb(cq->notify->flags, SIW_NOTIFY_SOLICITED);
1267 else
1268 /*
1269 * Enable CQ event for any signalled completion.
1270 * and make it visible to all associated producers.
1271 */
1272 smp_store_mb(cq->notify->flags, SIW_NOTIFY_ALL);
1273
1274 if (flags & IB_CQ_REPORT_MISSED_EVENTS)
1275 return cq->cq_put - cq->cq_get;
1276
1277 return 0;
1278 }
1279
1280 /*
1281 * siw_dereg_mr()
1282 *
1283 * Release Memory Region.
1284 *
1285 * @base_mr: Base MR contained in siw MR.
1286 * @udata: points to user context, unused.
1287 */
siw_dereg_mr(struct ib_mr * base_mr,struct ib_udata * udata)1288 int siw_dereg_mr(struct ib_mr *base_mr, struct ib_udata *udata)
1289 {
1290 struct siw_mr *mr = to_siw_mr(base_mr);
1291 struct siw_device *sdev = to_siw_dev(base_mr->device);
1292
1293 siw_dbg_mem(mr->mem, "deregister MR\n");
1294
1295 atomic_dec(&sdev->num_mr);
1296
1297 siw_mr_drop_mem(mr);
1298 kfree_rcu(mr, rcu);
1299
1300 return 0;
1301 }
1302
1303 /*
1304 * siw_reg_user_mr()
1305 *
1306 * Register Memory Region.
1307 *
1308 * @pd: Protection Domain
1309 * @start: starting address of MR (virtual address)
1310 * @len: len of MR
1311 * @rnic_va: not used by siw
1312 * @rights: MR access rights
1313 * @udata: user buffer to communicate STag and Key.
1314 */
siw_reg_user_mr(struct ib_pd * pd,u64 start,u64 len,u64 rnic_va,int rights,struct ib_udata * udata)1315 struct ib_mr *siw_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,
1316 u64 rnic_va, int rights, struct ib_udata *udata)
1317 {
1318 struct siw_mr *mr = NULL;
1319 struct siw_umem *umem = NULL;
1320 struct siw_ureq_reg_mr ureq;
1321 struct siw_device *sdev = to_siw_dev(pd->device);
1322
1323 unsigned long mem_limit = rlimit(RLIMIT_MEMLOCK);
1324 int rv;
1325
1326 siw_dbg_pd(pd, "start: 0x%pK, va: 0x%pK, len: %llu\n",
1327 (void *)(uintptr_t)start, (void *)(uintptr_t)rnic_va,
1328 (unsigned long long)len);
1329
1330 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) {
1331 siw_dbg_pd(pd, "too many mr's\n");
1332 rv = -ENOMEM;
1333 goto err_out;
1334 }
1335 if (!len) {
1336 rv = -EINVAL;
1337 goto err_out;
1338 }
1339 if (mem_limit != RLIM_INFINITY) {
1340 unsigned long num_pages =
1341 (PAGE_ALIGN(len + (start & ~PAGE_MASK))) >> PAGE_SHIFT;
1342 mem_limit >>= PAGE_SHIFT;
1343
1344 if (num_pages > mem_limit - current->mm->locked_vm) {
1345 siw_dbg_pd(pd, "pages req %lu, max %lu, lock %lu\n",
1346 num_pages, mem_limit,
1347 current->mm->locked_vm);
1348 rv = -ENOMEM;
1349 goto err_out;
1350 }
1351 }
1352 umem = siw_umem_get(start, len, ib_access_writable(rights));
1353 if (IS_ERR(umem)) {
1354 rv = PTR_ERR(umem);
1355 siw_dbg_pd(pd, "getting user memory failed: %d\n", rv);
1356 umem = NULL;
1357 goto err_out;
1358 }
1359 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1360 if (!mr) {
1361 rv = -ENOMEM;
1362 goto err_out;
1363 }
1364 rv = siw_mr_add_mem(mr, pd, umem, start, len, rights);
1365 if (rv)
1366 goto err_out;
1367
1368 if (udata) {
1369 struct siw_uresp_reg_mr uresp = {};
1370 struct siw_mem *mem = mr->mem;
1371
1372 if (udata->inlen < sizeof(ureq)) {
1373 rv = -EINVAL;
1374 goto err_out;
1375 }
1376 rv = ib_copy_from_udata(&ureq, udata, sizeof(ureq));
1377 if (rv)
1378 goto err_out;
1379
1380 mr->base_mr.lkey |= ureq.stag_key;
1381 mr->base_mr.rkey |= ureq.stag_key;
1382 mem->stag |= ureq.stag_key;
1383 uresp.stag = mem->stag;
1384
1385 if (udata->outlen < sizeof(uresp)) {
1386 rv = -EINVAL;
1387 goto err_out;
1388 }
1389 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
1390 if (rv)
1391 goto err_out;
1392 }
1393 mr->mem->stag_valid = 1;
1394
1395 return &mr->base_mr;
1396
1397 err_out:
1398 atomic_dec(&sdev->num_mr);
1399 if (mr) {
1400 if (mr->mem)
1401 siw_mr_drop_mem(mr);
1402 kfree_rcu(mr, rcu);
1403 } else {
1404 if (umem)
1405 siw_umem_release(umem, false);
1406 }
1407 return ERR_PTR(rv);
1408 }
1409
siw_alloc_mr(struct ib_pd * pd,enum ib_mr_type mr_type,u32 max_sge)1410 struct ib_mr *siw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1411 u32 max_sge)
1412 {
1413 struct siw_device *sdev = to_siw_dev(pd->device);
1414 struct siw_mr *mr = NULL;
1415 struct siw_pbl *pbl = NULL;
1416 int rv;
1417
1418 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) {
1419 siw_dbg_pd(pd, "too many mr's\n");
1420 rv = -ENOMEM;
1421 goto err_out;
1422 }
1423 if (mr_type != IB_MR_TYPE_MEM_REG) {
1424 siw_dbg_pd(pd, "mr type %d unsupported\n", mr_type);
1425 rv = -EOPNOTSUPP;
1426 goto err_out;
1427 }
1428 if (max_sge > SIW_MAX_SGE_PBL) {
1429 siw_dbg_pd(pd, "too many sge's: %d\n", max_sge);
1430 rv = -ENOMEM;
1431 goto err_out;
1432 }
1433 pbl = siw_pbl_alloc(max_sge);
1434 if (IS_ERR(pbl)) {
1435 rv = PTR_ERR(pbl);
1436 siw_dbg_pd(pd, "pbl allocation failed: %d\n", rv);
1437 pbl = NULL;
1438 goto err_out;
1439 }
1440 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1441 if (!mr) {
1442 rv = -ENOMEM;
1443 goto err_out;
1444 }
1445 rv = siw_mr_add_mem(mr, pd, pbl, 0, max_sge * PAGE_SIZE, 0);
1446 if (rv)
1447 goto err_out;
1448
1449 mr->mem->is_pbl = 1;
1450
1451 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag);
1452
1453 return &mr->base_mr;
1454
1455 err_out:
1456 atomic_dec(&sdev->num_mr);
1457
1458 if (!mr) {
1459 kfree(pbl);
1460 } else {
1461 if (mr->mem)
1462 siw_mr_drop_mem(mr);
1463 kfree_rcu(mr, rcu);
1464 }
1465 siw_dbg_pd(pd, "failed: %d\n", rv);
1466
1467 return ERR_PTR(rv);
1468 }
1469
1470 /* Just used to count number of pages being mapped */
siw_set_pbl_page(struct ib_mr * base_mr,u64 buf_addr)1471 static int siw_set_pbl_page(struct ib_mr *base_mr, u64 buf_addr)
1472 {
1473 return 0;
1474 }
1475
siw_map_mr_sg(struct ib_mr * base_mr,struct scatterlist * sl,int num_sle,unsigned int * sg_off)1476 int siw_map_mr_sg(struct ib_mr *base_mr, struct scatterlist *sl, int num_sle,
1477 unsigned int *sg_off)
1478 {
1479 struct scatterlist *slp;
1480 struct siw_mr *mr = to_siw_mr(base_mr);
1481 struct siw_mem *mem = mr->mem;
1482 struct siw_pbl *pbl = mem->pbl;
1483 struct siw_pble *pble;
1484 unsigned long pbl_size;
1485 int i, rv;
1486
1487 if (!pbl) {
1488 siw_dbg_mem(mem, "no PBL allocated\n");
1489 return -EINVAL;
1490 }
1491 pble = pbl->pbe;
1492
1493 if (pbl->max_buf < num_sle) {
1494 siw_dbg_mem(mem, "too many SGE's: %d > %d\n",
1495 num_sle, pbl->max_buf);
1496 return -ENOMEM;
1497 }
1498 for_each_sg(sl, slp, num_sle, i) {
1499 if (sg_dma_len(slp) == 0) {
1500 siw_dbg_mem(mem, "empty SGE\n");
1501 return -EINVAL;
1502 }
1503 if (i == 0) {
1504 pble->addr = sg_dma_address(slp);
1505 pble->size = sg_dma_len(slp);
1506 pble->pbl_off = 0;
1507 pbl_size = pble->size;
1508 pbl->num_buf = 1;
1509 } else {
1510 /* Merge PBL entries if adjacent */
1511 if (pble->addr + pble->size == sg_dma_address(slp)) {
1512 pble->size += sg_dma_len(slp);
1513 } else {
1514 pble++;
1515 pbl->num_buf++;
1516 pble->addr = sg_dma_address(slp);
1517 pble->size = sg_dma_len(slp);
1518 pble->pbl_off = pbl_size;
1519 }
1520 pbl_size += sg_dma_len(slp);
1521 }
1522 siw_dbg_mem(mem,
1523 "sge[%d], size %u, addr 0x%p, total %lu\n",
1524 i, pble->size, (void *)(uintptr_t)pble->addr,
1525 pbl_size);
1526 }
1527 rv = ib_sg_to_pages(base_mr, sl, num_sle, sg_off, siw_set_pbl_page);
1528 if (rv > 0) {
1529 mem->len = base_mr->length;
1530 mem->va = base_mr->iova;
1531 siw_dbg_mem(mem,
1532 "%llu bytes, start 0x%pK, %u SLE to %u entries\n",
1533 mem->len, (void *)(uintptr_t)mem->va, num_sle,
1534 pbl->num_buf);
1535 }
1536 return rv;
1537 }
1538
1539 /*
1540 * siw_get_dma_mr()
1541 *
1542 * Create a (empty) DMA memory region, where no umem is attached.
1543 */
siw_get_dma_mr(struct ib_pd * pd,int rights)1544 struct ib_mr *siw_get_dma_mr(struct ib_pd *pd, int rights)
1545 {
1546 struct siw_device *sdev = to_siw_dev(pd->device);
1547 struct siw_mr *mr = NULL;
1548 int rv;
1549
1550 if (atomic_inc_return(&sdev->num_mr) > SIW_MAX_MR) {
1551 siw_dbg_pd(pd, "too many mr's\n");
1552 rv = -ENOMEM;
1553 goto err_out;
1554 }
1555 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1556 if (!mr) {
1557 rv = -ENOMEM;
1558 goto err_out;
1559 }
1560 rv = siw_mr_add_mem(mr, pd, NULL, 0, ULONG_MAX, rights);
1561 if (rv)
1562 goto err_out;
1563
1564 mr->mem->stag_valid = 1;
1565
1566 siw_dbg_pd(pd, "[MEM %u]: success\n", mr->mem->stag);
1567
1568 return &mr->base_mr;
1569
1570 err_out:
1571 if (rv)
1572 kfree(mr);
1573
1574 atomic_dec(&sdev->num_mr);
1575
1576 return ERR_PTR(rv);
1577 }
1578
1579 /*
1580 * siw_create_srq()
1581 *
1582 * Create Shared Receive Queue of attributes @init_attrs
1583 * within protection domain given by @pd.
1584 *
1585 * @base_srq: Base SRQ contained in siw SRQ.
1586 * @init_attrs: SRQ init attributes.
1587 * @udata: points to user context
1588 */
siw_create_srq(struct ib_srq * base_srq,struct ib_srq_init_attr * init_attrs,struct ib_udata * udata)1589 int siw_create_srq(struct ib_srq *base_srq,
1590 struct ib_srq_init_attr *init_attrs, struct ib_udata *udata)
1591 {
1592 struct siw_srq *srq = to_siw_srq(base_srq);
1593 struct ib_srq_attr *attrs = &init_attrs->attr;
1594 struct siw_device *sdev = to_siw_dev(base_srq->device);
1595 struct siw_ucontext *ctx =
1596 rdma_udata_to_drv_context(udata, struct siw_ucontext,
1597 base_ucontext);
1598 int rv;
1599
1600 if (init_attrs->srq_type != IB_SRQT_BASIC)
1601 return -EOPNOTSUPP;
1602
1603 if (atomic_inc_return(&sdev->num_srq) > SIW_MAX_SRQ) {
1604 siw_dbg_pd(base_srq->pd, "too many SRQ's\n");
1605 rv = -ENOMEM;
1606 goto err_out;
1607 }
1608 if (attrs->max_wr == 0 || attrs->max_wr > SIW_MAX_SRQ_WR ||
1609 attrs->max_sge > SIW_MAX_SGE || attrs->srq_limit > attrs->max_wr) {
1610 rv = -EINVAL;
1611 goto err_out;
1612 }
1613 srq->max_sge = attrs->max_sge;
1614 srq->num_rqe = roundup_pow_of_two(attrs->max_wr);
1615 srq->limit = attrs->srq_limit;
1616 if (srq->limit)
1617 srq->armed = true;
1618
1619 srq->is_kernel_res = !udata;
1620
1621 if (udata)
1622 srq->recvq =
1623 vmalloc_user(srq->num_rqe * sizeof(struct siw_rqe));
1624 else
1625 srq->recvq = vzalloc(srq->num_rqe * sizeof(struct siw_rqe));
1626
1627 if (srq->recvq == NULL) {
1628 rv = -ENOMEM;
1629 goto err_out;
1630 }
1631 if (udata) {
1632 struct siw_uresp_create_srq uresp = {};
1633 size_t length = srq->num_rqe * sizeof(struct siw_rqe);
1634
1635 srq->srq_entry =
1636 siw_mmap_entry_insert(ctx, srq->recvq,
1637 length, &uresp.srq_key);
1638 if (!srq->srq_entry) {
1639 rv = -ENOMEM;
1640 goto err_out;
1641 }
1642
1643 uresp.num_rqe = srq->num_rqe;
1644
1645 if (udata->outlen < sizeof(uresp)) {
1646 rv = -EINVAL;
1647 goto err_out;
1648 }
1649 rv = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
1650 if (rv)
1651 goto err_out;
1652 }
1653 spin_lock_init(&srq->lock);
1654
1655 siw_dbg_pd(base_srq->pd, "[SRQ]: success\n");
1656
1657 return 0;
1658
1659 err_out:
1660 if (srq->recvq) {
1661 if (ctx)
1662 rdma_user_mmap_entry_remove(srq->srq_entry);
1663 vfree(srq->recvq);
1664 }
1665 atomic_dec(&sdev->num_srq);
1666
1667 return rv;
1668 }
1669
1670 /*
1671 * siw_modify_srq()
1672 *
1673 * Modify SRQ. The caller may resize SRQ and/or set/reset notification
1674 * limit and (re)arm IB_EVENT_SRQ_LIMIT_REACHED notification.
1675 *
1676 * NOTE: it is unclear if RDMA core allows for changing the MAX_SGE
1677 * parameter. siw_modify_srq() does not check the attrs->max_sge param.
1678 */
siw_modify_srq(struct ib_srq * base_srq,struct ib_srq_attr * attrs,enum ib_srq_attr_mask attr_mask,struct ib_udata * udata)1679 int siw_modify_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs,
1680 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1681 {
1682 struct siw_srq *srq = to_siw_srq(base_srq);
1683 unsigned long flags;
1684 int rv = 0;
1685
1686 spin_lock_irqsave(&srq->lock, flags);
1687
1688 if (attr_mask & IB_SRQ_MAX_WR) {
1689 /* resize request not yet supported */
1690 rv = -EOPNOTSUPP;
1691 goto out;
1692 }
1693 if (attr_mask & IB_SRQ_LIMIT) {
1694 if (attrs->srq_limit) {
1695 if (unlikely(attrs->srq_limit > srq->num_rqe)) {
1696 rv = -EINVAL;
1697 goto out;
1698 }
1699 srq->armed = true;
1700 } else {
1701 srq->armed = false;
1702 }
1703 srq->limit = attrs->srq_limit;
1704 }
1705 out:
1706 spin_unlock_irqrestore(&srq->lock, flags);
1707
1708 return rv;
1709 }
1710
1711 /*
1712 * siw_query_srq()
1713 *
1714 * Query SRQ attributes.
1715 */
siw_query_srq(struct ib_srq * base_srq,struct ib_srq_attr * attrs)1716 int siw_query_srq(struct ib_srq *base_srq, struct ib_srq_attr *attrs)
1717 {
1718 struct siw_srq *srq = to_siw_srq(base_srq);
1719 unsigned long flags;
1720
1721 spin_lock_irqsave(&srq->lock, flags);
1722
1723 attrs->max_wr = srq->num_rqe;
1724 attrs->max_sge = srq->max_sge;
1725 attrs->srq_limit = srq->limit;
1726
1727 spin_unlock_irqrestore(&srq->lock, flags);
1728
1729 return 0;
1730 }
1731
1732 /*
1733 * siw_destroy_srq()
1734 *
1735 * Destroy SRQ.
1736 * It is assumed that the SRQ is not referenced by any
1737 * QP anymore - the code trusts the RDMA core environment to keep track
1738 * of QP references.
1739 */
siw_destroy_srq(struct ib_srq * base_srq,struct ib_udata * udata)1740 int siw_destroy_srq(struct ib_srq *base_srq, struct ib_udata *udata)
1741 {
1742 struct siw_srq *srq = to_siw_srq(base_srq);
1743 struct siw_device *sdev = to_siw_dev(base_srq->device);
1744 struct siw_ucontext *ctx =
1745 rdma_udata_to_drv_context(udata, struct siw_ucontext,
1746 base_ucontext);
1747
1748 if (ctx)
1749 rdma_user_mmap_entry_remove(srq->srq_entry);
1750 vfree(srq->recvq);
1751 atomic_dec(&sdev->num_srq);
1752 return 0;
1753 }
1754
1755 /*
1756 * siw_post_srq_recv()
1757 *
1758 * Post a list of receive queue elements to SRQ.
1759 * NOTE: The function does not check or lock a certain SRQ state
1760 * during the post operation. The code simply trusts the
1761 * RDMA core environment.
1762 *
1763 * @base_srq: Base SRQ contained in siw SRQ
1764 * @wr: List of R-WR's
1765 * @bad_wr: Updated to failing WR if posting fails.
1766 */
siw_post_srq_recv(struct ib_srq * base_srq,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)1767 int siw_post_srq_recv(struct ib_srq *base_srq, const struct ib_recv_wr *wr,
1768 const struct ib_recv_wr **bad_wr)
1769 {
1770 struct siw_srq *srq = to_siw_srq(base_srq);
1771 unsigned long flags;
1772 int rv = 0;
1773
1774 if (unlikely(!srq->is_kernel_res)) {
1775 siw_dbg_pd(base_srq->pd,
1776 "[SRQ]: no kernel post_recv for mapped srq\n");
1777 rv = -EINVAL;
1778 goto out;
1779 }
1780 /*
1781 * Serialize potentially multiple producers.
1782 * Also needed to serialize potentially multiple
1783 * consumers.
1784 */
1785 spin_lock_irqsave(&srq->lock, flags);
1786
1787 while (wr) {
1788 u32 idx = srq->rq_put % srq->num_rqe;
1789 struct siw_rqe *rqe = &srq->recvq[idx];
1790
1791 if (rqe->flags) {
1792 siw_dbg_pd(base_srq->pd, "SRQ full\n");
1793 rv = -ENOMEM;
1794 break;
1795 }
1796 if (unlikely(wr->num_sge > srq->max_sge)) {
1797 siw_dbg_pd(base_srq->pd,
1798 "[SRQ]: too many sge's: %d\n", wr->num_sge);
1799 rv = -EINVAL;
1800 break;
1801 }
1802 rqe->id = wr->wr_id;
1803 rqe->num_sge = wr->num_sge;
1804 siw_copy_sgl(wr->sg_list, rqe->sge, wr->num_sge);
1805
1806 /* Make sure S-RQE is completely written before valid */
1807 smp_wmb();
1808
1809 rqe->flags = SIW_WQE_VALID;
1810
1811 srq->rq_put++;
1812 wr = wr->next;
1813 }
1814 spin_unlock_irqrestore(&srq->lock, flags);
1815 out:
1816 if (unlikely(rv < 0)) {
1817 siw_dbg_pd(base_srq->pd, "[SRQ]: error %d\n", rv);
1818 *bad_wr = wr;
1819 }
1820 return rv;
1821 }
1822
siw_qp_event(struct siw_qp * qp,enum ib_event_type etype)1823 void siw_qp_event(struct siw_qp *qp, enum ib_event_type etype)
1824 {
1825 struct ib_event event;
1826 struct ib_qp *base_qp = &qp->base_qp;
1827
1828 /*
1829 * Do not report asynchronous errors on QP which gets
1830 * destroyed via verbs interface (siw_destroy_qp())
1831 */
1832 if (qp->attrs.flags & SIW_QP_IN_DESTROY)
1833 return;
1834
1835 event.event = etype;
1836 event.device = base_qp->device;
1837 event.element.qp = base_qp;
1838
1839 if (base_qp->event_handler) {
1840 siw_dbg_qp(qp, "reporting event %d\n", etype);
1841 base_qp->event_handler(&event, base_qp->qp_context);
1842 }
1843 }
1844
siw_cq_event(struct siw_cq * cq,enum ib_event_type etype)1845 void siw_cq_event(struct siw_cq *cq, enum ib_event_type etype)
1846 {
1847 struct ib_event event;
1848 struct ib_cq *base_cq = &cq->base_cq;
1849
1850 event.event = etype;
1851 event.device = base_cq->device;
1852 event.element.cq = base_cq;
1853
1854 if (base_cq->event_handler) {
1855 siw_dbg_cq(cq, "reporting CQ event %d\n", etype);
1856 base_cq->event_handler(&event, base_cq->cq_context);
1857 }
1858 }
1859
siw_srq_event(struct siw_srq * srq,enum ib_event_type etype)1860 void siw_srq_event(struct siw_srq *srq, enum ib_event_type etype)
1861 {
1862 struct ib_event event;
1863 struct ib_srq *base_srq = &srq->base_srq;
1864
1865 event.event = etype;
1866 event.device = base_srq->device;
1867 event.element.srq = base_srq;
1868
1869 if (base_srq->event_handler) {
1870 siw_dbg_pd(srq->base_srq.pd,
1871 "reporting SRQ event %d\n", etype);
1872 base_srq->event_handler(&event, base_srq->srq_context);
1873 }
1874 }
1875
siw_port_event(struct siw_device * sdev,u32 port,enum ib_event_type etype)1876 void siw_port_event(struct siw_device *sdev, u32 port, enum ib_event_type etype)
1877 {
1878 struct ib_event event;
1879
1880 event.event = etype;
1881 event.device = &sdev->base_dev;
1882 event.element.port_num = port;
1883
1884 siw_dbg(&sdev->base_dev, "reporting port event %d\n", etype);
1885
1886 ib_dispatch_event(&event);
1887 }
1888