1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/amdgpu_drm.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
37 #include "atom.h"
38 #include "amd_pcie.h"
39
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
50
51 #include "soc15.h"
52 #include "soc15_common.h"
53 #include "gfx_v9_0.h"
54 #include "gmc_v9_0.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
57 #include "df_v1_7.h"
58 #include "df_v3_6.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
62 #include "hdp_v4_0.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
67 #include "uvd_v7_0.h"
68 #include "vce_v4_0.h"
69 #include "vcn_v1_0.h"
70 #include "vcn_v2_0.h"
71 #include "jpeg_v2_0.h"
72 #include "vcn_v2_5.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "amdgpu_vkms.h"
78 #include "mxgpu_ai.h"
79 #include "amdgpu_ras.h"
80 #include "amdgpu_xgmi.h"
81 #include <uapi/linux/kfd_ioctl.h>
82
83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88 /* Vega, Raven, Arcturus */
89 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
90 {
91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
92 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
93 };
94
95 static const struct amdgpu_video_codecs vega_video_codecs_encode =
96 {
97 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
98 .codec_array = vega_video_codecs_encode_array,
99 };
100
101 /* Vega */
102 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
103 {
104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
110 };
111
112 static const struct amdgpu_video_codecs vega_video_codecs_decode =
113 {
114 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
115 .codec_array = vega_video_codecs_decode_array,
116 };
117
118 /* Raven */
119 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
120 {
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
128 };
129
130 static const struct amdgpu_video_codecs rv_video_codecs_decode =
131 {
132 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
133 .codec_array = rv_video_codecs_decode_array,
134 };
135
136 /* Renoir, Arcturus */
137 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
138 {
139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
146 };
147
148 static const struct amdgpu_video_codecs rn_video_codecs_decode =
149 {
150 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
151 .codec_array = rn_video_codecs_decode_array,
152 };
153
soc15_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)154 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
155 const struct amdgpu_video_codecs **codecs)
156 {
157 switch (adev->asic_type) {
158 case CHIP_VEGA20:
159 case CHIP_VEGA10:
160 case CHIP_VEGA12:
161 if (encode)
162 *codecs = &vega_video_codecs_encode;
163 else
164 *codecs = &vega_video_codecs_decode;
165 return 0;
166 case CHIP_RAVEN:
167 if (encode)
168 *codecs = &vega_video_codecs_encode;
169 else
170 *codecs = &rv_video_codecs_decode;
171 return 0;
172 case CHIP_ARCTURUS:
173 case CHIP_ALDEBARAN:
174 case CHIP_RENOIR:
175 if (encode)
176 *codecs = &vega_video_codecs_encode;
177 else
178 *codecs = &rn_video_codecs_decode;
179 return 0;
180 default:
181 return -EINVAL;
182 }
183 }
184
185 /*
186 * Indirect registers accessor
187 */
soc15_pcie_rreg(struct amdgpu_device * adev,u32 reg)188 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
189 {
190 unsigned long address, data;
191 address = adev->nbio.funcs->get_pcie_index_offset(adev);
192 data = adev->nbio.funcs->get_pcie_data_offset(adev);
193
194 return amdgpu_device_indirect_rreg(adev, address, data, reg);
195 }
196
soc15_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)197 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
198 {
199 unsigned long address, data;
200
201 address = adev->nbio.funcs->get_pcie_index_offset(adev);
202 data = adev->nbio.funcs->get_pcie_data_offset(adev);
203
204 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
205 }
206
soc15_pcie_rreg64(struct amdgpu_device * adev,u32 reg)207 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
208 {
209 unsigned long address, data;
210 address = adev->nbio.funcs->get_pcie_index_offset(adev);
211 data = adev->nbio.funcs->get_pcie_data_offset(adev);
212
213 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
214 }
215
soc15_pcie_wreg64(struct amdgpu_device * adev,u32 reg,u64 v)216 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
217 {
218 unsigned long address, data;
219
220 address = adev->nbio.funcs->get_pcie_index_offset(adev);
221 data = adev->nbio.funcs->get_pcie_data_offset(adev);
222
223 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
224 }
225
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)226 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
227 {
228 unsigned long flags, address, data;
229 u32 r;
230
231 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
232 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
233
234 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
235 WREG32(address, ((reg) & 0x1ff));
236 r = RREG32(data);
237 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
238 return r;
239 }
240
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)241 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
242 {
243 unsigned long flags, address, data;
244
245 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
246 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
247
248 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
249 WREG32(address, ((reg) & 0x1ff));
250 WREG32(data, (v));
251 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
252 }
253
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)254 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
255 {
256 unsigned long flags, address, data;
257 u32 r;
258
259 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
260 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
261
262 spin_lock_irqsave(&adev->didt_idx_lock, flags);
263 WREG32(address, (reg));
264 r = RREG32(data);
265 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
266 return r;
267 }
268
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)269 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
270 {
271 unsigned long flags, address, data;
272
273 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
274 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
275
276 spin_lock_irqsave(&adev->didt_idx_lock, flags);
277 WREG32(address, (reg));
278 WREG32(data, (v));
279 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
280 }
281
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)282 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
283 {
284 unsigned long flags;
285 u32 r;
286
287 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
288 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
289 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
290 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
291 return r;
292 }
293
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)294 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
295 {
296 unsigned long flags;
297
298 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
299 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
300 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
301 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
302 }
303
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)304 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
305 {
306 unsigned long flags;
307 u32 r;
308
309 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
310 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
311 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
312 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
313 return r;
314 }
315
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)316 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
317 {
318 unsigned long flags;
319
320 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
321 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
322 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
323 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
324 }
325
soc15_get_config_memsize(struct amdgpu_device * adev)326 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
327 {
328 return adev->nbio.funcs->get_memsize(adev);
329 }
330
soc15_get_xclk(struct amdgpu_device * adev)331 static u32 soc15_get_xclk(struct amdgpu_device *adev)
332 {
333 u32 reference_clock = adev->clock.spll.reference_freq;
334
335 if (adev->asic_type == CHIP_RENOIR)
336 return 10000;
337 if (adev->asic_type == CHIP_RAVEN)
338 return reference_clock / 4;
339
340 return reference_clock;
341 }
342
343
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)344 void soc15_grbm_select(struct amdgpu_device *adev,
345 u32 me, u32 pipe, u32 queue, u32 vmid)
346 {
347 u32 grbm_gfx_cntl = 0;
348 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
349 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
350 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
351 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
352
353 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
354 }
355
soc15_vga_set_state(struct amdgpu_device * adev,bool state)356 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
357 {
358 /* todo */
359 }
360
soc15_read_disabled_bios(struct amdgpu_device * adev)361 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
362 {
363 /* todo */
364 return false;
365 }
366
soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)367 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
368 u8 *bios, u32 length_bytes)
369 {
370 u32 *dw_ptr;
371 u32 i, length_dw;
372 uint32_t rom_index_offset;
373 uint32_t rom_data_offset;
374
375 if (bios == NULL)
376 return false;
377 if (length_bytes == 0)
378 return false;
379 /* APU vbios image is part of sbios image */
380 if (adev->flags & AMD_IS_APU)
381 return false;
382
383 dw_ptr = (u32 *)bios;
384 length_dw = ALIGN(length_bytes, 4) / 4;
385
386 rom_index_offset =
387 adev->smuio.funcs->get_rom_index_offset(adev);
388 rom_data_offset =
389 adev->smuio.funcs->get_rom_data_offset(adev);
390
391 /* set rom index to 0 */
392 WREG32(rom_index_offset, 0);
393 /* read out the rom data */
394 for (i = 0; i < length_dw; i++)
395 dw_ptr[i] = RREG32(rom_data_offset);
396
397 return true;
398 }
399
400 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
401 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
402 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
403 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
404 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
405 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
406 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
407 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
408 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
409 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
410 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
411 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
412 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
413 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
414 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
415 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
416 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
417 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
418 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
419 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
420 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
421 };
422
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)423 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
424 u32 sh_num, u32 reg_offset)
425 {
426 uint32_t val;
427
428 mutex_lock(&adev->grbm_idx_mutex);
429 if (se_num != 0xffffffff || sh_num != 0xffffffff)
430 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
431
432 val = RREG32(reg_offset);
433
434 if (se_num != 0xffffffff || sh_num != 0xffffffff)
435 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
436 mutex_unlock(&adev->grbm_idx_mutex);
437 return val;
438 }
439
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)440 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
441 bool indexed, u32 se_num,
442 u32 sh_num, u32 reg_offset)
443 {
444 if (indexed) {
445 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
446 } else {
447 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
448 return adev->gfx.config.gb_addr_config;
449 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
450 return adev->gfx.config.db_debug2;
451 return RREG32(reg_offset);
452 }
453 }
454
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)455 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
456 u32 sh_num, u32 reg_offset, u32 *value)
457 {
458 uint32_t i;
459 struct soc15_allowed_register_entry *en;
460
461 *value = 0;
462 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
463 en = &soc15_allowed_read_registers[i];
464 if (!adev->reg_offset[en->hwip][en->inst])
465 continue;
466 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
467 + en->reg_offset))
468 continue;
469
470 *value = soc15_get_register_value(adev,
471 soc15_allowed_read_registers[i].grbm_indexed,
472 se_num, sh_num, reg_offset);
473 return 0;
474 }
475 return -EINVAL;
476 }
477
478
479 /**
480 * soc15_program_register_sequence - program an array of registers.
481 *
482 * @adev: amdgpu_device pointer
483 * @regs: pointer to the register array
484 * @array_size: size of the register array
485 *
486 * Programs an array or registers with and and or masks.
487 * This is a helper for setting golden registers.
488 */
489
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)490 void soc15_program_register_sequence(struct amdgpu_device *adev,
491 const struct soc15_reg_golden *regs,
492 const u32 array_size)
493 {
494 const struct soc15_reg_golden *entry;
495 u32 tmp, reg;
496 int i;
497
498 for (i = 0; i < array_size; ++i) {
499 entry = ®s[i];
500 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
501
502 if (entry->and_mask == 0xffffffff) {
503 tmp = entry->or_mask;
504 } else {
505 tmp = (entry->hwip == GC_HWIP) ?
506 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
507
508 tmp &= ~(entry->and_mask);
509 tmp |= (entry->or_mask & entry->and_mask);
510 }
511
512 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
513 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
514 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
515 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
516 WREG32_RLC(reg, tmp);
517 else
518 (entry->hwip == GC_HWIP) ?
519 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
520
521 }
522
523 }
524
soc15_asic_baco_reset(struct amdgpu_device * adev)525 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
526 {
527 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
528 int ret = 0;
529
530 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
531 if (ras && adev->ras_enabled)
532 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
533
534 ret = amdgpu_dpm_baco_reset(adev);
535 if (ret)
536 return ret;
537
538 /* re-enable doorbell interrupt after BACO exit */
539 if (ras && adev->ras_enabled)
540 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
541
542 return 0;
543 }
544
545 static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device * adev)546 soc15_asic_reset_method(struct amdgpu_device *adev)
547 {
548 bool baco_reset = false;
549 bool connected_to_cpu = false;
550 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
551
552 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
553 connected_to_cpu = true;
554
555 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
556 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
557 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
558 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
559 /* If connected to cpu, driver only support mode2 */
560 if (connected_to_cpu)
561 return AMD_RESET_METHOD_MODE2;
562 return amdgpu_reset_method;
563 }
564
565 if (amdgpu_reset_method != -1)
566 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
567 amdgpu_reset_method);
568
569 switch (adev->asic_type) {
570 case CHIP_RAVEN:
571 case CHIP_RENOIR:
572 return AMD_RESET_METHOD_MODE2;
573 case CHIP_VEGA10:
574 case CHIP_VEGA12:
575 case CHIP_ARCTURUS:
576 baco_reset = amdgpu_dpm_is_baco_supported(adev);
577 break;
578 case CHIP_VEGA20:
579 if (adev->psp.sos.fw_version >= 0x80067)
580 baco_reset = amdgpu_dpm_is_baco_supported(adev);
581
582 /*
583 * 1. PMFW version > 0x284300: all cases use baco
584 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
585 */
586 if (ras && adev->ras_enabled &&
587 adev->pm.fw_version <= 0x283400)
588 baco_reset = false;
589 break;
590 case CHIP_ALDEBARAN:
591 /*
592 * 1.connected to cpu: driver issue mode2 reset
593 * 2.discret gpu: driver issue mode1 reset
594 */
595 if (connected_to_cpu)
596 return AMD_RESET_METHOD_MODE2;
597 break;
598 default:
599 break;
600 }
601
602 if (baco_reset)
603 return AMD_RESET_METHOD_BACO;
604 else
605 return AMD_RESET_METHOD_MODE1;
606 }
607
soc15_asic_reset(struct amdgpu_device * adev)608 static int soc15_asic_reset(struct amdgpu_device *adev)
609 {
610 /* original raven doesn't have full asic reset */
611 if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
612 (adev->apu_flags & AMD_APU_IS_RAVEN2))
613 return 0;
614
615 switch (soc15_asic_reset_method(adev)) {
616 case AMD_RESET_METHOD_PCI:
617 dev_info(adev->dev, "PCI reset\n");
618 return amdgpu_device_pci_reset(adev);
619 case AMD_RESET_METHOD_BACO:
620 dev_info(adev->dev, "BACO reset\n");
621 return soc15_asic_baco_reset(adev);
622 case AMD_RESET_METHOD_MODE2:
623 dev_info(adev->dev, "MODE2 reset\n");
624 return amdgpu_dpm_mode2_reset(adev);
625 default:
626 dev_info(adev->dev, "MODE1 reset\n");
627 return amdgpu_device_mode1_reset(adev);
628 }
629 }
630
soc15_supports_baco(struct amdgpu_device * adev)631 static bool soc15_supports_baco(struct amdgpu_device *adev)
632 {
633 switch (adev->asic_type) {
634 case CHIP_VEGA10:
635 case CHIP_VEGA12:
636 case CHIP_ARCTURUS:
637 return amdgpu_dpm_is_baco_supported(adev);
638 case CHIP_VEGA20:
639 if (adev->psp.sos.fw_version >= 0x80067)
640 return amdgpu_dpm_is_baco_supported(adev);
641 return false;
642 default:
643 return false;
644 }
645 }
646
647 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
648 u32 cntl_reg, u32 status_reg)
649 {
650 return 0;
651 }*/
652
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)653 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
654 {
655 /*int r;
656
657 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
658 if (r)
659 return r;
660
661 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
662 */
663 return 0;
664 }
665
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)666 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
667 {
668 /* todo */
669
670 return 0;
671 }
672
soc15_pcie_gen3_enable(struct amdgpu_device * adev)673 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
674 {
675 if (pci_is_root_bus(adev->pdev->bus))
676 return;
677
678 if (amdgpu_pcie_gen2 == 0)
679 return;
680
681 if (adev->flags & AMD_IS_APU)
682 return;
683
684 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
685 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
686 return;
687
688 /* todo */
689 }
690
soc15_program_aspm(struct amdgpu_device * adev)691 static void soc15_program_aspm(struct amdgpu_device *adev)
692 {
693 if (!amdgpu_device_should_use_aspm(adev))
694 return;
695
696 if (!(adev->flags & AMD_IS_APU) &&
697 (adev->nbio.funcs->program_aspm))
698 adev->nbio.funcs->program_aspm(adev);
699 }
700
soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)701 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
702 bool enable)
703 {
704 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
705 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
706 }
707
708 static const struct amdgpu_ip_block_version vega10_common_ip_block =
709 {
710 .type = AMD_IP_BLOCK_TYPE_COMMON,
711 .major = 2,
712 .minor = 0,
713 .rev = 0,
714 .funcs = &soc15_common_ip_funcs,
715 };
716
soc15_get_rev_id(struct amdgpu_device * adev)717 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
718 {
719 return adev->nbio.funcs->get_rev_id(adev);
720 }
721
soc15_reg_base_init(struct amdgpu_device * adev)722 static void soc15_reg_base_init(struct amdgpu_device *adev)
723 {
724 int r;
725
726 /* Set IP register base before any HW register access */
727 switch (adev->asic_type) {
728 case CHIP_VEGA10:
729 case CHIP_VEGA12:
730 case CHIP_RAVEN:
731 vega10_reg_base_init(adev);
732 break;
733 case CHIP_RENOIR:
734 /* It's safe to do ip discovery here for Renior,
735 * it doesn't support SRIOV. */
736 if (amdgpu_discovery) {
737 r = amdgpu_discovery_reg_base_init(adev);
738 if (r == 0)
739 break;
740 DRM_WARN("failed to init reg base from ip discovery table, "
741 "fallback to legacy init method\n");
742 }
743 vega10_reg_base_init(adev);
744 break;
745 case CHIP_VEGA20:
746 vega20_reg_base_init(adev);
747 break;
748 case CHIP_ARCTURUS:
749 arct_reg_base_init(adev);
750 break;
751 case CHIP_ALDEBARAN:
752 aldebaran_reg_base_init(adev);
753 break;
754 default:
755 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
756 break;
757 }
758 }
759
soc15_set_virt_ops(struct amdgpu_device * adev)760 void soc15_set_virt_ops(struct amdgpu_device *adev)
761 {
762 adev->virt.ops = &xgpu_ai_virt_ops;
763
764 /* init soc15 reg base early enough so we can
765 * request request full access for sriov before
766 * set_ip_blocks. */
767 soc15_reg_base_init(adev);
768 }
769
soc15_set_ip_blocks(struct amdgpu_device * adev)770 int soc15_set_ip_blocks(struct amdgpu_device *adev)
771 {
772 /* for bare metal case */
773 if (!amdgpu_sriov_vf(adev))
774 soc15_reg_base_init(adev);
775
776 if (adev->flags & AMD_IS_APU) {
777 adev->nbio.funcs = &nbio_v7_0_funcs;
778 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
779 } else if (adev->asic_type == CHIP_VEGA20 ||
780 adev->asic_type == CHIP_ARCTURUS ||
781 adev->asic_type == CHIP_ALDEBARAN) {
782 adev->nbio.funcs = &nbio_v7_4_funcs;
783 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
784 } else {
785 adev->nbio.funcs = &nbio_v6_1_funcs;
786 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
787 }
788 adev->hdp.funcs = &hdp_v4_0_funcs;
789
790 if (adev->asic_type == CHIP_VEGA20 ||
791 adev->asic_type == CHIP_ARCTURUS ||
792 adev->asic_type == CHIP_ALDEBARAN)
793 adev->df.funcs = &df_v3_6_funcs;
794 else
795 adev->df.funcs = &df_v1_7_funcs;
796
797 if (adev->asic_type == CHIP_VEGA20 ||
798 adev->asic_type == CHIP_ARCTURUS)
799 adev->smuio.funcs = &smuio_v11_0_funcs;
800 else if (adev->asic_type == CHIP_ALDEBARAN)
801 adev->smuio.funcs = &smuio_v13_0_funcs;
802 else
803 adev->smuio.funcs = &smuio_v9_0_funcs;
804
805 adev->rev_id = soc15_get_rev_id(adev);
806
807 switch (adev->asic_type) {
808 case CHIP_VEGA10:
809 case CHIP_VEGA12:
810 case CHIP_VEGA20:
811 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
812 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
813
814 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
815 if (amdgpu_sriov_vf(adev)) {
816 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
817 if (adev->asic_type == CHIP_VEGA20)
818 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
819 else
820 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
821 }
822 if (adev->asic_type == CHIP_VEGA20)
823 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
824 else
825 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
826 } else {
827 if (adev->asic_type == CHIP_VEGA20)
828 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
829 else
830 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
831 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
832 if (adev->asic_type == CHIP_VEGA20)
833 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
834 else
835 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
836 }
837 }
838 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
839 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
840 if (is_support_sw_smu(adev)) {
841 if (!amdgpu_sriov_vf(adev))
842 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
843 } else {
844 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
845 }
846 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
847 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
848 #if defined(CONFIG_DRM_AMD_DC)
849 else if (amdgpu_device_has_dc_support(adev))
850 amdgpu_device_ip_block_add(adev, &dm_ip_block);
851 #endif
852 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
853 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
854 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
855 }
856 break;
857 case CHIP_RAVEN:
858 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
859 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
860 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
861 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
862 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
863 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
864 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
865 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
866 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
867 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
868 #if defined(CONFIG_DRM_AMD_DC)
869 else if (amdgpu_device_has_dc_support(adev))
870 amdgpu_device_ip_block_add(adev, &dm_ip_block);
871 #endif
872 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
873 break;
874 case CHIP_ARCTURUS:
875 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
876 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
877
878 if (amdgpu_sriov_vf(adev)) {
879 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
880 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
881 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
882 } else {
883 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
884 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
885 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
886 }
887
888 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
889 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
890 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
891 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
892 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
893
894 if (amdgpu_sriov_vf(adev)) {
895 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
896 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
897 } else {
898 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
899 }
900 if (!amdgpu_sriov_vf(adev))
901 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
902 break;
903 case CHIP_RENOIR:
904 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
905 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
906 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
907 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
908 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
909 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
910 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
911 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
912 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
913 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
914 #if defined(CONFIG_DRM_AMD_DC)
915 else if (amdgpu_device_has_dc_support(adev))
916 amdgpu_device_ip_block_add(adev, &dm_ip_block);
917 #endif
918 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
919 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
920 break;
921 case CHIP_ALDEBARAN:
922 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
923 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
924
925 if (amdgpu_sriov_vf(adev)) {
926 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
927 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
928 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
929 } else {
930 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
931 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
932 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
933 }
934
935 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
936 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
937
938 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
939 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
940 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
941 break;
942 default:
943 return -EINVAL;
944 }
945
946 return 0;
947 }
948
soc15_need_full_reset(struct amdgpu_device * adev)949 static bool soc15_need_full_reset(struct amdgpu_device *adev)
950 {
951 /* change this when we implement soft reset */
952 return true;
953 }
954
soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)955 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
956 uint64_t *count1)
957 {
958 uint32_t perfctr = 0;
959 uint64_t cnt0_of, cnt1_of;
960 int tmp;
961
962 /* This reports 0 on APUs, so return to avoid writing/reading registers
963 * that may or may not be different from their GPU counterparts
964 */
965 if (adev->flags & AMD_IS_APU)
966 return;
967
968 /* Set the 2 events that we wish to watch, defined above */
969 /* Reg 40 is # received msgs */
970 /* Reg 104 is # of posted requests sent */
971 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
972 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
973
974 /* Write to enable desired perf counters */
975 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
976 /* Zero out and enable the perf counters
977 * Write 0x5:
978 * Bit 0 = Start all counters(1)
979 * Bit 2 = Global counter reset enable(1)
980 */
981 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
982
983 msleep(1000);
984
985 /* Load the shadow and disable the perf counters
986 * Write 0x2:
987 * Bit 0 = Stop counters(0)
988 * Bit 1 = Load the shadow counters(1)
989 */
990 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
991
992 /* Read register values to get any >32bit overflow */
993 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
994 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
995 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
996
997 /* Get the values and add the overflow */
998 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
999 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1000 }
1001
vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)1002 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1003 uint64_t *count1)
1004 {
1005 uint32_t perfctr = 0;
1006 uint64_t cnt0_of, cnt1_of;
1007 int tmp;
1008
1009 /* This reports 0 on APUs, so return to avoid writing/reading registers
1010 * that may or may not be different from their GPU counterparts
1011 */
1012 if (adev->flags & AMD_IS_APU)
1013 return;
1014
1015 /* Set the 2 events that we wish to watch, defined above */
1016 /* Reg 40 is # received msgs */
1017 /* Reg 108 is # of posted requests sent on VG20 */
1018 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1019 EVENT0_SEL, 40);
1020 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1021 EVENT1_SEL, 108);
1022
1023 /* Write to enable desired perf counters */
1024 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
1025 /* Zero out and enable the perf counters
1026 * Write 0x5:
1027 * Bit 0 = Start all counters(1)
1028 * Bit 2 = Global counter reset enable(1)
1029 */
1030 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1031
1032 msleep(1000);
1033
1034 /* Load the shadow and disable the perf counters
1035 * Write 0x2:
1036 * Bit 0 = Stop counters(0)
1037 * Bit 1 = Load the shadow counters(1)
1038 */
1039 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1040
1041 /* Read register values to get any >32bit overflow */
1042 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
1043 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
1044 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
1045
1046 /* Get the values and add the overflow */
1047 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
1048 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
1049 }
1050
soc15_need_reset_on_init(struct amdgpu_device * adev)1051 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
1052 {
1053 u32 sol_reg;
1054
1055 /* Just return false for soc15 GPUs. Reset does not seem to
1056 * be necessary.
1057 */
1058 if (!amdgpu_passthrough(adev))
1059 return false;
1060
1061 if (adev->flags & AMD_IS_APU)
1062 return false;
1063
1064 /* Check sOS sign of life register to confirm sys driver and sOS
1065 * are already been loaded.
1066 */
1067 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1068 if (sol_reg)
1069 return true;
1070
1071 return false;
1072 }
1073
soc15_get_pcie_replay_count(struct amdgpu_device * adev)1074 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1075 {
1076 uint64_t nak_r, nak_g;
1077
1078 /* Get the number of NAKs received and generated */
1079 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1080 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1081
1082 /* Add the total number of NAKs, i.e the number of replays */
1083 return (nak_r + nak_g);
1084 }
1085
soc15_pre_asic_init(struct amdgpu_device * adev)1086 static void soc15_pre_asic_init(struct amdgpu_device *adev)
1087 {
1088 gmc_v9_0_restore_registers(adev);
1089 }
1090
1091 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1092 {
1093 .read_disabled_bios = &soc15_read_disabled_bios,
1094 .read_bios_from_rom = &soc15_read_bios_from_rom,
1095 .read_register = &soc15_read_register,
1096 .reset = &soc15_asic_reset,
1097 .reset_method = &soc15_asic_reset_method,
1098 .set_vga_state = &soc15_vga_set_state,
1099 .get_xclk = &soc15_get_xclk,
1100 .set_uvd_clocks = &soc15_set_uvd_clocks,
1101 .set_vce_clocks = &soc15_set_vce_clocks,
1102 .get_config_memsize = &soc15_get_config_memsize,
1103 .need_full_reset = &soc15_need_full_reset,
1104 .init_doorbell_index = &vega10_doorbell_index_init,
1105 .get_pcie_usage = &soc15_get_pcie_usage,
1106 .need_reset_on_init = &soc15_need_reset_on_init,
1107 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1108 .supports_baco = &soc15_supports_baco,
1109 .pre_asic_init = &soc15_pre_asic_init,
1110 .query_video_codecs = &soc15_query_video_codecs,
1111 };
1112
1113 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1114 {
1115 .read_disabled_bios = &soc15_read_disabled_bios,
1116 .read_bios_from_rom = &soc15_read_bios_from_rom,
1117 .read_register = &soc15_read_register,
1118 .reset = &soc15_asic_reset,
1119 .reset_method = &soc15_asic_reset_method,
1120 .set_vga_state = &soc15_vga_set_state,
1121 .get_xclk = &soc15_get_xclk,
1122 .set_uvd_clocks = &soc15_set_uvd_clocks,
1123 .set_vce_clocks = &soc15_set_vce_clocks,
1124 .get_config_memsize = &soc15_get_config_memsize,
1125 .need_full_reset = &soc15_need_full_reset,
1126 .init_doorbell_index = &vega20_doorbell_index_init,
1127 .get_pcie_usage = &vega20_get_pcie_usage,
1128 .need_reset_on_init = &soc15_need_reset_on_init,
1129 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1130 .supports_baco = &soc15_supports_baco,
1131 .pre_asic_init = &soc15_pre_asic_init,
1132 .query_video_codecs = &soc15_query_video_codecs,
1133 };
1134
soc15_common_early_init(void * handle)1135 static int soc15_common_early_init(void *handle)
1136 {
1137 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1141 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1142 adev->smc_rreg = NULL;
1143 adev->smc_wreg = NULL;
1144 adev->pcie_rreg = &soc15_pcie_rreg;
1145 adev->pcie_wreg = &soc15_pcie_wreg;
1146 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1147 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1148 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1149 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1150 adev->didt_rreg = &soc15_didt_rreg;
1151 adev->didt_wreg = &soc15_didt_wreg;
1152 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1153 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1154 adev->se_cac_rreg = &soc15_se_cac_rreg;
1155 adev->se_cac_wreg = &soc15_se_cac_wreg;
1156
1157
1158 adev->external_rev_id = 0xFF;
1159 switch (adev->asic_type) {
1160 case CHIP_VEGA10:
1161 adev->asic_funcs = &soc15_asic_funcs;
1162 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1163 AMD_CG_SUPPORT_GFX_MGLS |
1164 AMD_CG_SUPPORT_GFX_RLC_LS |
1165 AMD_CG_SUPPORT_GFX_CP_LS |
1166 AMD_CG_SUPPORT_GFX_3D_CGCG |
1167 AMD_CG_SUPPORT_GFX_3D_CGLS |
1168 AMD_CG_SUPPORT_GFX_CGCG |
1169 AMD_CG_SUPPORT_GFX_CGLS |
1170 AMD_CG_SUPPORT_BIF_MGCG |
1171 AMD_CG_SUPPORT_BIF_LS |
1172 AMD_CG_SUPPORT_HDP_LS |
1173 AMD_CG_SUPPORT_DRM_MGCG |
1174 AMD_CG_SUPPORT_DRM_LS |
1175 AMD_CG_SUPPORT_ROM_MGCG |
1176 AMD_CG_SUPPORT_DF_MGCG |
1177 AMD_CG_SUPPORT_SDMA_MGCG |
1178 AMD_CG_SUPPORT_SDMA_LS |
1179 AMD_CG_SUPPORT_MC_MGCG |
1180 AMD_CG_SUPPORT_MC_LS;
1181 adev->pg_flags = 0;
1182 adev->external_rev_id = 0x1;
1183 break;
1184 case CHIP_VEGA12:
1185 adev->asic_funcs = &soc15_asic_funcs;
1186 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1187 AMD_CG_SUPPORT_GFX_MGLS |
1188 AMD_CG_SUPPORT_GFX_CGCG |
1189 AMD_CG_SUPPORT_GFX_CGLS |
1190 AMD_CG_SUPPORT_GFX_3D_CGCG |
1191 AMD_CG_SUPPORT_GFX_3D_CGLS |
1192 AMD_CG_SUPPORT_GFX_CP_LS |
1193 AMD_CG_SUPPORT_MC_LS |
1194 AMD_CG_SUPPORT_MC_MGCG |
1195 AMD_CG_SUPPORT_SDMA_MGCG |
1196 AMD_CG_SUPPORT_SDMA_LS |
1197 AMD_CG_SUPPORT_BIF_MGCG |
1198 AMD_CG_SUPPORT_BIF_LS |
1199 AMD_CG_SUPPORT_HDP_MGCG |
1200 AMD_CG_SUPPORT_HDP_LS |
1201 AMD_CG_SUPPORT_ROM_MGCG |
1202 AMD_CG_SUPPORT_VCE_MGCG |
1203 AMD_CG_SUPPORT_UVD_MGCG;
1204 adev->pg_flags = 0;
1205 adev->external_rev_id = adev->rev_id + 0x14;
1206 break;
1207 case CHIP_VEGA20:
1208 adev->asic_funcs = &vega20_asic_funcs;
1209 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1210 AMD_CG_SUPPORT_GFX_MGLS |
1211 AMD_CG_SUPPORT_GFX_CGCG |
1212 AMD_CG_SUPPORT_GFX_CGLS |
1213 AMD_CG_SUPPORT_GFX_3D_CGCG |
1214 AMD_CG_SUPPORT_GFX_3D_CGLS |
1215 AMD_CG_SUPPORT_GFX_CP_LS |
1216 AMD_CG_SUPPORT_MC_LS |
1217 AMD_CG_SUPPORT_MC_MGCG |
1218 AMD_CG_SUPPORT_SDMA_MGCG |
1219 AMD_CG_SUPPORT_SDMA_LS |
1220 AMD_CG_SUPPORT_BIF_MGCG |
1221 AMD_CG_SUPPORT_BIF_LS |
1222 AMD_CG_SUPPORT_HDP_MGCG |
1223 AMD_CG_SUPPORT_HDP_LS |
1224 AMD_CG_SUPPORT_ROM_MGCG |
1225 AMD_CG_SUPPORT_VCE_MGCG |
1226 AMD_CG_SUPPORT_UVD_MGCG;
1227 adev->pg_flags = 0;
1228 adev->external_rev_id = adev->rev_id + 0x28;
1229 break;
1230 case CHIP_RAVEN:
1231 adev->asic_funcs = &soc15_asic_funcs;
1232
1233 if (adev->rev_id >= 0x8)
1234 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1235
1236 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1237 adev->external_rev_id = adev->rev_id + 0x79;
1238 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1239 adev->external_rev_id = adev->rev_id + 0x41;
1240 else if (adev->rev_id == 1)
1241 adev->external_rev_id = adev->rev_id + 0x20;
1242 else
1243 adev->external_rev_id = adev->rev_id + 0x01;
1244
1245 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1246 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1247 AMD_CG_SUPPORT_GFX_MGLS |
1248 AMD_CG_SUPPORT_GFX_CP_LS |
1249 AMD_CG_SUPPORT_GFX_3D_CGCG |
1250 AMD_CG_SUPPORT_GFX_3D_CGLS |
1251 AMD_CG_SUPPORT_GFX_CGCG |
1252 AMD_CG_SUPPORT_GFX_CGLS |
1253 AMD_CG_SUPPORT_BIF_LS |
1254 AMD_CG_SUPPORT_HDP_LS |
1255 AMD_CG_SUPPORT_MC_MGCG |
1256 AMD_CG_SUPPORT_MC_LS |
1257 AMD_CG_SUPPORT_SDMA_MGCG |
1258 AMD_CG_SUPPORT_SDMA_LS |
1259 AMD_CG_SUPPORT_VCN_MGCG;
1260
1261 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1262 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1263 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1264 AMD_CG_SUPPORT_GFX_MGLS |
1265 AMD_CG_SUPPORT_GFX_CP_LS |
1266 AMD_CG_SUPPORT_GFX_3D_CGLS |
1267 AMD_CG_SUPPORT_GFX_CGCG |
1268 AMD_CG_SUPPORT_GFX_CGLS |
1269 AMD_CG_SUPPORT_BIF_LS |
1270 AMD_CG_SUPPORT_HDP_LS |
1271 AMD_CG_SUPPORT_MC_MGCG |
1272 AMD_CG_SUPPORT_MC_LS |
1273 AMD_CG_SUPPORT_SDMA_MGCG |
1274 AMD_CG_SUPPORT_SDMA_LS |
1275 AMD_CG_SUPPORT_VCN_MGCG;
1276
1277 /*
1278 * MMHUB PG needs to be disabled for Picasso for
1279 * stability reasons.
1280 */
1281 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1282 AMD_PG_SUPPORT_VCN;
1283 } else {
1284 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1285 AMD_CG_SUPPORT_GFX_MGLS |
1286 AMD_CG_SUPPORT_GFX_RLC_LS |
1287 AMD_CG_SUPPORT_GFX_CP_LS |
1288 AMD_CG_SUPPORT_GFX_3D_CGLS |
1289 AMD_CG_SUPPORT_GFX_CGCG |
1290 AMD_CG_SUPPORT_GFX_CGLS |
1291 AMD_CG_SUPPORT_BIF_MGCG |
1292 AMD_CG_SUPPORT_BIF_LS |
1293 AMD_CG_SUPPORT_HDP_MGCG |
1294 AMD_CG_SUPPORT_HDP_LS |
1295 AMD_CG_SUPPORT_DRM_MGCG |
1296 AMD_CG_SUPPORT_DRM_LS |
1297 AMD_CG_SUPPORT_MC_MGCG |
1298 AMD_CG_SUPPORT_MC_LS |
1299 AMD_CG_SUPPORT_SDMA_MGCG |
1300 AMD_CG_SUPPORT_SDMA_LS |
1301 AMD_CG_SUPPORT_VCN_MGCG;
1302
1303 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1304 }
1305 break;
1306 case CHIP_ARCTURUS:
1307 adev->asic_funcs = &vega20_asic_funcs;
1308 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1309 AMD_CG_SUPPORT_GFX_MGLS |
1310 AMD_CG_SUPPORT_GFX_CGCG |
1311 AMD_CG_SUPPORT_GFX_CGLS |
1312 AMD_CG_SUPPORT_GFX_CP_LS |
1313 AMD_CG_SUPPORT_HDP_MGCG |
1314 AMD_CG_SUPPORT_HDP_LS |
1315 AMD_CG_SUPPORT_SDMA_MGCG |
1316 AMD_CG_SUPPORT_SDMA_LS |
1317 AMD_CG_SUPPORT_MC_MGCG |
1318 AMD_CG_SUPPORT_MC_LS |
1319 AMD_CG_SUPPORT_IH_CG |
1320 AMD_CG_SUPPORT_VCN_MGCG |
1321 AMD_CG_SUPPORT_JPEG_MGCG;
1322 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1323 adev->external_rev_id = adev->rev_id + 0x32;
1324 break;
1325 case CHIP_RENOIR:
1326 adev->asic_funcs = &soc15_asic_funcs;
1327
1328 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1329 adev->external_rev_id = adev->rev_id + 0x91;
1330 else
1331 adev->external_rev_id = adev->rev_id + 0xa1;
1332 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1333 AMD_CG_SUPPORT_GFX_MGLS |
1334 AMD_CG_SUPPORT_GFX_3D_CGCG |
1335 AMD_CG_SUPPORT_GFX_3D_CGLS |
1336 AMD_CG_SUPPORT_GFX_CGCG |
1337 AMD_CG_SUPPORT_GFX_CGLS |
1338 AMD_CG_SUPPORT_GFX_CP_LS |
1339 AMD_CG_SUPPORT_MC_MGCG |
1340 AMD_CG_SUPPORT_MC_LS |
1341 AMD_CG_SUPPORT_SDMA_MGCG |
1342 AMD_CG_SUPPORT_SDMA_LS |
1343 AMD_CG_SUPPORT_BIF_LS |
1344 AMD_CG_SUPPORT_HDP_LS |
1345 AMD_CG_SUPPORT_VCN_MGCG |
1346 AMD_CG_SUPPORT_JPEG_MGCG |
1347 AMD_CG_SUPPORT_IH_CG |
1348 AMD_CG_SUPPORT_ATHUB_LS |
1349 AMD_CG_SUPPORT_ATHUB_MGCG |
1350 AMD_CG_SUPPORT_DF_MGCG;
1351 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1352 AMD_PG_SUPPORT_VCN |
1353 AMD_PG_SUPPORT_JPEG |
1354 AMD_PG_SUPPORT_VCN_DPG;
1355 break;
1356 case CHIP_ALDEBARAN:
1357 adev->asic_funcs = &vega20_asic_funcs;
1358 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1359 AMD_CG_SUPPORT_GFX_MGLS |
1360 AMD_CG_SUPPORT_GFX_CP_LS |
1361 AMD_CG_SUPPORT_HDP_LS |
1362 AMD_CG_SUPPORT_SDMA_MGCG |
1363 AMD_CG_SUPPORT_SDMA_LS |
1364 AMD_CG_SUPPORT_IH_CG |
1365 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1366 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1367 adev->external_rev_id = adev->rev_id + 0x3c;
1368 break;
1369 default:
1370 /* FIXME: not supported yet */
1371 return -EINVAL;
1372 }
1373
1374 if (amdgpu_sriov_vf(adev)) {
1375 amdgpu_virt_init_setting(adev);
1376 xgpu_ai_mailbox_set_irq_funcs(adev);
1377 }
1378
1379 return 0;
1380 }
1381
soc15_common_late_init(void * handle)1382 static int soc15_common_late_init(void *handle)
1383 {
1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1385 int r = 0;
1386
1387 if (amdgpu_sriov_vf(adev))
1388 xgpu_ai_mailbox_get_irq(adev);
1389
1390 if (adev->nbio.ras_funcs &&
1391 adev->nbio.ras_funcs->ras_late_init)
1392 r = adev->nbio.ras_funcs->ras_late_init(adev);
1393
1394 return r;
1395 }
1396
soc15_common_sw_init(void * handle)1397 static int soc15_common_sw_init(void *handle)
1398 {
1399 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1400
1401 if (amdgpu_sriov_vf(adev))
1402 xgpu_ai_mailbox_add_irq_id(adev);
1403
1404 adev->df.funcs->sw_init(adev);
1405
1406 return 0;
1407 }
1408
soc15_common_sw_fini(void * handle)1409 static int soc15_common_sw_fini(void *handle)
1410 {
1411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1412
1413 if (adev->nbio.ras_funcs &&
1414 adev->nbio.ras_funcs->ras_fini)
1415 adev->nbio.ras_funcs->ras_fini(adev);
1416 adev->df.funcs->sw_fini(adev);
1417 return 0;
1418 }
1419
soc15_sdma_doorbell_range_init(struct amdgpu_device * adev)1420 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1421 {
1422 int i;
1423
1424 /* sdma doorbell range is programed by hypervisor */
1425 if (!amdgpu_sriov_vf(adev)) {
1426 for (i = 0; i < adev->sdma.num_instances; i++) {
1427 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1428 true, adev->doorbell_index.sdma_engine[i] << 1,
1429 adev->doorbell_index.sdma_doorbell_range);
1430 }
1431 }
1432 }
1433
soc15_common_hw_init(void * handle)1434 static int soc15_common_hw_init(void *handle)
1435 {
1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437
1438 /* enable pcie gen2/3 link */
1439 soc15_pcie_gen3_enable(adev);
1440 /* enable aspm */
1441 soc15_program_aspm(adev);
1442 /* setup nbio registers */
1443 adev->nbio.funcs->init_registers(adev);
1444 /* remap HDP registers to a hole in mmio space,
1445 * for the purpose of expose those registers
1446 * to process space
1447 */
1448 if (adev->nbio.funcs->remap_hdp_registers)
1449 adev->nbio.funcs->remap_hdp_registers(adev);
1450
1451 /* enable the doorbell aperture */
1452 soc15_enable_doorbell_aperture(adev, true);
1453 /* HW doorbell routing policy: doorbell writing not
1454 * in SDMA/IH/MM/ACV range will be routed to CP. So
1455 * we need to init SDMA doorbell range prior
1456 * to CP ip block init and ring test. IH already
1457 * happens before CP.
1458 */
1459 soc15_sdma_doorbell_range_init(adev);
1460
1461 return 0;
1462 }
1463
soc15_common_hw_fini(void * handle)1464 static int soc15_common_hw_fini(void *handle)
1465 {
1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1467
1468 /* disable the doorbell aperture */
1469 soc15_enable_doorbell_aperture(adev, false);
1470 if (amdgpu_sriov_vf(adev))
1471 xgpu_ai_mailbox_put_irq(adev);
1472
1473 if (adev->nbio.ras_if &&
1474 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1475 if (adev->nbio.ras_funcs &&
1476 adev->nbio.ras_funcs->init_ras_controller_interrupt)
1477 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1478 if (adev->nbio.ras_funcs &&
1479 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)
1480 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1481 }
1482
1483 return 0;
1484 }
1485
soc15_common_suspend(void * handle)1486 static int soc15_common_suspend(void *handle)
1487 {
1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1489
1490 return soc15_common_hw_fini(adev);
1491 }
1492
soc15_need_reset_on_resume(struct amdgpu_device * adev)1493 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
1494 {
1495 u32 sol_reg;
1496
1497 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1498
1499 /* Will reset for the following suspend abort cases.
1500 * 1) Only reset limit on APU side, dGPU hasn't checked yet.
1501 * 2) S3 suspend abort and TOS already launched.
1502 */
1503 if (adev->flags & AMD_IS_APU && adev->in_s3 &&
1504 !adev->suspend_complete &&
1505 sol_reg)
1506 return true;
1507
1508 return false;
1509 }
1510
soc15_common_resume(void * handle)1511 static int soc15_common_resume(void *handle)
1512 {
1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1514
1515 if (soc15_need_reset_on_resume(adev)) {
1516 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");
1517 soc15_asic_reset(adev);
1518 }
1519 return soc15_common_hw_init(adev);
1520 }
1521
soc15_common_is_idle(void * handle)1522 static bool soc15_common_is_idle(void *handle)
1523 {
1524 return true;
1525 }
1526
soc15_common_wait_for_idle(void * handle)1527 static int soc15_common_wait_for_idle(void *handle)
1528 {
1529 return 0;
1530 }
1531
soc15_common_soft_reset(void * handle)1532 static int soc15_common_soft_reset(void *handle)
1533 {
1534 return 0;
1535 }
1536
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)1537 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1538 {
1539 uint32_t def, data;
1540
1541 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1542
1543 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1544 data &= ~(0x01000000 |
1545 0x02000000 |
1546 0x04000000 |
1547 0x08000000 |
1548 0x10000000 |
1549 0x20000000 |
1550 0x40000000 |
1551 0x80000000);
1552 else
1553 data |= (0x01000000 |
1554 0x02000000 |
1555 0x04000000 |
1556 0x08000000 |
1557 0x10000000 |
1558 0x20000000 |
1559 0x40000000 |
1560 0x80000000);
1561
1562 if (def != data)
1563 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1564 }
1565
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1566 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1567 {
1568 uint32_t def, data;
1569
1570 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1571
1572 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1573 data |= 1;
1574 else
1575 data &= ~1;
1576
1577 if (def != data)
1578 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1579 }
1580
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1581 static int soc15_common_set_clockgating_state(void *handle,
1582 enum amd_clockgating_state state)
1583 {
1584 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1585
1586 if (amdgpu_sriov_vf(adev))
1587 return 0;
1588
1589 switch (adev->asic_type) {
1590 case CHIP_VEGA10:
1591 case CHIP_VEGA12:
1592 case CHIP_VEGA20:
1593 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1594 state == AMD_CG_STATE_GATE);
1595 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1596 state == AMD_CG_STATE_GATE);
1597 adev->hdp.funcs->update_clock_gating(adev,
1598 state == AMD_CG_STATE_GATE);
1599 soc15_update_drm_clock_gating(adev,
1600 state == AMD_CG_STATE_GATE);
1601 soc15_update_drm_light_sleep(adev,
1602 state == AMD_CG_STATE_GATE);
1603 adev->smuio.funcs->update_rom_clock_gating(adev,
1604 state == AMD_CG_STATE_GATE);
1605 adev->df.funcs->update_medium_grain_clock_gating(adev,
1606 state == AMD_CG_STATE_GATE);
1607 break;
1608 case CHIP_RAVEN:
1609 case CHIP_RENOIR:
1610 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1611 state == AMD_CG_STATE_GATE);
1612 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1613 state == AMD_CG_STATE_GATE);
1614 adev->hdp.funcs->update_clock_gating(adev,
1615 state == AMD_CG_STATE_GATE);
1616 soc15_update_drm_clock_gating(adev,
1617 state == AMD_CG_STATE_GATE);
1618 soc15_update_drm_light_sleep(adev,
1619 state == AMD_CG_STATE_GATE);
1620 break;
1621 case CHIP_ARCTURUS:
1622 case CHIP_ALDEBARAN:
1623 adev->hdp.funcs->update_clock_gating(adev,
1624 state == AMD_CG_STATE_GATE);
1625 break;
1626 default:
1627 break;
1628 }
1629 return 0;
1630 }
1631
soc15_common_get_clockgating_state(void * handle,u32 * flags)1632 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1633 {
1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1635 int data;
1636
1637 if (amdgpu_sriov_vf(adev))
1638 *flags = 0;
1639
1640 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1641 adev->nbio.funcs->get_clockgating_state(adev, flags);
1642
1643 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1644 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1645
1646 if (adev->asic_type != CHIP_ALDEBARAN) {
1647
1648 /* AMD_CG_SUPPORT_DRM_MGCG */
1649 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1650 if (!(data & 0x01000000))
1651 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1652
1653 /* AMD_CG_SUPPORT_DRM_LS */
1654 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1655 if (data & 0x1)
1656 *flags |= AMD_CG_SUPPORT_DRM_LS;
1657 }
1658
1659 /* AMD_CG_SUPPORT_ROM_MGCG */
1660 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1661 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1662
1663 if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1664 adev->df.funcs->get_clockgating_state(adev, flags);
1665 }
1666
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)1667 static int soc15_common_set_powergating_state(void *handle,
1668 enum amd_powergating_state state)
1669 {
1670 /* todo */
1671 return 0;
1672 }
1673
1674 const struct amd_ip_funcs soc15_common_ip_funcs = {
1675 .name = "soc15_common",
1676 .early_init = soc15_common_early_init,
1677 .late_init = soc15_common_late_init,
1678 .sw_init = soc15_common_sw_init,
1679 .sw_fini = soc15_common_sw_fini,
1680 .hw_init = soc15_common_hw_init,
1681 .hw_fini = soc15_common_hw_fini,
1682 .suspend = soc15_common_suspend,
1683 .resume = soc15_common_resume,
1684 .is_idle = soc15_common_is_idle,
1685 .wait_for_idle = soc15_common_wait_for_idle,
1686 .soft_reset = soc15_common_soft_reset,
1687 .set_clockgating_state = soc15_common_set_clockgating_state,
1688 .set_powergating_state = soc15_common_set_powergating_state,
1689 .get_clockgating_state= soc15_common_get_clockgating_state,
1690 };
1691