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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2012 Avionic Design GmbH
4  * Copyright (C) 2012-2016 NVIDIA CORPORATION.  All rights reserved.
5  */
6 
7 #include <linux/bitops.h>
8 #include <linux/host1x.h>
9 #include <linux/idr.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 
14 #include <drm/drm_aperture.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_debugfs.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_ioctl.h>
21 #include <drm/drm_prime.h>
22 #include <drm/drm_vblank.h>
23 
24 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
25 #include <asm/dma-iommu.h>
26 #endif
27 
28 #include "dc.h"
29 #include "drm.h"
30 #include "gem.h"
31 #include "uapi.h"
32 
33 #define DRIVER_NAME "tegra"
34 #define DRIVER_DESC "NVIDIA Tegra graphics"
35 #define DRIVER_DATE "20120330"
36 #define DRIVER_MAJOR 1
37 #define DRIVER_MINOR 0
38 #define DRIVER_PATCHLEVEL 0
39 
40 #define CARVEOUT_SZ SZ_64M
41 #define CDMA_GATHER_FETCHES_MAX_NB 16383
42 
tegra_atomic_check(struct drm_device * drm,struct drm_atomic_state * state)43 static int tegra_atomic_check(struct drm_device *drm,
44 			      struct drm_atomic_state *state)
45 {
46 	int err;
47 
48 	err = drm_atomic_helper_check(drm, state);
49 	if (err < 0)
50 		return err;
51 
52 	return tegra_display_hub_atomic_check(drm, state);
53 }
54 
55 static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
56 	.fb_create = tegra_fb_create,
57 #ifdef CONFIG_DRM_FBDEV_EMULATION
58 	.output_poll_changed = drm_fb_helper_output_poll_changed,
59 #endif
60 	.atomic_check = tegra_atomic_check,
61 	.atomic_commit = drm_atomic_helper_commit,
62 };
63 
tegra_atomic_post_commit(struct drm_device * drm,struct drm_atomic_state * old_state)64 static void tegra_atomic_post_commit(struct drm_device *drm,
65 				     struct drm_atomic_state *old_state)
66 {
67 	struct drm_crtc_state *old_crtc_state __maybe_unused;
68 	struct drm_crtc *crtc;
69 	unsigned int i;
70 
71 	for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
72 		tegra_crtc_atomic_post_commit(crtc, old_state);
73 }
74 
tegra_atomic_commit_tail(struct drm_atomic_state * old_state)75 static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
76 {
77 	struct drm_device *drm = old_state->dev;
78 	struct tegra_drm *tegra = drm->dev_private;
79 
80 	if (tegra->hub) {
81 		bool fence_cookie = dma_fence_begin_signalling();
82 
83 		drm_atomic_helper_commit_modeset_disables(drm, old_state);
84 		tegra_display_hub_atomic_commit(drm, old_state);
85 		drm_atomic_helper_commit_planes(drm, old_state, 0);
86 		drm_atomic_helper_commit_modeset_enables(drm, old_state);
87 		drm_atomic_helper_commit_hw_done(old_state);
88 		dma_fence_end_signalling(fence_cookie);
89 		drm_atomic_helper_wait_for_vblanks(drm, old_state);
90 		drm_atomic_helper_cleanup_planes(drm, old_state);
91 	} else {
92 		drm_atomic_helper_commit_tail_rpm(old_state);
93 	}
94 
95 	tegra_atomic_post_commit(drm, old_state);
96 }
97 
98 static const struct drm_mode_config_helper_funcs
99 tegra_drm_mode_config_helpers = {
100 	.atomic_commit_tail = tegra_atomic_commit_tail,
101 };
102 
tegra_drm_open(struct drm_device * drm,struct drm_file * filp)103 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
104 {
105 	struct tegra_drm_file *fpriv;
106 
107 	fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
108 	if (!fpriv)
109 		return -ENOMEM;
110 
111 	idr_init_base(&fpriv->legacy_contexts, 1);
112 	xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
113 	xa_init(&fpriv->syncpoints);
114 	mutex_init(&fpriv->lock);
115 	filp->driver_priv = fpriv;
116 
117 	return 0;
118 }
119 
tegra_drm_context_free(struct tegra_drm_context * context)120 static void tegra_drm_context_free(struct tegra_drm_context *context)
121 {
122 	context->client->ops->close_channel(context);
123 	kfree(context);
124 }
125 
host1x_reloc_copy_from_user(struct host1x_reloc * dest,struct drm_tegra_reloc __user * src,struct drm_device * drm,struct drm_file * file)126 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
127 				       struct drm_tegra_reloc __user *src,
128 				       struct drm_device *drm,
129 				       struct drm_file *file)
130 {
131 	u32 cmdbuf, target;
132 	int err;
133 
134 	err = get_user(cmdbuf, &src->cmdbuf.handle);
135 	if (err < 0)
136 		return err;
137 
138 	err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
139 	if (err < 0)
140 		return err;
141 
142 	err = get_user(target, &src->target.handle);
143 	if (err < 0)
144 		return err;
145 
146 	err = get_user(dest->target.offset, &src->target.offset);
147 	if (err < 0)
148 		return err;
149 
150 	err = get_user(dest->shift, &src->shift);
151 	if (err < 0)
152 		return err;
153 
154 	dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
155 
156 	dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
157 	if (!dest->cmdbuf.bo)
158 		return -ENOENT;
159 
160 	dest->target.bo = tegra_gem_lookup(file, target);
161 	if (!dest->target.bo)
162 		return -ENOENT;
163 
164 	return 0;
165 }
166 
tegra_drm_submit(struct tegra_drm_context * context,struct drm_tegra_submit * args,struct drm_device * drm,struct drm_file * file)167 int tegra_drm_submit(struct tegra_drm_context *context,
168 		     struct drm_tegra_submit *args, struct drm_device *drm,
169 		     struct drm_file *file)
170 {
171 	struct host1x_client *client = &context->client->base;
172 	unsigned int num_cmdbufs = args->num_cmdbufs;
173 	unsigned int num_relocs = args->num_relocs;
174 	struct drm_tegra_cmdbuf __user *user_cmdbufs;
175 	struct drm_tegra_reloc __user *user_relocs;
176 	struct drm_tegra_syncpt __user *user_syncpt;
177 	struct drm_tegra_syncpt syncpt;
178 	struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
179 	struct drm_gem_object **refs;
180 	struct host1x_syncpt *sp = NULL;
181 	struct host1x_job *job;
182 	unsigned int num_refs;
183 	int err;
184 
185 	user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
186 	user_relocs = u64_to_user_ptr(args->relocs);
187 	user_syncpt = u64_to_user_ptr(args->syncpts);
188 
189 	/* We don't yet support other than one syncpt_incr struct per submit */
190 	if (args->num_syncpts != 1)
191 		return -EINVAL;
192 
193 	/* We don't yet support waitchks */
194 	if (args->num_waitchks != 0)
195 		return -EINVAL;
196 
197 	job = host1x_job_alloc(context->channel, args->num_cmdbufs,
198 			       args->num_relocs, false);
199 	if (!job)
200 		return -ENOMEM;
201 
202 	job->num_relocs = args->num_relocs;
203 	job->client = client;
204 	job->class = client->class;
205 	job->serialize = true;
206 	job->syncpt_recovery = true;
207 
208 	/*
209 	 * Track referenced BOs so that they can be unreferenced after the
210 	 * submission is complete.
211 	 */
212 	num_refs = num_cmdbufs + num_relocs * 2;
213 
214 	refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
215 	if (!refs) {
216 		err = -ENOMEM;
217 		goto put;
218 	}
219 
220 	/* reuse as an iterator later */
221 	num_refs = 0;
222 
223 	while (num_cmdbufs) {
224 		struct drm_tegra_cmdbuf cmdbuf;
225 		struct host1x_bo *bo;
226 		struct tegra_bo *obj;
227 		u64 offset;
228 
229 		if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
230 			err = -EFAULT;
231 			goto fail;
232 		}
233 
234 		/*
235 		 * The maximum number of CDMA gather fetches is 16383, a higher
236 		 * value means the words count is malformed.
237 		 */
238 		if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
239 			err = -EINVAL;
240 			goto fail;
241 		}
242 
243 		bo = tegra_gem_lookup(file, cmdbuf.handle);
244 		if (!bo) {
245 			err = -ENOENT;
246 			goto fail;
247 		}
248 
249 		offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
250 		obj = host1x_to_tegra_bo(bo);
251 		refs[num_refs++] = &obj->gem;
252 
253 		/*
254 		 * Gather buffer base address must be 4-bytes aligned,
255 		 * unaligned offset is malformed and cause commands stream
256 		 * corruption on the buffer address relocation.
257 		 */
258 		if (offset & 3 || offset > obj->gem.size) {
259 			err = -EINVAL;
260 			goto fail;
261 		}
262 
263 		host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
264 		num_cmdbufs--;
265 		user_cmdbufs++;
266 	}
267 
268 	/* copy and resolve relocations from submit */
269 	while (num_relocs--) {
270 		struct host1x_reloc *reloc;
271 		struct tegra_bo *obj;
272 
273 		err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
274 						  &user_relocs[num_relocs], drm,
275 						  file);
276 		if (err < 0)
277 			goto fail;
278 
279 		reloc = &job->relocs[num_relocs];
280 		obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
281 		refs[num_refs++] = &obj->gem;
282 
283 		/*
284 		 * The unaligned cmdbuf offset will cause an unaligned write
285 		 * during of the relocations patching, corrupting the commands
286 		 * stream.
287 		 */
288 		if (reloc->cmdbuf.offset & 3 ||
289 		    reloc->cmdbuf.offset >= obj->gem.size) {
290 			err = -EINVAL;
291 			goto fail;
292 		}
293 
294 		obj = host1x_to_tegra_bo(reloc->target.bo);
295 		refs[num_refs++] = &obj->gem;
296 
297 		if (reloc->target.offset >= obj->gem.size) {
298 			err = -EINVAL;
299 			goto fail;
300 		}
301 	}
302 
303 	if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
304 		err = -EFAULT;
305 		goto fail;
306 	}
307 
308 	/* Syncpoint ref will be dropped on job release. */
309 	sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
310 	if (!sp) {
311 		err = -ENOENT;
312 		goto fail;
313 	}
314 
315 	job->is_addr_reg = context->client->ops->is_addr_reg;
316 	job->is_valid_class = context->client->ops->is_valid_class;
317 	job->syncpt_incrs = syncpt.incrs;
318 	job->syncpt = sp;
319 	job->timeout = 10000;
320 
321 	if (args->timeout && args->timeout < 10000)
322 		job->timeout = args->timeout;
323 
324 	err = host1x_job_pin(job, context->client->base.dev);
325 	if (err)
326 		goto fail;
327 
328 	err = host1x_job_submit(job);
329 	if (err) {
330 		host1x_job_unpin(job);
331 		goto fail;
332 	}
333 
334 	args->fence = job->syncpt_end;
335 
336 fail:
337 	while (num_refs--)
338 		drm_gem_object_put(refs[num_refs]);
339 
340 	kfree(refs);
341 
342 put:
343 	host1x_job_put(job);
344 	return err;
345 }
346 
347 
348 #ifdef CONFIG_DRM_TEGRA_STAGING
tegra_gem_create(struct drm_device * drm,void * data,struct drm_file * file)349 static int tegra_gem_create(struct drm_device *drm, void *data,
350 			    struct drm_file *file)
351 {
352 	struct drm_tegra_gem_create *args = data;
353 	struct tegra_bo *bo;
354 
355 	bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
356 					 &args->handle);
357 	if (IS_ERR(bo))
358 		return PTR_ERR(bo);
359 
360 	return 0;
361 }
362 
tegra_gem_mmap(struct drm_device * drm,void * data,struct drm_file * file)363 static int tegra_gem_mmap(struct drm_device *drm, void *data,
364 			  struct drm_file *file)
365 {
366 	struct drm_tegra_gem_mmap *args = data;
367 	struct drm_gem_object *gem;
368 	struct tegra_bo *bo;
369 
370 	gem = drm_gem_object_lookup(file, args->handle);
371 	if (!gem)
372 		return -EINVAL;
373 
374 	bo = to_tegra_bo(gem);
375 
376 	args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
377 
378 	drm_gem_object_put(gem);
379 
380 	return 0;
381 }
382 
tegra_syncpt_read(struct drm_device * drm,void * data,struct drm_file * file)383 static int tegra_syncpt_read(struct drm_device *drm, void *data,
384 			     struct drm_file *file)
385 {
386 	struct host1x *host = dev_get_drvdata(drm->dev->parent);
387 	struct drm_tegra_syncpt_read *args = data;
388 	struct host1x_syncpt *sp;
389 
390 	sp = host1x_syncpt_get_by_id_noref(host, args->id);
391 	if (!sp)
392 		return -EINVAL;
393 
394 	args->value = host1x_syncpt_read_min(sp);
395 	return 0;
396 }
397 
tegra_syncpt_incr(struct drm_device * drm,void * data,struct drm_file * file)398 static int tegra_syncpt_incr(struct drm_device *drm, void *data,
399 			     struct drm_file *file)
400 {
401 	struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
402 	struct drm_tegra_syncpt_incr *args = data;
403 	struct host1x_syncpt *sp;
404 
405 	sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
406 	if (!sp)
407 		return -EINVAL;
408 
409 	return host1x_syncpt_incr(sp);
410 }
411 
tegra_syncpt_wait(struct drm_device * drm,void * data,struct drm_file * file)412 static int tegra_syncpt_wait(struct drm_device *drm, void *data,
413 			     struct drm_file *file)
414 {
415 	struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
416 	struct drm_tegra_syncpt_wait *args = data;
417 	struct host1x_syncpt *sp;
418 
419 	sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
420 	if (!sp)
421 		return -EINVAL;
422 
423 	return host1x_syncpt_wait(sp, args->thresh,
424 				  msecs_to_jiffies(args->timeout),
425 				  &args->value);
426 }
427 
tegra_client_open(struct tegra_drm_file * fpriv,struct tegra_drm_client * client,struct tegra_drm_context * context)428 static int tegra_client_open(struct tegra_drm_file *fpriv,
429 			     struct tegra_drm_client *client,
430 			     struct tegra_drm_context *context)
431 {
432 	int err;
433 
434 	err = client->ops->open_channel(client, context);
435 	if (err < 0)
436 		return err;
437 
438 	err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
439 	if (err < 0) {
440 		client->ops->close_channel(context);
441 		return err;
442 	}
443 
444 	context->client = client;
445 	context->id = err;
446 
447 	return 0;
448 }
449 
tegra_open_channel(struct drm_device * drm,void * data,struct drm_file * file)450 static int tegra_open_channel(struct drm_device *drm, void *data,
451 			      struct drm_file *file)
452 {
453 	struct tegra_drm_file *fpriv = file->driver_priv;
454 	struct tegra_drm *tegra = drm->dev_private;
455 	struct drm_tegra_open_channel *args = data;
456 	struct tegra_drm_context *context;
457 	struct tegra_drm_client *client;
458 	int err = -ENODEV;
459 
460 	context = kzalloc(sizeof(*context), GFP_KERNEL);
461 	if (!context)
462 		return -ENOMEM;
463 
464 	mutex_lock(&fpriv->lock);
465 
466 	list_for_each_entry(client, &tegra->clients, list)
467 		if (client->base.class == args->client) {
468 			err = tegra_client_open(fpriv, client, context);
469 			if (err < 0)
470 				break;
471 
472 			args->context = context->id;
473 			break;
474 		}
475 
476 	if (err < 0)
477 		kfree(context);
478 
479 	mutex_unlock(&fpriv->lock);
480 	return err;
481 }
482 
tegra_close_channel(struct drm_device * drm,void * data,struct drm_file * file)483 static int tegra_close_channel(struct drm_device *drm, void *data,
484 			       struct drm_file *file)
485 {
486 	struct tegra_drm_file *fpriv = file->driver_priv;
487 	struct drm_tegra_close_channel *args = data;
488 	struct tegra_drm_context *context;
489 	int err = 0;
490 
491 	mutex_lock(&fpriv->lock);
492 
493 	context = idr_find(&fpriv->legacy_contexts, args->context);
494 	if (!context) {
495 		err = -EINVAL;
496 		goto unlock;
497 	}
498 
499 	idr_remove(&fpriv->legacy_contexts, context->id);
500 	tegra_drm_context_free(context);
501 
502 unlock:
503 	mutex_unlock(&fpriv->lock);
504 	return err;
505 }
506 
tegra_get_syncpt(struct drm_device * drm,void * data,struct drm_file * file)507 static int tegra_get_syncpt(struct drm_device *drm, void *data,
508 			    struct drm_file *file)
509 {
510 	struct tegra_drm_file *fpriv = file->driver_priv;
511 	struct drm_tegra_get_syncpt *args = data;
512 	struct tegra_drm_context *context;
513 	struct host1x_syncpt *syncpt;
514 	int err = 0;
515 
516 	mutex_lock(&fpriv->lock);
517 
518 	context = idr_find(&fpriv->legacy_contexts, args->context);
519 	if (!context) {
520 		err = -ENODEV;
521 		goto unlock;
522 	}
523 
524 	if (args->index >= context->client->base.num_syncpts) {
525 		err = -EINVAL;
526 		goto unlock;
527 	}
528 
529 	syncpt = context->client->base.syncpts[args->index];
530 	args->id = host1x_syncpt_id(syncpt);
531 
532 unlock:
533 	mutex_unlock(&fpriv->lock);
534 	return err;
535 }
536 
tegra_submit(struct drm_device * drm,void * data,struct drm_file * file)537 static int tegra_submit(struct drm_device *drm, void *data,
538 			struct drm_file *file)
539 {
540 	struct tegra_drm_file *fpriv = file->driver_priv;
541 	struct drm_tegra_submit *args = data;
542 	struct tegra_drm_context *context;
543 	int err;
544 
545 	mutex_lock(&fpriv->lock);
546 
547 	context = idr_find(&fpriv->legacy_contexts, args->context);
548 	if (!context) {
549 		err = -ENODEV;
550 		goto unlock;
551 	}
552 
553 	err = context->client->ops->submit(context, args, drm, file);
554 
555 unlock:
556 	mutex_unlock(&fpriv->lock);
557 	return err;
558 }
559 
tegra_get_syncpt_base(struct drm_device * drm,void * data,struct drm_file * file)560 static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
561 				 struct drm_file *file)
562 {
563 	struct tegra_drm_file *fpriv = file->driver_priv;
564 	struct drm_tegra_get_syncpt_base *args = data;
565 	struct tegra_drm_context *context;
566 	struct host1x_syncpt_base *base;
567 	struct host1x_syncpt *syncpt;
568 	int err = 0;
569 
570 	mutex_lock(&fpriv->lock);
571 
572 	context = idr_find(&fpriv->legacy_contexts, args->context);
573 	if (!context) {
574 		err = -ENODEV;
575 		goto unlock;
576 	}
577 
578 	if (args->syncpt >= context->client->base.num_syncpts) {
579 		err = -EINVAL;
580 		goto unlock;
581 	}
582 
583 	syncpt = context->client->base.syncpts[args->syncpt];
584 
585 	base = host1x_syncpt_get_base(syncpt);
586 	if (!base) {
587 		err = -ENXIO;
588 		goto unlock;
589 	}
590 
591 	args->id = host1x_syncpt_base_id(base);
592 
593 unlock:
594 	mutex_unlock(&fpriv->lock);
595 	return err;
596 }
597 
tegra_gem_set_tiling(struct drm_device * drm,void * data,struct drm_file * file)598 static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
599 				struct drm_file *file)
600 {
601 	struct drm_tegra_gem_set_tiling *args = data;
602 	enum tegra_bo_tiling_mode mode;
603 	struct drm_gem_object *gem;
604 	unsigned long value = 0;
605 	struct tegra_bo *bo;
606 
607 	switch (args->mode) {
608 	case DRM_TEGRA_GEM_TILING_MODE_PITCH:
609 		mode = TEGRA_BO_TILING_MODE_PITCH;
610 
611 		if (args->value != 0)
612 			return -EINVAL;
613 
614 		break;
615 
616 	case DRM_TEGRA_GEM_TILING_MODE_TILED:
617 		mode = TEGRA_BO_TILING_MODE_TILED;
618 
619 		if (args->value != 0)
620 			return -EINVAL;
621 
622 		break;
623 
624 	case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
625 		mode = TEGRA_BO_TILING_MODE_BLOCK;
626 
627 		if (args->value > 5)
628 			return -EINVAL;
629 
630 		value = args->value;
631 		break;
632 
633 	default:
634 		return -EINVAL;
635 	}
636 
637 	gem = drm_gem_object_lookup(file, args->handle);
638 	if (!gem)
639 		return -ENOENT;
640 
641 	bo = to_tegra_bo(gem);
642 
643 	bo->tiling.mode = mode;
644 	bo->tiling.value = value;
645 
646 	drm_gem_object_put(gem);
647 
648 	return 0;
649 }
650 
tegra_gem_get_tiling(struct drm_device * drm,void * data,struct drm_file * file)651 static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
652 				struct drm_file *file)
653 {
654 	struct drm_tegra_gem_get_tiling *args = data;
655 	struct drm_gem_object *gem;
656 	struct tegra_bo *bo;
657 	int err = 0;
658 
659 	gem = drm_gem_object_lookup(file, args->handle);
660 	if (!gem)
661 		return -ENOENT;
662 
663 	bo = to_tegra_bo(gem);
664 
665 	switch (bo->tiling.mode) {
666 	case TEGRA_BO_TILING_MODE_PITCH:
667 		args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
668 		args->value = 0;
669 		break;
670 
671 	case TEGRA_BO_TILING_MODE_TILED:
672 		args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
673 		args->value = 0;
674 		break;
675 
676 	case TEGRA_BO_TILING_MODE_BLOCK:
677 		args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
678 		args->value = bo->tiling.value;
679 		break;
680 
681 	default:
682 		err = -EINVAL;
683 		break;
684 	}
685 
686 	drm_gem_object_put(gem);
687 
688 	return err;
689 }
690 
tegra_gem_set_flags(struct drm_device * drm,void * data,struct drm_file * file)691 static int tegra_gem_set_flags(struct drm_device *drm, void *data,
692 			       struct drm_file *file)
693 {
694 	struct drm_tegra_gem_set_flags *args = data;
695 	struct drm_gem_object *gem;
696 	struct tegra_bo *bo;
697 
698 	if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
699 		return -EINVAL;
700 
701 	gem = drm_gem_object_lookup(file, args->handle);
702 	if (!gem)
703 		return -ENOENT;
704 
705 	bo = to_tegra_bo(gem);
706 	bo->flags = 0;
707 
708 	if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
709 		bo->flags |= TEGRA_BO_BOTTOM_UP;
710 
711 	drm_gem_object_put(gem);
712 
713 	return 0;
714 }
715 
tegra_gem_get_flags(struct drm_device * drm,void * data,struct drm_file * file)716 static int tegra_gem_get_flags(struct drm_device *drm, void *data,
717 			       struct drm_file *file)
718 {
719 	struct drm_tegra_gem_get_flags *args = data;
720 	struct drm_gem_object *gem;
721 	struct tegra_bo *bo;
722 
723 	gem = drm_gem_object_lookup(file, args->handle);
724 	if (!gem)
725 		return -ENOENT;
726 
727 	bo = to_tegra_bo(gem);
728 	args->flags = 0;
729 
730 	if (bo->flags & TEGRA_BO_BOTTOM_UP)
731 		args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
732 
733 	drm_gem_object_put(gem);
734 
735 	return 0;
736 }
737 #endif
738 
739 static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
740 #ifdef CONFIG_DRM_TEGRA_STAGING
741 	DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open,
742 			  DRM_RENDER_ALLOW),
743 	DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close,
744 			  DRM_RENDER_ALLOW),
745 	DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map,
746 			  DRM_RENDER_ALLOW),
747 	DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
748 			  DRM_RENDER_ALLOW),
749 	DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit,
750 			  DRM_RENDER_ALLOW),
751 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate,
752 			  DRM_RENDER_ALLOW),
753 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free,
754 			  DRM_RENDER_ALLOW),
755 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_WAIT, tegra_drm_ioctl_syncpoint_wait,
756 			  DRM_RENDER_ALLOW),
757 
758 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW),
759 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW),
760 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
761 			  DRM_RENDER_ALLOW),
762 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
763 			  DRM_RENDER_ALLOW),
764 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
765 			  DRM_RENDER_ALLOW),
766 	DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
767 			  DRM_RENDER_ALLOW),
768 	DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
769 			  DRM_RENDER_ALLOW),
770 	DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
771 			  DRM_RENDER_ALLOW),
772 	DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
773 			  DRM_RENDER_ALLOW),
774 	DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
775 			  DRM_RENDER_ALLOW),
776 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
777 			  DRM_RENDER_ALLOW),
778 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
779 			  DRM_RENDER_ALLOW),
780 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
781 			  DRM_RENDER_ALLOW),
782 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
783 			  DRM_RENDER_ALLOW),
784 #endif
785 };
786 
787 static const struct file_operations tegra_drm_fops = {
788 	.owner = THIS_MODULE,
789 	.open = drm_open,
790 	.release = drm_release,
791 	.unlocked_ioctl = drm_ioctl,
792 	.mmap = tegra_drm_mmap,
793 	.poll = drm_poll,
794 	.read = drm_read,
795 	.compat_ioctl = drm_compat_ioctl,
796 	.llseek = noop_llseek,
797 };
798 
tegra_drm_context_cleanup(int id,void * p,void * data)799 static int tegra_drm_context_cleanup(int id, void *p, void *data)
800 {
801 	struct tegra_drm_context *context = p;
802 
803 	tegra_drm_context_free(context);
804 
805 	return 0;
806 }
807 
tegra_drm_postclose(struct drm_device * drm,struct drm_file * file)808 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
809 {
810 	struct tegra_drm_file *fpriv = file->driver_priv;
811 
812 	mutex_lock(&fpriv->lock);
813 	idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
814 	tegra_drm_uapi_close_file(fpriv);
815 	mutex_unlock(&fpriv->lock);
816 
817 	idr_destroy(&fpriv->legacy_contexts);
818 	mutex_destroy(&fpriv->lock);
819 	kfree(fpriv);
820 }
821 
822 #ifdef CONFIG_DEBUG_FS
tegra_debugfs_framebuffers(struct seq_file * s,void * data)823 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
824 {
825 	struct drm_info_node *node = (struct drm_info_node *)s->private;
826 	struct drm_device *drm = node->minor->dev;
827 	struct drm_framebuffer *fb;
828 
829 	mutex_lock(&drm->mode_config.fb_lock);
830 
831 	list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
832 		seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
833 			   fb->base.id, fb->width, fb->height,
834 			   fb->format->depth,
835 			   fb->format->cpp[0] * 8,
836 			   drm_framebuffer_read_refcount(fb));
837 	}
838 
839 	mutex_unlock(&drm->mode_config.fb_lock);
840 
841 	return 0;
842 }
843 
tegra_debugfs_iova(struct seq_file * s,void * data)844 static int tegra_debugfs_iova(struct seq_file *s, void *data)
845 {
846 	struct drm_info_node *node = (struct drm_info_node *)s->private;
847 	struct drm_device *drm = node->minor->dev;
848 	struct tegra_drm *tegra = drm->dev_private;
849 	struct drm_printer p = drm_seq_file_printer(s);
850 
851 	if (tegra->domain) {
852 		mutex_lock(&tegra->mm_lock);
853 		drm_mm_print(&tegra->mm, &p);
854 		mutex_unlock(&tegra->mm_lock);
855 	}
856 
857 	return 0;
858 }
859 
860 static struct drm_info_list tegra_debugfs_list[] = {
861 	{ "framebuffers", tegra_debugfs_framebuffers, 0 },
862 	{ "iova", tegra_debugfs_iova, 0 },
863 };
864 
tegra_debugfs_init(struct drm_minor * minor)865 static void tegra_debugfs_init(struct drm_minor *minor)
866 {
867 	drm_debugfs_create_files(tegra_debugfs_list,
868 				 ARRAY_SIZE(tegra_debugfs_list),
869 				 minor->debugfs_root, minor);
870 }
871 #endif
872 
873 static const struct drm_driver tegra_drm_driver = {
874 	.driver_features = DRIVER_MODESET | DRIVER_GEM |
875 			   DRIVER_ATOMIC | DRIVER_RENDER | DRIVER_SYNCOBJ,
876 	.open = tegra_drm_open,
877 	.postclose = tegra_drm_postclose,
878 	.lastclose = drm_fb_helper_lastclose,
879 
880 #if defined(CONFIG_DEBUG_FS)
881 	.debugfs_init = tegra_debugfs_init,
882 #endif
883 
884 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
885 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
886 	.gem_prime_import = tegra_gem_prime_import,
887 
888 	.dumb_create = tegra_bo_dumb_create,
889 
890 	.ioctls = tegra_drm_ioctls,
891 	.num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
892 	.fops = &tegra_drm_fops,
893 
894 	.name = DRIVER_NAME,
895 	.desc = DRIVER_DESC,
896 	.date = DRIVER_DATE,
897 	.major = DRIVER_MAJOR,
898 	.minor = DRIVER_MINOR,
899 	.patchlevel = DRIVER_PATCHLEVEL,
900 };
901 
tegra_drm_register_client(struct tegra_drm * tegra,struct tegra_drm_client * client)902 int tegra_drm_register_client(struct tegra_drm *tegra,
903 			      struct tegra_drm_client *client)
904 {
905 	/*
906 	 * When MLOCKs are implemented, change to allocate a shared channel
907 	 * only when MLOCKs are disabled.
908 	 */
909 	client->shared_channel = host1x_channel_request(&client->base);
910 	if (!client->shared_channel)
911 		return -EBUSY;
912 
913 	mutex_lock(&tegra->clients_lock);
914 	list_add_tail(&client->list, &tegra->clients);
915 	client->drm = tegra;
916 	mutex_unlock(&tegra->clients_lock);
917 
918 	return 0;
919 }
920 
tegra_drm_unregister_client(struct tegra_drm * tegra,struct tegra_drm_client * client)921 int tegra_drm_unregister_client(struct tegra_drm *tegra,
922 				struct tegra_drm_client *client)
923 {
924 	mutex_lock(&tegra->clients_lock);
925 	list_del_init(&client->list);
926 	client->drm = NULL;
927 	mutex_unlock(&tegra->clients_lock);
928 
929 	if (client->shared_channel)
930 		host1x_channel_put(client->shared_channel);
931 
932 	return 0;
933 }
934 
host1x_client_iommu_attach(struct host1x_client * client)935 int host1x_client_iommu_attach(struct host1x_client *client)
936 {
937 	struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
938 	struct drm_device *drm = dev_get_drvdata(client->host);
939 	struct tegra_drm *tegra = drm->dev_private;
940 	struct iommu_group *group = NULL;
941 	int err;
942 
943 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
944 	if (client->dev->archdata.mapping) {
945 		struct dma_iommu_mapping *mapping =
946 				to_dma_iommu_mapping(client->dev);
947 		arm_iommu_detach_device(client->dev);
948 		arm_iommu_release_mapping(mapping);
949 
950 		domain = iommu_get_domain_for_dev(client->dev);
951 	}
952 #endif
953 
954 	/*
955 	 * If the host1x client is already attached to an IOMMU domain that is
956 	 * not the shared IOMMU domain, don't try to attach it to a different
957 	 * domain. This allows using the IOMMU-backed DMA API.
958 	 */
959 	if (domain && domain != tegra->domain)
960 		return 0;
961 
962 	if (tegra->domain) {
963 		group = iommu_group_get(client->dev);
964 		if (!group)
965 			return -ENODEV;
966 
967 		if (domain != tegra->domain) {
968 			err = iommu_attach_group(tegra->domain, group);
969 			if (err < 0) {
970 				iommu_group_put(group);
971 				return err;
972 			}
973 		}
974 
975 		tegra->use_explicit_iommu = true;
976 	}
977 
978 	client->group = group;
979 
980 	return 0;
981 }
982 
host1x_client_iommu_detach(struct host1x_client * client)983 void host1x_client_iommu_detach(struct host1x_client *client)
984 {
985 	struct drm_device *drm = dev_get_drvdata(client->host);
986 	struct tegra_drm *tegra = drm->dev_private;
987 	struct iommu_domain *domain;
988 
989 	if (client->group) {
990 		/*
991 		 * Devices that are part of the same group may no longer be
992 		 * attached to a domain at this point because their group may
993 		 * have been detached by an earlier client.
994 		 */
995 		domain = iommu_get_domain_for_dev(client->dev);
996 		if (domain)
997 			iommu_detach_group(tegra->domain, client->group);
998 
999 		iommu_group_put(client->group);
1000 		client->group = NULL;
1001 	}
1002 }
1003 
tegra_drm_alloc(struct tegra_drm * tegra,size_t size,dma_addr_t * dma)1004 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
1005 {
1006 	struct iova *alloc;
1007 	void *virt;
1008 	gfp_t gfp;
1009 	int err;
1010 
1011 	if (tegra->domain)
1012 		size = iova_align(&tegra->carveout.domain, size);
1013 	else
1014 		size = PAGE_ALIGN(size);
1015 
1016 	gfp = GFP_KERNEL | __GFP_ZERO;
1017 	if (!tegra->domain) {
1018 		/*
1019 		 * Many units only support 32-bit addresses, even on 64-bit
1020 		 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1021 		 * virtual address space, force allocations to be in the
1022 		 * lower 32-bit range.
1023 		 */
1024 		gfp |= GFP_DMA;
1025 	}
1026 
1027 	virt = (void *)__get_free_pages(gfp, get_order(size));
1028 	if (!virt)
1029 		return ERR_PTR(-ENOMEM);
1030 
1031 	if (!tegra->domain) {
1032 		/*
1033 		 * If IOMMU is disabled, devices address physical memory
1034 		 * directly.
1035 		 */
1036 		*dma = virt_to_phys(virt);
1037 		return virt;
1038 	}
1039 
1040 	alloc = alloc_iova(&tegra->carveout.domain,
1041 			   size >> tegra->carveout.shift,
1042 			   tegra->carveout.limit, true);
1043 	if (!alloc) {
1044 		err = -EBUSY;
1045 		goto free_pages;
1046 	}
1047 
1048 	*dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1049 	err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1050 			size, IOMMU_READ | IOMMU_WRITE);
1051 	if (err < 0)
1052 		goto free_iova;
1053 
1054 	return virt;
1055 
1056 free_iova:
1057 	__free_iova(&tegra->carveout.domain, alloc);
1058 free_pages:
1059 	free_pages((unsigned long)virt, get_order(size));
1060 
1061 	return ERR_PTR(err);
1062 }
1063 
tegra_drm_free(struct tegra_drm * tegra,size_t size,void * virt,dma_addr_t dma)1064 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1065 		    dma_addr_t dma)
1066 {
1067 	if (tegra->domain)
1068 		size = iova_align(&tegra->carveout.domain, size);
1069 	else
1070 		size = PAGE_ALIGN(size);
1071 
1072 	if (tegra->domain) {
1073 		iommu_unmap(tegra->domain, dma, size);
1074 		free_iova(&tegra->carveout.domain,
1075 			  iova_pfn(&tegra->carveout.domain, dma));
1076 	}
1077 
1078 	free_pages((unsigned long)virt, get_order(size));
1079 }
1080 
host1x_drm_wants_iommu(struct host1x_device * dev)1081 static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1082 {
1083 	struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1084 	struct iommu_domain *domain;
1085 
1086 	/* Our IOMMU usage policy doesn't currently play well with GART */
1087 	if (of_machine_is_compatible("nvidia,tegra20"))
1088 		return false;
1089 
1090 	/*
1091 	 * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1092 	 * likely to be allocated beyond the 32-bit boundary if sufficient
1093 	 * system memory is available. This is problematic on earlier Tegra
1094 	 * generations where host1x supports a maximum of 32 address bits in
1095 	 * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1096 	 * as well it won't be able to process buffers allocated beyond the
1097 	 * 32-bit boundary.
1098 	 *
1099 	 * The DMA API will use bounce buffers in this case, so that could
1100 	 * perhaps still be made to work, even if less efficient, but there
1101 	 * is another catch: in order to perform cache maintenance on pages
1102 	 * allocated for discontiguous buffers we need to map and unmap the
1103 	 * SG table representing these buffers. This is fine for something
1104 	 * small like a push buffer, but it exhausts the bounce buffer pool
1105 	 * (typically on the order of a few MiB) for framebuffers (many MiB
1106 	 * for any modern resolution).
1107 	 *
1108 	 * Work around this by making sure that Tegra DRM clients only use
1109 	 * an IOMMU if the parent host1x also uses an IOMMU.
1110 	 *
1111 	 * Note that there's still a small gap here that we don't cover: if
1112 	 * the DMA API is backed by an IOMMU there's no way to control which
1113 	 * device is attached to an IOMMU and which isn't, except via wiring
1114 	 * up the device tree appropriately. This is considered an problem
1115 	 * of integration, so care must be taken for the DT to be consistent.
1116 	 */
1117 	domain = iommu_get_domain_for_dev(dev->dev.parent);
1118 
1119 	/*
1120 	 * Tegra20 and Tegra30 don't support addressing memory beyond the
1121 	 * 32-bit boundary, so the regular GATHER opcodes will always be
1122 	 * sufficient and whether or not the host1x is attached to an IOMMU
1123 	 * doesn't matter.
1124 	 */
1125 	if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1126 		return true;
1127 
1128 	return domain != NULL;
1129 }
1130 
host1x_drm_probe(struct host1x_device * dev)1131 static int host1x_drm_probe(struct host1x_device *dev)
1132 {
1133 	struct tegra_drm *tegra;
1134 	struct drm_device *drm;
1135 	int err;
1136 
1137 	drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1138 	if (IS_ERR(drm))
1139 		return PTR_ERR(drm);
1140 
1141 	tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
1142 	if (!tegra) {
1143 		err = -ENOMEM;
1144 		goto put;
1145 	}
1146 
1147 	if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1148 		tegra->domain = iommu_domain_alloc(&platform_bus_type);
1149 		if (!tegra->domain) {
1150 			err = -ENOMEM;
1151 			goto free;
1152 		}
1153 
1154 		err = iova_cache_get();
1155 		if (err < 0)
1156 			goto domain;
1157 	}
1158 
1159 	mutex_init(&tegra->clients_lock);
1160 	INIT_LIST_HEAD(&tegra->clients);
1161 
1162 	dev_set_drvdata(&dev->dev, drm);
1163 	drm->dev_private = tegra;
1164 	tegra->drm = drm;
1165 
1166 	drm_mode_config_init(drm);
1167 
1168 	drm->mode_config.min_width = 0;
1169 	drm->mode_config.min_height = 0;
1170 	drm->mode_config.max_width = 0;
1171 	drm->mode_config.max_height = 0;
1172 
1173 	drm->mode_config.normalize_zpos = true;
1174 
1175 	drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1176 	drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1177 
1178 	err = tegra_drm_fb_prepare(drm);
1179 	if (err < 0)
1180 		goto config;
1181 
1182 	drm_kms_helper_poll_init(drm);
1183 
1184 	err = host1x_device_init(dev);
1185 	if (err < 0)
1186 		goto fbdev;
1187 
1188 	/*
1189 	 * Now that all display controller have been initialized, the maximum
1190 	 * supported resolution is known and the bitmask for horizontal and
1191 	 * vertical bitfields can be computed.
1192 	 */
1193 	tegra->hmask = drm->mode_config.max_width - 1;
1194 	tegra->vmask = drm->mode_config.max_height - 1;
1195 
1196 	if (tegra->use_explicit_iommu) {
1197 		u64 carveout_start, carveout_end, gem_start, gem_end;
1198 		u64 dma_mask = dma_get_mask(&dev->dev);
1199 		dma_addr_t start, end;
1200 		unsigned long order;
1201 
1202 		start = tegra->domain->geometry.aperture_start & dma_mask;
1203 		end = tegra->domain->geometry.aperture_end & dma_mask;
1204 
1205 		gem_start = start;
1206 		gem_end = end - CARVEOUT_SZ;
1207 		carveout_start = gem_end + 1;
1208 		carveout_end = end;
1209 
1210 		order = __ffs(tegra->domain->pgsize_bitmap);
1211 		init_iova_domain(&tegra->carveout.domain, 1UL << order,
1212 				 carveout_start >> order);
1213 
1214 		tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1215 		tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1216 
1217 		drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1218 		mutex_init(&tegra->mm_lock);
1219 
1220 		DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1221 		DRM_DEBUG_DRIVER("  GEM: %#llx-%#llx\n", gem_start, gem_end);
1222 		DRM_DEBUG_DRIVER("  Carveout: %#llx-%#llx\n", carveout_start,
1223 				 carveout_end);
1224 	} else if (tegra->domain) {
1225 		iommu_domain_free(tegra->domain);
1226 		tegra->domain = NULL;
1227 		iova_cache_put();
1228 	}
1229 
1230 	if (tegra->hub) {
1231 		err = tegra_display_hub_prepare(tegra->hub);
1232 		if (err < 0)
1233 			goto device;
1234 	}
1235 
1236 	/* syncpoints are used for full 32-bit hardware VBLANK counters */
1237 	drm->max_vblank_count = 0xffffffff;
1238 
1239 	err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1240 	if (err < 0)
1241 		goto hub;
1242 
1243 	drm_mode_config_reset(drm);
1244 
1245 	err = drm_aperture_remove_framebuffers(false, &tegra_drm_driver);
1246 	if (err < 0)
1247 		goto hub;
1248 
1249 	err = tegra_drm_fb_init(drm);
1250 	if (err < 0)
1251 		goto hub;
1252 
1253 	err = drm_dev_register(drm, 0);
1254 	if (err < 0)
1255 		goto fb;
1256 
1257 	return 0;
1258 
1259 fb:
1260 	tegra_drm_fb_exit(drm);
1261 hub:
1262 	if (tegra->hub)
1263 		tegra_display_hub_cleanup(tegra->hub);
1264 device:
1265 	if (tegra->domain) {
1266 		mutex_destroy(&tegra->mm_lock);
1267 		drm_mm_takedown(&tegra->mm);
1268 		put_iova_domain(&tegra->carveout.domain);
1269 		iova_cache_put();
1270 	}
1271 
1272 	host1x_device_exit(dev);
1273 fbdev:
1274 	drm_kms_helper_poll_fini(drm);
1275 	tegra_drm_fb_free(drm);
1276 config:
1277 	drm_mode_config_cleanup(drm);
1278 domain:
1279 	if (tegra->domain)
1280 		iommu_domain_free(tegra->domain);
1281 free:
1282 	kfree(tegra);
1283 put:
1284 	drm_dev_put(drm);
1285 	return err;
1286 }
1287 
host1x_drm_remove(struct host1x_device * dev)1288 static int host1x_drm_remove(struct host1x_device *dev)
1289 {
1290 	struct drm_device *drm = dev_get_drvdata(&dev->dev);
1291 	struct tegra_drm *tegra = drm->dev_private;
1292 	int err;
1293 
1294 	drm_dev_unregister(drm);
1295 
1296 	drm_kms_helper_poll_fini(drm);
1297 	tegra_drm_fb_exit(drm);
1298 	drm_atomic_helper_shutdown(drm);
1299 	drm_mode_config_cleanup(drm);
1300 
1301 	if (tegra->hub)
1302 		tegra_display_hub_cleanup(tegra->hub);
1303 
1304 	err = host1x_device_exit(dev);
1305 	if (err < 0)
1306 		dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1307 
1308 	if (tegra->domain) {
1309 		mutex_destroy(&tegra->mm_lock);
1310 		drm_mm_takedown(&tegra->mm);
1311 		put_iova_domain(&tegra->carveout.domain);
1312 		iova_cache_put();
1313 		iommu_domain_free(tegra->domain);
1314 	}
1315 
1316 	kfree(tegra);
1317 	drm_dev_put(drm);
1318 
1319 	return 0;
1320 }
1321 
1322 #ifdef CONFIG_PM_SLEEP
host1x_drm_suspend(struct device * dev)1323 static int host1x_drm_suspend(struct device *dev)
1324 {
1325 	struct drm_device *drm = dev_get_drvdata(dev);
1326 
1327 	return drm_mode_config_helper_suspend(drm);
1328 }
1329 
host1x_drm_resume(struct device * dev)1330 static int host1x_drm_resume(struct device *dev)
1331 {
1332 	struct drm_device *drm = dev_get_drvdata(dev);
1333 
1334 	return drm_mode_config_helper_resume(drm);
1335 }
1336 #endif
1337 
1338 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1339 			 host1x_drm_resume);
1340 
1341 static const struct of_device_id host1x_drm_subdevs[] = {
1342 	{ .compatible = "nvidia,tegra20-dc", },
1343 	{ .compatible = "nvidia,tegra20-hdmi", },
1344 	{ .compatible = "nvidia,tegra20-gr2d", },
1345 	{ .compatible = "nvidia,tegra20-gr3d", },
1346 	{ .compatible = "nvidia,tegra30-dc", },
1347 	{ .compatible = "nvidia,tegra30-hdmi", },
1348 	{ .compatible = "nvidia,tegra30-gr2d", },
1349 	{ .compatible = "nvidia,tegra30-gr3d", },
1350 	{ .compatible = "nvidia,tegra114-dc", },
1351 	{ .compatible = "nvidia,tegra114-dsi", },
1352 	{ .compatible = "nvidia,tegra114-hdmi", },
1353 	{ .compatible = "nvidia,tegra114-gr2d", },
1354 	{ .compatible = "nvidia,tegra114-gr3d", },
1355 	{ .compatible = "nvidia,tegra124-dc", },
1356 	{ .compatible = "nvidia,tegra124-sor", },
1357 	{ .compatible = "nvidia,tegra124-hdmi", },
1358 	{ .compatible = "nvidia,tegra124-dsi", },
1359 	{ .compatible = "nvidia,tegra124-vic", },
1360 	{ .compatible = "nvidia,tegra132-dsi", },
1361 	{ .compatible = "nvidia,tegra210-dc", },
1362 	{ .compatible = "nvidia,tegra210-dsi", },
1363 	{ .compatible = "nvidia,tegra210-sor", },
1364 	{ .compatible = "nvidia,tegra210-sor1", },
1365 	{ .compatible = "nvidia,tegra210-vic", },
1366 	{ .compatible = "nvidia,tegra186-display", },
1367 	{ .compatible = "nvidia,tegra186-dc", },
1368 	{ .compatible = "nvidia,tegra186-sor", },
1369 	{ .compatible = "nvidia,tegra186-sor1", },
1370 	{ .compatible = "nvidia,tegra186-vic", },
1371 	{ .compatible = "nvidia,tegra194-display", },
1372 	{ .compatible = "nvidia,tegra194-dc", },
1373 	{ .compatible = "nvidia,tegra194-sor", },
1374 	{ .compatible = "nvidia,tegra194-vic", },
1375 	{ /* sentinel */ }
1376 };
1377 
1378 static struct host1x_driver host1x_drm_driver = {
1379 	.driver = {
1380 		.name = "drm",
1381 		.pm = &host1x_drm_pm_ops,
1382 	},
1383 	.probe = host1x_drm_probe,
1384 	.remove = host1x_drm_remove,
1385 	.subdevs = host1x_drm_subdevs,
1386 };
1387 
1388 static struct platform_driver * const drivers[] = {
1389 	&tegra_display_hub_driver,
1390 	&tegra_dc_driver,
1391 	&tegra_hdmi_driver,
1392 	&tegra_dsi_driver,
1393 	&tegra_dpaux_driver,
1394 	&tegra_sor_driver,
1395 	&tegra_gr2d_driver,
1396 	&tegra_gr3d_driver,
1397 	&tegra_vic_driver,
1398 };
1399 
host1x_drm_init(void)1400 static int __init host1x_drm_init(void)
1401 {
1402 	int err;
1403 
1404 	err = host1x_driver_register(&host1x_drm_driver);
1405 	if (err < 0)
1406 		return err;
1407 
1408 	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1409 	if (err < 0)
1410 		goto unregister_host1x;
1411 
1412 	return 0;
1413 
1414 unregister_host1x:
1415 	host1x_driver_unregister(&host1x_drm_driver);
1416 	return err;
1417 }
1418 module_init(host1x_drm_init);
1419 
host1x_drm_exit(void)1420 static void __exit host1x_drm_exit(void)
1421 {
1422 	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1423 	host1x_driver_unregister(&host1x_drm_driver);
1424 }
1425 module_exit(host1x_drm_exit);
1426 
1427 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1428 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1429 MODULE_LICENSE("GPL v2");
1430