1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "ior.h"
23
24 #include <subdev/timer.h>
25
26 void
tu102_sor_dp_vcpi(struct nvkm_ior * sor,int head,u8 slot,u8 slot_nr,u16 pbn,u16 aligned)27 tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
28 u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
29 {
30 struct nvkm_device *device = sor->disp->engine.subdev.device;
31 const u32 hoff = head * 0x800;
32
33 nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
34 nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
35 }
36
37 static int
tu102_sor_dp_links(struct nvkm_ior * sor,struct nvkm_i2c_aux * aux)38 tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
39 {
40 struct nvkm_device *device = sor->disp->engine.subdev.device;
41 const u32 soff = nv50_ior_base(sor);
42 const u32 loff = nv50_sor_link(sor);
43 u32 dpctrl = 0x00000000;
44 u32 clksor = 0x00000000;
45
46 clksor |= sor->dp.bw << 18;
47 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
48 if (sor->dp.mst)
49 dpctrl |= 0x40000000;
50 if (sor->dp.ef)
51 dpctrl |= 0x00004000;
52
53 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
54
55 /*XXX*/
56 nvkm_msec(device, 40, NVKM_DELAY);
57 nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
58 nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
59
60 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
61 return 0;
62 }
63
64 static const struct nvkm_ior_func
65 tu102_sor_hda = {
66 .route = {
67 .get = gm200_sor_route_get,
68 .set = gm200_sor_route_set,
69 },
70 .state = gv100_sor_state,
71 .power = nv50_sor_power,
72 .clock = gf119_sor_clock,
73 .hdmi = {
74 .ctrl = gv100_hdmi_ctrl,
75 .scdc = gm200_hdmi_scdc,
76 },
77 .dp = {
78 .lanes = { 0, 1, 2, 3 },
79 .links = tu102_sor_dp_links,
80 .power = g94_sor_dp_power,
81 .pattern = gm107_sor_dp_pattern,
82 .drive = gm200_sor_dp_drive,
83 .vcpi = tu102_sor_dp_vcpi,
84 .audio = gv100_sor_dp_audio,
85 .audio_sym = gv100_sor_dp_audio_sym,
86 .watermark = gv100_sor_dp_watermark,
87 },
88 .hda = {
89 .hpd = gf119_hda_hpd,
90 .eld = gf119_hda_eld,
91 .device_entry = gv100_hda_device_entry,
92 },
93 };
94
95 static const struct nvkm_ior_func
96 tu102_sor = {
97 .route = {
98 .get = gm200_sor_route_get,
99 .set = gm200_sor_route_set,
100 },
101 .state = gv100_sor_state,
102 .power = nv50_sor_power,
103 .clock = gf119_sor_clock,
104 .hdmi = {
105 .ctrl = gv100_hdmi_ctrl,
106 .scdc = gm200_hdmi_scdc,
107 },
108 .dp = {
109 .lanes = { 0, 1, 2, 3 },
110 .links = tu102_sor_dp_links,
111 .power = g94_sor_dp_power,
112 .pattern = gm107_sor_dp_pattern,
113 .drive = gm200_sor_dp_drive,
114 .vcpi = tu102_sor_dp_vcpi,
115 .audio = gv100_sor_dp_audio,
116 .audio_sym = gv100_sor_dp_audio_sym,
117 .watermark = gv100_sor_dp_watermark,
118 },
119 };
120
121 int
tu102_sor_new(struct nvkm_disp * disp,int id)122 tu102_sor_new(struct nvkm_disp *disp, int id)
123 {
124 struct nvkm_device *device = disp->engine.subdev.device;
125 u32 hda = nvkm_rd32(device, 0x08a15c);
126 if (hda & BIT(id))
127 return nvkm_ior_new_(&tu102_sor_hda, disp, SOR, id);
128 return nvkm_ior_new_(&tu102_sor, disp, SOR, id);
129 }
130