1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35 #include "i915_drv.h"
36 #include "gvt.h"
37
get_edp_pipe(struct intel_vgpu * vgpu)38 static int get_edp_pipe(struct intel_vgpu *vgpu)
39 {
40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
41 int pipe = -1;
42
43 switch (data & TRANS_DDI_EDP_INPUT_MASK) {
44 case TRANS_DDI_EDP_INPUT_A_ON:
45 case TRANS_DDI_EDP_INPUT_A_ONOFF:
46 pipe = PIPE_A;
47 break;
48 case TRANS_DDI_EDP_INPUT_B_ONOFF:
49 pipe = PIPE_B;
50 break;
51 case TRANS_DDI_EDP_INPUT_C_ONOFF:
52 pipe = PIPE_C;
53 break;
54 }
55 return pipe;
56 }
57
edp_pipe_is_enabled(struct intel_vgpu * vgpu)58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59 {
60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
61
62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63 return 0;
64
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
66 return 0;
67 return 1;
68 }
69
pipe_is_enabled(struct intel_vgpu * vgpu,int pipe)70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71 {
72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
73
74 if (drm_WARN_ON(&dev_priv->drm,
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES))
76 return -EINVAL;
77
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
79 return 1;
80
81 if (edp_pipe_is_enabled(vgpu) &&
82 get_edp_pipe(vgpu) == pipe)
83 return 1;
84 return 0;
85 }
86
87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
88 {
89 /* EDID with 1024x768 as its resolution */
90 /*Header*/
91 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
92 /* Vendor & Product Identification */
93 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
94 /* Version & Revision */
95 0x01, 0x04,
96 /* Basic Display Parameters & Features */
97 0xa5, 0x34, 0x20, 0x78, 0x23,
98 /* Color Characteristics */
99 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
100 /* Established Timings: maximum resolution is 1024x768 */
101 0x21, 0x08, 0x00,
102 /* Standard Timings. All invalid */
103 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
104 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
105 /* 18 Byte Data Blocks 1: invalid */
106 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
107 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
108 /* 18 Byte Data Blocks 2: invalid */
109 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
110 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
111 /* 18 Byte Data Blocks 3: invalid */
112 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
113 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
114 /* 18 Byte Data Blocks 4: invalid */
115 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
116 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
117 /* Extension Block Count */
118 0x00,
119 /* Checksum */
120 0xef,
121 },
122 {
123 /* EDID with 1920x1200 as its resolution */
124 /*Header*/
125 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
126 /* Vendor & Product Identification */
127 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
128 /* Version & Revision */
129 0x01, 0x04,
130 /* Basic Display Parameters & Features */
131 0xa5, 0x34, 0x20, 0x78, 0x23,
132 /* Color Characteristics */
133 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
134 /* Established Timings: maximum resolution is 1024x768 */
135 0x21, 0x08, 0x00,
136 /*
137 * Standard Timings.
138 * below new resolutions can be supported:
139 * 1920x1080, 1280x720, 1280x960, 1280x1024,
140 * 1440x900, 1600x1200, 1680x1050
141 */
142 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
143 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
144 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
145 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
146 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
147 /* 18 Byte Data Blocks 2: invalid */
148 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
149 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
150 /* 18 Byte Data Blocks 3: invalid */
151 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
152 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
153 /* 18 Byte Data Blocks 4: invalid */
154 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
155 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
156 /* Extension Block Count */
157 0x00,
158 /* Checksum */
159 0x45,
160 },
161 };
162
163 #define DPCD_HEADER_SIZE 0xb
164
165 /* let the virtual display supports DP1.2 */
166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
167 0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
168 };
169
emulate_monitor_status_change(struct intel_vgpu * vgpu)170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
171 {
172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
173 int pipe;
174
175 if (IS_BROXTON(dev_priv)) {
176 enum transcoder trans;
177 enum port port;
178
179 /* Clear PIPE, DDI, PHY, HPD before setting new */
180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
181 ~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
182 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
183 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
184
185 for_each_pipe(dev_priv, pipe) {
186 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
187 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
188 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
189 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
191 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
192 }
193
194 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
195 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
196 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
197 TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
198 }
199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
200 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
201 TRANS_DDI_PORT_MASK);
202
203 for (port = PORT_A; port <= PORT_C; port++) {
204 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
205 ~BXT_PHY_LANE_ENABLED;
206 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
207 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
208 BXT_PHY_LANE_POWERDOWN_ACK);
209
210 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
211 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
212 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
213 PORT_PLL_ENABLE);
214
215 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
216 ~(DDI_INIT_DISPLAY_DETECTED |
217 DDI_BUF_CTL_ENABLE);
218 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
219 }
220 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
221 ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
222 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
223 ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
224 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
225 ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
226 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
227 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
228 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
229
230 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
231 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
232 ~PHY_POWER_GOOD;
233 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
234 ~PHY_POWER_GOOD;
235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
236 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
237
238 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
239 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
240
241 /*
242 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
243 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
244 * TRANSCODER_A can be enabled. PORT_x depends on the input of
245 * setup_virtual_dp_monitor.
246 */
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
248 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
249
250 /*
251 * Golden M/N are calculated based on:
252 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
253 * DP link clk 1620 MHz and non-constant_n.
254 * TODO: calculate DP link symbol clk and stream clk m/n.
255 */
256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
258 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
259 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
260 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
261
262 /* Enable per-DDI/PORT vreg */
263 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
265 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
266 PHY_POWER_GOOD;
267 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
268 BIT(30);
269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
270 BXT_PHY_LANE_ENABLED;
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
272 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
273 BXT_PHY_LANE_POWERDOWN_ACK);
274 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
275 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
276 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
277 PORT_PLL_ENABLE);
278 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
279 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
280 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
281 ~DDI_BUF_IS_IDLE;
282 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
283 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
284 TRANS_DDI_FUNC_ENABLE);
285 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
286 PORTA_HOTPLUG_ENABLE;
287 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
288 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
289 }
290
291 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
292 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
293 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
294 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
295 PHY_POWER_GOOD;
296 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
297 BIT(30);
298 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
299 BXT_PHY_LANE_ENABLED;
300 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
301 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
302 BXT_PHY_LANE_POWERDOWN_ACK);
303 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
304 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
305 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
306 PORT_PLL_ENABLE);
307 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
308 DDI_BUF_CTL_ENABLE;
309 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
310 ~DDI_BUF_IS_IDLE;
311 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
312 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
313 (PORT_B << TRANS_DDI_PORT_SHIFT) |
314 TRANS_DDI_FUNC_ENABLE);
315 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
316 PORTB_HOTPLUG_ENABLE;
317 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
318 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
319 }
320
321 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
322 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
323 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
324 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
325 PHY_POWER_GOOD;
326 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
327 BIT(30);
328 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
329 BXT_PHY_LANE_ENABLED;
330 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
331 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
332 BXT_PHY_LANE_POWERDOWN_ACK);
333 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
334 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
335 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
336 PORT_PLL_ENABLE);
337 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
338 DDI_BUF_CTL_ENABLE;
339 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
340 ~DDI_BUF_IS_IDLE;
341 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
342 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
343 (PORT_B << TRANS_DDI_PORT_SHIFT) |
344 TRANS_DDI_FUNC_ENABLE);
345 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
346 PORTC_HOTPLUG_ENABLE;
347 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
348 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
349 }
350
351 return;
352 }
353
354 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
355 SDE_PORTC_HOTPLUG_CPT |
356 SDE_PORTD_HOTPLUG_CPT);
357
358 if (IS_SKYLAKE(dev_priv) ||
359 IS_KABYLAKE(dev_priv) ||
360 IS_COFFEELAKE(dev_priv) ||
361 IS_COMETLAKE(dev_priv)) {
362 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
363 SDE_PORTE_HOTPLUG_SPT);
364 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
365 SKL_FUSE_DOWNLOAD_STATUS |
366 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
367 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
368 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
369 /*
370 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
371 * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
372 * TRANSCODER_A can be enabled. PORT_x depends on the input of
373 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
374 * so we fixed to DPLL0 here.
375 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
376 */
377 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
378 DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
379 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
380 DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
381 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
382 LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
383 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
384 /*
385 * Golden M/N are calculated based on:
386 * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
387 * DP link clk 1620 MHz and non-constant_n.
388 * TODO: calculate DP link symbol clk and stream clk m/n.
389 */
390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
391 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
392 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
393 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
394 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
395 }
396
397 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
398 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
399 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
400 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
401 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
402 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
403 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
404 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
405 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
406 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
407 TRANS_DDI_PORT_MASK);
408 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
409 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
410 (PORT_B << TRANS_DDI_PORT_SHIFT) |
411 TRANS_DDI_FUNC_ENABLE);
412 if (IS_BROADWELL(dev_priv)) {
413 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
414 ~PORT_CLK_SEL_MASK;
415 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
416 PORT_CLK_SEL_LCPLL_810;
417 }
418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
419 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
420 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
421 }
422
423 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
424 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
425 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
426 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
427 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
428 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
429 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
430 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
431 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
432 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
433 TRANS_DDI_PORT_MASK);
434 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
435 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
436 (PORT_C << TRANS_DDI_PORT_SHIFT) |
437 TRANS_DDI_FUNC_ENABLE);
438 if (IS_BROADWELL(dev_priv)) {
439 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
440 ~PORT_CLK_SEL_MASK;
441 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
442 PORT_CLK_SEL_LCPLL_810;
443 }
444 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
445 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
446 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
447 }
448
449 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
450 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
451 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
452 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
453 DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
454 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
455 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
456 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
457 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
458 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
459 TRANS_DDI_PORT_MASK);
460 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
461 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
462 (PORT_D << TRANS_DDI_PORT_SHIFT) |
463 TRANS_DDI_FUNC_ENABLE);
464 if (IS_BROADWELL(dev_priv)) {
465 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
466 ~PORT_CLK_SEL_MASK;
467 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
468 PORT_CLK_SEL_LCPLL_810;
469 }
470 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
471 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
472 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
473 }
474
475 if ((IS_SKYLAKE(dev_priv) ||
476 IS_KABYLAKE(dev_priv) ||
477 IS_COFFEELAKE(dev_priv) ||
478 IS_COMETLAKE(dev_priv)) &&
479 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
480 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
481 }
482
483 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
484 if (IS_BROADWELL(dev_priv))
485 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
486 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
487 else
488 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
489
490 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
491 }
492
493 /* Clear host CRT status, so guest couldn't detect this host CRT. */
494 if (IS_BROADWELL(dev_priv))
495 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
496
497 /* Disable Primary/Sprite/Cursor plane */
498 for_each_pipe(dev_priv, pipe) {
499 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
500 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
501 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
502 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
503 }
504
505 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
506 }
507
clean_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num)508 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
509 {
510 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
511
512 kfree(port->edid);
513 port->edid = NULL;
514
515 kfree(port->dpcd);
516 port->dpcd = NULL;
517 }
518
vblank_timer_fn(struct hrtimer * data)519 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
520 {
521 struct intel_vgpu_vblank_timer *vblank_timer;
522 struct intel_vgpu *vgpu;
523
524 vblank_timer = container_of(data, struct intel_vgpu_vblank_timer, timer);
525 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
526
527 /* Set vblank emulation request per-vGPU bit */
528 intel_gvt_request_service(vgpu->gvt,
529 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
530 hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
531 return HRTIMER_RESTART;
532 }
533
setup_virtual_dp_monitor(struct intel_vgpu * vgpu,int port_num,int type,unsigned int resolution)534 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
535 int type, unsigned int resolution)
536 {
537 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
538 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
539 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
540
541 if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
542 return -EINVAL;
543
544 port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
545 if (!port->edid)
546 return -ENOMEM;
547
548 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
549 if (!port->dpcd) {
550 kfree(port->edid);
551 return -ENOMEM;
552 }
553
554 memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
555 EDID_SIZE);
556 port->edid->data_valid = true;
557
558 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
559 port->dpcd->data_valid = true;
560 port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
561 port->type = type;
562 port->id = resolution;
563 port->vrefresh_k = GVT_DEFAULT_REFRESH_RATE * MSEC_PER_SEC;
564 vgpu->display.port_num = port_num;
565
566 /* Init hrtimer based on default refresh rate */
567 hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
568 vblank_timer->timer.function = vblank_timer_fn;
569 vblank_timer->vrefresh_k = port->vrefresh_k;
570 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
571
572 emulate_monitor_status_change(vgpu);
573
574 return 0;
575 }
576
577 /**
578 * vgpu_update_vblank_emulation - Update per-vGPU vblank_timer
579 * @vgpu: vGPU operated
580 * @turnon: Turn ON/OFF vblank_timer
581 *
582 * This function is used to turn on/off or update the per-vGPU vblank_timer
583 * when PIPECONF is enabled or disabled. vblank_timer period is also updated
584 * if guest changed the refresh rate.
585 *
586 */
vgpu_update_vblank_emulation(struct intel_vgpu * vgpu,bool turnon)587 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
588 {
589 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
590 struct intel_vgpu_port *port =
591 intel_vgpu_port(vgpu, vgpu->display.port_num);
592
593 if (turnon) {
594 /*
595 * Skip the re-enable if already active and vrefresh unchanged.
596 * Otherwise, stop timer if already active and restart with new
597 * period.
598 */
599 if (vblank_timer->vrefresh_k != port->vrefresh_k ||
600 !hrtimer_active(&vblank_timer->timer)) {
601 /* Stop timer before start with new period if active */
602 if (hrtimer_active(&vblank_timer->timer))
603 hrtimer_cancel(&vblank_timer->timer);
604
605 /* Make sure new refresh rate updated to timer period */
606 vblank_timer->vrefresh_k = port->vrefresh_k;
607 vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k);
608 hrtimer_start(&vblank_timer->timer,
609 ktime_add_ns(ktime_get(), vblank_timer->period),
610 HRTIMER_MODE_ABS);
611 }
612 } else {
613 /* Caller request to stop vblank */
614 hrtimer_cancel(&vblank_timer->timer);
615 }
616 }
617
emulate_vblank_on_pipe(struct intel_vgpu * vgpu,int pipe)618 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
619 {
620 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
621 struct intel_vgpu_irq *irq = &vgpu->irq;
622 int vblank_event[] = {
623 [PIPE_A] = PIPE_A_VBLANK,
624 [PIPE_B] = PIPE_B_VBLANK,
625 [PIPE_C] = PIPE_C_VBLANK,
626 };
627 int event;
628
629 if (pipe < PIPE_A || pipe > PIPE_C)
630 return;
631
632 for_each_set_bit(event, irq->flip_done_event[pipe],
633 INTEL_GVT_EVENT_MAX) {
634 clear_bit(event, irq->flip_done_event[pipe]);
635 if (!pipe_is_enabled(vgpu, pipe))
636 continue;
637
638 intel_vgpu_trigger_virtual_event(vgpu, event);
639 }
640
641 if (pipe_is_enabled(vgpu, pipe)) {
642 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
643 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
644 }
645 }
646
intel_vgpu_emulate_vblank(struct intel_vgpu * vgpu)647 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
648 {
649 int pipe;
650
651 mutex_lock(&vgpu->vgpu_lock);
652 for_each_pipe(vgpu->gvt->gt->i915, pipe)
653 emulate_vblank_on_pipe(vgpu, pipe);
654 mutex_unlock(&vgpu->vgpu_lock);
655 }
656
657 /**
658 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
659 * @vgpu: a vGPU
660 * @connected: link state
661 *
662 * This function is used to trigger hotplug interrupt for vGPU
663 *
664 */
intel_vgpu_emulate_hotplug(struct intel_vgpu * vgpu,bool connected)665 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
666 {
667 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
668
669 /* TODO: add more platforms support */
670 if (IS_SKYLAKE(i915) ||
671 IS_KABYLAKE(i915) ||
672 IS_COFFEELAKE(i915) ||
673 IS_COMETLAKE(i915)) {
674 if (connected) {
675 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
676 SFUSE_STRAP_DDID_DETECTED;
677 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
678 } else {
679 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
680 ~SFUSE_STRAP_DDID_DETECTED;
681 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
682 }
683 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
684 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
685 PORTD_HOTPLUG_STATUS_MASK;
686 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
687 } else if (IS_BROXTON(i915)) {
688 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
689 if (connected) {
690 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
691 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
692 } else {
693 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
694 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
695 }
696 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
697 GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
698 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
699 ~PORTA_HOTPLUG_STATUS_MASK;
700 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
701 PORTA_HOTPLUG_LONG_DETECT;
702 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
703 }
704 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
705 if (connected) {
706 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
707 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
708 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
709 SFUSE_STRAP_DDIB_DETECTED;
710 } else {
711 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
712 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
713 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
714 ~SFUSE_STRAP_DDIB_DETECTED;
715 }
716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
717 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
718 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
719 ~PORTB_HOTPLUG_STATUS_MASK;
720 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
721 PORTB_HOTPLUG_LONG_DETECT;
722 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
723 }
724 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
725 if (connected) {
726 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
727 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
728 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
729 SFUSE_STRAP_DDIC_DETECTED;
730 } else {
731 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
732 ~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
733 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
734 ~SFUSE_STRAP_DDIC_DETECTED;
735 }
736 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
737 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
738 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
739 ~PORTC_HOTPLUG_STATUS_MASK;
740 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
741 PORTC_HOTPLUG_LONG_DETECT;
742 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
743 }
744 }
745 }
746
747 /**
748 * intel_vgpu_clean_display - clean vGPU virtual display emulation
749 * @vgpu: a vGPU
750 *
751 * This function is used to clean vGPU virtual display emulation stuffs
752 *
753 */
intel_vgpu_clean_display(struct intel_vgpu * vgpu)754 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
755 {
756 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
757
758 if (IS_SKYLAKE(dev_priv) ||
759 IS_KABYLAKE(dev_priv) ||
760 IS_COFFEELAKE(dev_priv) ||
761 IS_COMETLAKE(dev_priv))
762 clean_virtual_dp_monitor(vgpu, PORT_D);
763 else
764 clean_virtual_dp_monitor(vgpu, PORT_B);
765
766 vgpu_update_vblank_emulation(vgpu, false);
767 }
768
769 /**
770 * intel_vgpu_init_display- initialize vGPU virtual display emulation
771 * @vgpu: a vGPU
772 * @resolution: resolution index for intel_vgpu_edid
773 *
774 * This function is used to initialize vGPU virtual display emulation stuffs
775 *
776 * Returns:
777 * Zero on success, negative error code if failed.
778 *
779 */
intel_vgpu_init_display(struct intel_vgpu * vgpu,u64 resolution)780 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
781 {
782 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
783
784 intel_vgpu_init_i2c_edid(vgpu);
785
786 if (IS_SKYLAKE(dev_priv) ||
787 IS_KABYLAKE(dev_priv) ||
788 IS_COFFEELAKE(dev_priv) ||
789 IS_COMETLAKE(dev_priv))
790 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
791 resolution);
792 else
793 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
794 resolution);
795 }
796
797 /**
798 * intel_vgpu_reset_display- reset vGPU virtual display emulation
799 * @vgpu: a vGPU
800 *
801 * This function is used to reset vGPU virtual display emulation stuffs
802 *
803 */
intel_vgpu_reset_display(struct intel_vgpu * vgpu)804 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
805 {
806 emulate_monitor_status_change(vgpu);
807 }
808