/drivers/char/mwave/ |
D | mwavedd.h | 79 #define PRINTK_2(f,s,v1) \ argument 84 #define PRINTK_3(f,s,v1,v2) \ argument 89 #define PRINTK_4(f,s,v1,v2,v3) \ argument 94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument 99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument 104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument 109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument 116 #define PRINTK_2(f,s,v1) argument 117 #define PRINTK_3(f,s,v1,v2) argument 118 #define PRINTK_4(f,s,v1,v2,v3) argument [all …]
|
/drivers/gpu/drm/amd/display/dc/inc/ |
D | reg_helper.h | 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument 78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument 85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument 94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument 104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument 115 #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument 127 #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ argument 140 #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ argument 160 #define REG_GET_2(reg_name, f1, v1, f2, v2) \ argument [all …]
|
D | bw_fixed.h | 54 static inline struct bw_fixed bw_min3(struct bw_fixed v1, in bw_min3() 61 static inline struct bw_fixed bw_max3(struct bw_fixed v1, in bw_max3()
|
/drivers/gpu/drm/amd/display/dmub/src/ |
D | dmub_reg.h | 65 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument 70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument 76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument 92 #define REG_UPDATE_2(reg, f1, v1, f2, v2) \ argument 97 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ argument 103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
|
/drivers/staging/r8188eu/hal/ |
D | HalHWImg8188E_BB.c | 7 #define read_next_pair(array, v1, v2, i) \ argument 205 u32 v1 = array[i]; in ODM_ReadAndConfig_AGC_TAB_1T_8188E() local 484 u32 v1 = array[i]; in ODM_ReadAndConfig_PHY_REG_1T_8188E() local 678 u32 v1 = array[i]; in ODM_ReadAndConfig_PHY_REG_PG_8188E() local
|
D | HalHWImg8188E_RF.c | 141 #define READ_NEXT_PAIR(v1, v2, i) do \ in ODM_ReadAndConfig_RadioA_1T_8188E() argument 173 u32 v1 = Array[i]; in ODM_ReadAndConfig_RadioA_1T_8188E() local
|
D | HalHWImg8188E_MAC.c | 132 #define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0) in ODM_ReadAndConfig_MAC_REG_8188E() argument 163 u32 v1 = array[i]; in ODM_ReadAndConfig_MAC_REG_8188E() local
|
/drivers/staging/rtl8723bs/hal/ |
D | HalHWImg8723B_BB.c | 226 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_AGC_TAB() local 488 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG() local 563 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_PHY_REG_PG() local
|
D | HalHWImg8723B_MAC.c | 196 u32 v1 = Array[i]; in ODM_ReadAndConfig_MP_8723B_MAC_REG() local
|
D | odm_types.h | 47 #define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Arra… argument
|
/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/ |
D | ia_css_xnr3_types.h | 55 int v1; /** Sigma for V range similarity in bright area */ member 70 int v1; /** Coring threshold of V channel in bright area */ member
|
/drivers/gpu/drm/amd/display/dc/calcs/ |
D | dcn_calc_math.c | 96 float dcn_bw_max3(float v1, float v2, float v3) in dcn_bw_max3() 101 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5()
|
/drivers/video/fbdev/ |
D | atafb_iplan2p4.c | 106 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local 155 u32 pval[4], v, v1, mask; in atafb_iplan2p4_copyarea() local
|
D | atafb_iplan2p2.c | 106 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local 148 u32 pval[4], v, v1, mask; in atafb_iplan2p2_copyarea() local
|
D | atafb_iplan2p8.c | 113 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local 176 u32 pval[4], v, v1, mask; in atafb_iplan2p8_copyarea() local
|
/drivers/net/ethernet/toshiba/ |
D | ps3_gelic_net.c | 107 u64 v1, v2; in gelic_card_set_link_mode() local 1303 u64 v1, v2; in gelic_net_set_wol() local 1465 u64 v1, v2; in gelic_net_setup_netdev() local 1571 u64 v1, v2; in gelic_card_get_vlan_info() local
|
/drivers/gpu/drm/amd/amdgpu/ |
D | atombios_crtc.c | 236 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; member 301 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; member 460 PIXEL_CLOCK_PARAMETERS v1; member
|
D | atombios_encoders.c | 555 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; member 743 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; member 1209 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; member 1451 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; member
|
D | amdgpu_atombios.c | 875 struct _ATOM_ASIC_SS_ASSIGNMENT v1; member 987 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; member 1184 struct _SET_VOLTAGE_PARAMETERS v1; member 1236 struct _ATOM_VOLTAGE_OBJECT_INFO v1; member 1242 struct _ATOM_VOLTAGE_OBJECT v1; member
|
/drivers/net/ieee802154/ |
D | mac802154_hwsim.c | 419 u32 v0, v1; in hwsim_new_edge_nl() local 481 u32 v0, v1; in hwsim_del_edge_nl() local 528 u32 v0, v1; in hwsim_set_edge_lqi() local
|
/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/ |
D | phy.c | 382 #define READ_NEXT_PAIR(v1, v2, i) \ argument 391 u32 v1; in handle_branch1() local 435 u32 v1; in handle_branch2() local 638 u32 v1 = 0, v2 = 0; in phy_config_bb_with_pghdr() local 693 #define READ_NEXT_RF_PAIR(v1, v2, i) \ argument 705 u32 v1, v2; in process_path_a() local
|
/drivers/char/ |
D | sonypi.c | 637 u8 v1, v2; in sonypi_call1() local 648 u8 v1; in sonypi_call2() local 660 u8 v1; in sonypi_call3() local 826 u8 v1, v2, event = 0; in sonypi_irq() local
|
/drivers/gpu/drm/radeon/ |
D | atombios_encoders.c | 558 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; member 837 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; member 1006 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; member 1431 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; member 1857 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; member
|
/drivers/gpu/drm/msm/edp/ |
D | edp_phy.c | 62 void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1) in msm_edp_phy_vm_pe_cfg()
|
/drivers/net/wireless/ath/ath9k/ |
D | rng.c | 32 u32 v1, v2, rng_last = sc->rng_last; in ath9k_rng_data_read() local
|