| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) argument
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| /drivers/gpu/drm/msm/adreno/ |
| D | adreno_pm4.xml.h | 486 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF()
492 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC()
498 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK()
504 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT()
512 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE()
518 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR()
526 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) in CP_LOAD_STATE4_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) in CP_LOAD_STATE4_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) in CP_LOAD_STATE4_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE4_0_NUM_UNIT()
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| D | a6xx.xml.h | 1024 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_LO()
1030 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_RB_HI()
1036 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1042 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1050 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1056 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1080 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A6XX_CP_PROTECT_REG_BASE_ADDR()
1086 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A6XX_CP_PROTECT_REG_MASK_LEN()
1175 static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) in A6XX_CP_CSQ_IB1_STAT_REM()
1183 static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) in A6XX_CP_CSQ_IB2_STAT_REM()
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| D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE()
985 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) in A3XX_GRAS_CL_VPORT_YOFFSET()
993 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) in A3XX_GRAS_CL_VPORT_YSCALE()
1001 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) in A3XX_GRAS_CL_VPORT_ZOFFSET()
1009 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) in A3XX_GRAS_CL_VPORT_ZSCALE()
1017 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) in A3XX_GRAS_SU_POINT_MINMAX_MIN()
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| D | adreno_common.xml.h | 213 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) in AXXX_CP_RB_CNTL_BUFSZ()
219 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) in AXXX_CP_RB_CNTL_BLKSZ()
225 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) in AXXX_CP_RB_CNTL_BUF_SWAP()
236 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_SWAP()
242 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_ADDR()
260 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()
266 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()
272 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()
280 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()
286 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()
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| D | a4xx.xml.h | 844 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC()
901 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
907 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
923 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH()
929 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT()
943 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) in A4XX_RB_MSAA_CONTROL_SAMPLES()
951 static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) in A4XX_RB_RENDER_CONTROL2_COORD_MASK()
960 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
979 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) in A4XX_RB_MRT_CONTROL_ROP_CODE()
985 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) in A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
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| D | a5xx.xml.h | 1042 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR()
1048 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN()
1054 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1060 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ()
1837 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
1843 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP()
1849 static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val) in A5XX_RBBM_STATUS_HLSQ_BUSY()
1855 static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val) in A5XX_RBBM_STATUS_VSC_BUSY()
1861 static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val) in A5XX_RBBM_STATUS_TPL1_BUSY()
1867 static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val) in A5XX_RBBM_STATUS_SP_BUSY()
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| D | a2xx.xml.h | 1166 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
1172 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
1196 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR()
1202 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR()
1208 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR()
1214 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR()
1220 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR()
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| /drivers/gpu/drm/panel/ |
| D | panel-abt-y030xx067a.c | 22 #define REG00_VBRT_CTRL(val) (val) argument
24 #define REG01_COM_DC(val) (val) argument
26 #define REG02_DA_CONTRAST(val) (val) argument
27 #define REG02_VESA_SEL(val) ((val) << 5) argument
30 #define REG03_VPOSITION(val) (val) argument
35 #define REG04_HPOSITION1(val) (val) argument
40 #define REG05_SLBRCHARGE(val) ((val) << 3) argument
41 #define REG05_PRECHARGE_LEVEL(val) ((val) << 6) argument
48 #define REG06_GAMMA_SEL(val) ((val) << 5) argument
57 #define REG07_AMPTST(val) ((val) << 6) argument
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5.xml.h | 192 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
198 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
204 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
219 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
225 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
231 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
239 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
245 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
251 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
257 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4.xml.h | 121 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
127 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
149 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
155 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
161 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
191 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
198 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
205 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
212 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
219 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 147 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR()
153 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR()
159 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP()
214 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL()
220 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT()
226 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE()
243 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP()
251 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START()
257 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END()
265 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START()
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| /drivers/hwtracing/coresight/ |
| D | coresight-etm4x-sysfs.c | 61 unsigned long val; in nr_pe_cmp_show() local
73 unsigned long val; in nr_addr_cmp_show() local
85 unsigned long val; in nr_cntr_show() local
97 unsigned long val; in nr_ext_inp_show() local
109 unsigned long val; in numcidc_show() local
121 unsigned long val; in numvmidc_show() local
133 unsigned long val; in nrseqstate_show() local
145 unsigned long val; in nr_resource_show() local
157 unsigned long val; in nr_ss_cmp_show() local
170 unsigned long val; in reset_store() local
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| D | coresight-etm3x-sysfs.c | 16 unsigned long val; in nr_addr_cmp_show() local
26 { unsigned long val; in nr_cntr_show() local
37 unsigned long val; in nr_ctxid_cmp_show() local
48 unsigned long flags, val; in etmsr_show() local
70 unsigned long val; in reset_store() local
98 unsigned long val; in mode_show() local
111 unsigned long val; in mode_store() local
183 unsigned long val; in trigger_event_show() local
196 unsigned long val; in trigger_event_store() local
213 unsigned long val; in enable_event_show() local
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip()
95 __be32 val, __be32 mask) in cxgb4_fill_ipv4_dst_ip()
114 __be32 val, __be32 mask) in cxgb4_fill_ipv6_tos()
123 __be32 val, __be32 mask) in cxgb4_fill_ipv6_proto()
132 __be32 val, __be32 mask) in cxgb4_fill_ipv6_src_ip0()
141 __be32 val, __be32 mask) in cxgb4_fill_ipv6_src_ip1()
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| /drivers/gpu/drm/i915/ |
| D | intel_dram.c | 47 static int skl_get_dimm_size(u16 val) in skl_get_dimm_size()
52 static int skl_get_dimm_width(u16 val) in skl_get_dimm_width()
69 static int skl_get_dimm_ranks(u16 val) in skl_get_dimm_ranks()
80 static int icl_get_dimm_size(u16 val) in icl_get_dimm_size()
85 static int icl_get_dimm_width(u16 val) in icl_get_dimm_width()
102 static int icl_get_dimm_ranks(u16 val) in icl_get_dimm_ranks()
122 int channel, char dimm_name, u16 val) in skl_dram_get_dimm_info()
143 int channel, u32 val) in skl_dram_get_channel_info()
185 u32 val; in skl_dram_get_channels_info() local
223 u32 val; in skl_get_dram_type() local
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| D | intel_sideband.c | 95 u32 addr, u32 *val) in vlv_sideband_rw()
145 u32 val = 0; in vlv_punit_read() local
153 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val) in vlv_punit_write()
161 u32 val = 0; in vlv_bunit_read() local
169 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_bunit_write()
177 u32 val = 0; in vlv_nc_read() local
187 u32 val = 0; in vlv_iosf_sb_read() local
196 u8 port, u32 reg, u32 val) in vlv_iosf_sb_write()
204 u32 val = 0; in vlv_cck_read() local
212 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_cck_write()
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| D | i915_fixed.h | 15 u32 val; member
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16()
60 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val) in clamp_u64_to_fixed16()
69 static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val, in div_round_up_fixed16()
75 static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_round_up_u32_fixed16()
86 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, in mul_fixed16()
97 static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d) in div_fixed16()
107 static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d) in div_round_up_u32_fixed16()
118 static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul) in mul_u32_fixed16()
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| /drivers/dma/ti/ |
| D | k3-udma.h | 41 #define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff) argument
42 #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) argument
43 #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) argument
44 #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) argument
45 #define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff) argument
46 #define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff) argument
48 #define BCDMA_CAP2_BCHAN_CNT(val) ((val) & 0x1ff) argument
49 #define BCDMA_CAP2_TCHAN_CNT(val) (((val) >> 9) & 0x1ff) argument
50 #define BCDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) argument
51 #define BCDMA_CAP3_HBCHAN_CNT(val) (((val) >> 14) & 0x1ff) argument
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| /drivers/staging/wfx/ |
| D | hwio.c | 29 static int read32(struct wfx_dev *wdev, int reg, u32 *val) in read32()
48 static int write32(struct wfx_dev *wdev, int reg, u32 val) in write32()
65 static int read32_locked(struct wfx_dev *wdev, int reg, u32 *val) in read32_locked()
76 static int write32_locked(struct wfx_dev *wdev, int reg, u32 val) in write32_locked()
87 static int write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val) in write32_bits_locked()
199 u32 addr, u32 *val) in indirect_read32_locked()
216 u32 addr, u32 val) in indirect_write32_locked()
284 int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val) in sram_reg_read()
289 int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val) in ahb_reg_read()
294 int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val) in sram_reg_write()
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| /drivers/media/pci/cx18/ |
| D | cx18-io.h | 30 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel_noretry()
35 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel()
52 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel_noretry()
57 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel()
68 void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, in cx18_writel_expect()
90 void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew_noretry()
95 static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew()
111 void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb_noretry()
116 static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb()
137 static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) in cx18_write_reg_noretry()
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| /drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | debugfs.c | 6 mt7615_reg_set(void *data, u64 val) in mt7615_reg_set()
18 mt7615_reg_get(void *data, u64 *val) in mt7615_reg_get()
33 mt7615_radar_pattern_set(void *data, u64 val) in mt7615_radar_pattern_set()
51 static int mt7615_config(void *data, u64 val) in mt7615_config()
66 mt7615_scs_set(void *data, u64 val) in mt7615_scs_set()
83 mt7615_scs_get(void *data, u64 *val) in mt7615_scs_get()
96 mt7615_pm_set(void *data, u64 val) in mt7615_pm_set()
130 mt7615_pm_get(void *data, u64 *val) in mt7615_pm_get()
162 mt7615_pm_idle_timeout_set(void *data, u64 val) in mt7615_pm_idle_timeout_set()
172 mt7615_pm_idle_timeout_get(void *data, u64 *val) in mt7615_pm_idle_timeout_get()
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| /drivers/pci/controller/dwc/ |
| D | pcie-designware.c | 107 int dw_pcie_read(void __iomem *addr, int size, u32 *val) in dw_pcie_read()
129 int dw_pcie_write(void __iomem *addr, int size, u32 val) in dw_pcie_write()
150 u32 val; in dw_pcie_read_dbi() local
163 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi()
178 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi2()
195 u32 val; in dw_pcie_readl_atu() local
207 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) in dw_pcie_writel_atu()
229 u32 val) in dw_pcie_writel_ob_unroll()
236 static inline u32 dw_pcie_enable_ecrc(u32 val) in dw_pcie_enable_ecrc()
282 u32 retries, val; in dw_pcie_prog_outbound_atu_unroll() local
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| /drivers/media/dvb-frontends/ |
| D | lg2160.c | 53 static int lg216x_write_reg(struct lg216x_state *state, u16 reg, u8 val) in lg216x_write_reg()
77 static int lg216x_read_reg(struct lg216x_state *state, u16 reg, u8 *val) in lg216x_read_reg()
105 u8 val; member
126 u8 val; in lg216x_set_reg_bit() local
238 u8 val; in lg216x_set_if() local
263 u8 val; in lg2160_agc_fix() local
305 u8 val; in lg2160_agc_polarity() local
325 u8 val; in lg2160_tuner_pwr_save_polarity() local
344 u8 val; in lg2160_spectrum_polarity() local
362 u8 val; in lg2160_tuner_pwr_save() local
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