1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8 #ifndef __ASM_PROCESSOR_H
9 #define __ASM_PROCESSOR_H
10
11 /*
12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
13 * no point in shifting all network buffers by 2 bytes just to make some IP
14 * header fields appear aligned in memory, potentially sacrificing some DMA
15 * performance on some platforms.
16 */
17 #define NET_IP_ALIGN 0
18
19 #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20 #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21
22 #define MTE_CTRL_TCF_SYNC (1UL << 16)
23 #define MTE_CTRL_TCF_ASYNC (1UL << 17)
24 #define MTE_CTRL_TCF_ASYMM (1UL << 18)
25
26 #ifndef __ASSEMBLY__
27
28 #include <linux/build_bug.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/stddef.h>
32 #include <linux/string.h>
33 #include <linux/thread_info.h>
34 #include <linux/android_vendor.h>
35
36 #include <vdso/processor.h>
37
38 #include <asm/alternative.h>
39 #include <asm/cpufeature.h>
40 #include <asm/hw_breakpoint.h>
41 #include <asm/kasan.h>
42 #include <asm/lse.h>
43 #include <asm/pgtable-hwdef.h>
44 #include <asm/pointer_auth.h>
45 #include <asm/ptrace.h>
46 #include <asm/spectre.h>
47 #include <asm/types.h>
48
49 /*
50 * TASK_SIZE - the maximum size of a user space task.
51 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
52 */
53
54 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
55 #define TASK_SIZE_64 (UL(1) << vabits_actual)
56 #define TASK_SIZE_MAX (UL(1) << VA_BITS)
57
58 #ifdef CONFIG_COMPAT
59 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
60 /*
61 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
62 * by the compat vectors page.
63 */
64 #define TASK_SIZE_32 UL(0x100000000)
65 #else
66 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
67 #endif /* CONFIG_ARM64_64K_PAGES */
68 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
69 TASK_SIZE_32 : TASK_SIZE_64)
70 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
71 TASK_SIZE_32 : TASK_SIZE_64)
72 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
73 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
74 #else
75 #define TASK_SIZE TASK_SIZE_64
76 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
77 #endif /* CONFIG_COMPAT */
78
79 #ifdef CONFIG_ARM64_FORCE_52BIT
80 #define STACK_TOP_MAX TASK_SIZE_64
81 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
82 #else
83 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
84 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
85 #endif /* CONFIG_ARM64_FORCE_52BIT */
86
87 #ifdef CONFIG_COMPAT
88 #define AARCH32_VECTORS_BASE 0xffff0000
89 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
90 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
91 #else
92 #define STACK_TOP STACK_TOP_MAX
93 #endif /* CONFIG_COMPAT */
94
95 #ifndef CONFIG_ARM64_FORCE_52BIT
96 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
97 DEFAULT_MAP_WINDOW)
98
99 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
100 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
101 base)
102 #endif /* CONFIG_ARM64_FORCE_52BIT */
103
104 extern phys_addr_t arm64_dma_phys_limit;
105 #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
106
107 struct debug_info {
108 #ifdef CONFIG_HAVE_HW_BREAKPOINT
109 /* Have we suspended stepping by a debugger? */
110 int suspended_step;
111 /* Allow breakpoints and watchpoints to be disabled for this thread. */
112 int bps_disabled;
113 int wps_disabled;
114 /* Hardware breakpoints pinned to this task. */
115 struct perf_event *hbp_break[ARM_MAX_BRP];
116 struct perf_event *hbp_watch[ARM_MAX_WRP];
117 #endif
118 };
119
120 enum vec_type {
121 ARM64_VEC_SVE = 0,
122 ARM64_VEC_SME,
123 ARM64_VEC_MAX,
124 };
125
126 struct cpu_context {
127 unsigned long x19;
128 unsigned long x20;
129 unsigned long x21;
130 unsigned long x22;
131 unsigned long x23;
132 unsigned long x24;
133 unsigned long x25;
134 unsigned long x26;
135 unsigned long x27;
136 unsigned long x28;
137 unsigned long fp;
138 unsigned long sp;
139 unsigned long pc;
140 };
141
142 struct thread_struct {
143 struct cpu_context cpu_context; /* cpu context */
144
145 /*
146 * Whitelisted fields for hardened usercopy:
147 * Maintainers must ensure manually that this contains no
148 * implicit padding.
149 */
150 struct {
151 unsigned long tp_value; /* TLS register */
152 unsigned long tp2_value;
153 struct user_fpsimd_state fpsimd_state;
154 } uw;
155
156 ANDROID_VENDOR_DATA(1);
157
158 unsigned int fpsimd_cpu;
159 void *sve_state; /* SVE registers, if any */
160 void *za_state; /* ZA register, if any */
161 unsigned int vl[ARM64_VEC_MAX]; /* vector length */
162 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */
163 unsigned long fault_address; /* fault info */
164 unsigned long fault_code; /* ESR_EL1 value */
165 struct debug_info debug; /* debugging */
166 #ifdef CONFIG_ARM64_PTR_AUTH
167 struct ptrauth_keys_user keys_user;
168 #ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
169 struct ptrauth_keys_kernel keys_kernel;
170 #endif
171 #endif
172 #ifdef CONFIG_ARM64_MTE
173 u64 mte_ctrl;
174 #endif
175 u64 sctlr_user;
176 u64 svcr;
177 u64 tpidr2_el0;
178 };
179
thread_get_vl(struct thread_struct * thread,enum vec_type type)180 static inline unsigned int thread_get_vl(struct thread_struct *thread,
181 enum vec_type type)
182 {
183 return thread->vl[type];
184 }
185
thread_get_sve_vl(struct thread_struct * thread)186 static inline unsigned int thread_get_sve_vl(struct thread_struct *thread)
187 {
188 return thread_get_vl(thread, ARM64_VEC_SVE);
189 }
190
thread_get_sme_vl(struct thread_struct * thread)191 static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
192 {
193 return thread_get_vl(thread, ARM64_VEC_SME);
194 }
195
thread_get_cur_vl(struct thread_struct * thread)196 static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
197 {
198 if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
199 return thread_get_sme_vl(thread);
200 else
201 return thread_get_sve_vl(thread);
202 }
203
204 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type);
205 void task_set_vl(struct task_struct *task, enum vec_type type,
206 unsigned long vl);
207 void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
208 unsigned long vl);
209 unsigned int task_get_vl_onexec(const struct task_struct *task,
210 enum vec_type type);
211
task_get_sve_vl(const struct task_struct * task)212 static inline unsigned int task_get_sve_vl(const struct task_struct *task)
213 {
214 return task_get_vl(task, ARM64_VEC_SVE);
215 }
216
task_get_sme_vl(const struct task_struct * task)217 static inline unsigned int task_get_sme_vl(const struct task_struct *task)
218 {
219 return task_get_vl(task, ARM64_VEC_SME);
220 }
221
task_set_sve_vl(struct task_struct * task,unsigned long vl)222 static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl)
223 {
224 task_set_vl(task, ARM64_VEC_SVE, vl);
225 }
226
task_get_sve_vl_onexec(const struct task_struct * task)227 static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task)
228 {
229 return task_get_vl_onexec(task, ARM64_VEC_SVE);
230 }
231
task_set_sve_vl_onexec(struct task_struct * task,unsigned long vl)232 static inline void task_set_sve_vl_onexec(struct task_struct *task,
233 unsigned long vl)
234 {
235 task_set_vl_onexec(task, ARM64_VEC_SVE, vl);
236 }
237
238 #define SCTLR_USER_MASK \
239 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
240 SCTLR_EL1_TCF0_MASK)
241
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)242 static inline void arch_thread_struct_whitelist(unsigned long *offset,
243 unsigned long *size)
244 {
245 /* Verify that there is no padding among the whitelisted fields: */
246 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
247 sizeof_field(struct thread_struct, uw.tp_value) +
248 sizeof_field(struct thread_struct, uw.tp2_value) +
249 sizeof_field(struct thread_struct, uw.fpsimd_state));
250
251 *offset = offsetof(struct thread_struct, uw);
252 *size = sizeof_field(struct thread_struct, uw);
253 }
254
255 #ifdef CONFIG_COMPAT
256 #define task_user_tls(t) \
257 ({ \
258 unsigned long *__tls; \
259 if (is_compat_thread(task_thread_info(t))) \
260 __tls = &(t)->thread.uw.tp2_value; \
261 else \
262 __tls = &(t)->thread.uw.tp_value; \
263 __tls; \
264 })
265 #else
266 #define task_user_tls(t) (&(t)->thread.uw.tp_value)
267 #endif
268
269 /* Sync TPIDR_EL0 back to thread_struct for current */
270 void tls_preserve_current_state(void);
271
272 #define INIT_THREAD { \
273 .fpsimd_cpu = NR_CPUS, \
274 }
275
start_thread_common(struct pt_regs * regs,unsigned long pc)276 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
277 {
278 s32 previous_syscall = regs->syscallno;
279 memset(regs, 0, sizeof(*regs));
280 regs->syscallno = previous_syscall;
281 regs->pc = pc;
282
283 if (system_uses_irq_prio_masking())
284 regs->pmr_save = GIC_PRIO_IRQON;
285 }
286
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)287 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
288 unsigned long sp)
289 {
290 start_thread_common(regs, pc);
291 regs->pstate = PSR_MODE_EL0t;
292 spectre_v4_enable_task_mitigation(current);
293 regs->sp = sp;
294 }
295
296 #ifdef CONFIG_COMPAT
compat_start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)297 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
298 unsigned long sp)
299 {
300 start_thread_common(regs, pc);
301 regs->pstate = PSR_AA32_MODE_USR;
302 if (pc & 1)
303 regs->pstate |= PSR_AA32_T_BIT;
304
305 #ifdef __AARCH64EB__
306 regs->pstate |= PSR_AA32_E_BIT;
307 #endif
308
309 spectre_v4_enable_task_mitigation(current);
310 regs->compat_sp = sp;
311 }
312 #endif
313
is_ttbr0_addr(unsigned long addr)314 static __always_inline bool is_ttbr0_addr(unsigned long addr)
315 {
316 /* entry assembly clears tags for TTBR0 addrs */
317 return addr < TASK_SIZE;
318 }
319
is_ttbr1_addr(unsigned long addr)320 static __always_inline bool is_ttbr1_addr(unsigned long addr)
321 {
322 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
323 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
324 }
325
326 /* Forward declaration, a strange C thing */
327 struct task_struct;
328
329 /* Free all resources held by a thread. */
330 extern void release_thread(struct task_struct *);
331
332 unsigned long get_wchan(struct task_struct *p);
333
334 void update_sctlr_el1(u64 sctlr);
335
336 /* Thread switching */
337 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
338 struct task_struct *next);
339
340 #define task_pt_regs(p) \
341 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
342
343 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
344 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
345
346 /*
347 * Prefetching support
348 */
349 #define ARCH_HAS_PREFETCH
prefetch(const void * ptr)350 static inline void prefetch(const void *ptr)
351 {
352 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
353 }
354
355 #define ARCH_HAS_PREFETCHW
prefetchw(const void * ptr)356 static inline void prefetchw(const void *ptr)
357 {
358 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
359 }
360
361 #define ARCH_HAS_SPINLOCK_PREFETCH
spin_lock_prefetch(const void * ptr)362 static inline void spin_lock_prefetch(const void *ptr)
363 {
364 asm volatile(ARM64_LSE_ATOMIC_INSN(
365 "prfm pstl1strm, %a0",
366 "nop") : : "p" (ptr));
367 }
368
369 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
370 extern void __init minsigstksz_setup(void);
371
372 /*
373 * Not at the top of the file due to a direct #include cycle between
374 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
375 * ensures that contents of processor.h are visible to fpsimd.h even if
376 * processor.h is included first.
377 *
378 * These prctl helpers are the only things in this file that require
379 * fpsimd.h. The core code expects them to be in this header.
380 */
381 #include <asm/fpsimd.h>
382
383 /* Userspace interface for PR_S[MV]E_{SET,GET}_VL prctl()s: */
384 #define SVE_SET_VL(arg) sve_set_current_vl(arg)
385 #define SVE_GET_VL() sve_get_current_vl()
386 #define SME_SET_VL(arg) sme_set_current_vl(arg)
387 #define SME_GET_VL() sme_get_current_vl()
388
389 /* PR_PAC_RESET_KEYS prctl */
390 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
391
392 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
393 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
394 ptrauth_set_enabled_keys(tsk, keys, enabled)
395 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
396
397 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
398 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
399 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
400 long get_tagged_addr_ctrl(struct task_struct *task);
401 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
402 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
403 #endif
404
405 /*
406 * For CONFIG_GCC_PLUGIN_STACKLEAK
407 *
408 * These need to be macros because otherwise we get stuck in a nightmare
409 * of header definitions for the use of task_stack_page.
410 */
411
412 /*
413 * The top of the current task's task stack
414 */
415 #define current_top_of_stack() ((unsigned long)current->stack + THREAD_SIZE)
416 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, 1, NULL))
417
418 #endif /* __ASSEMBLY__ */
419 #endif /* __ASM_PROCESSOR_H */
420