1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 */
6
7 #ifndef AMD_IOMMU_H
8 #define AMD_IOMMU_H
9
10 #include <linux/iommu.h>
11
12 #include "amd_iommu_types.h"
13
14 extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
15 extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
16 extern void amd_iommu_apply_erratum_63(u16 devid);
17 extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
18 extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
19 extern int amd_iommu_init_devices(void);
20 extern void amd_iommu_uninit_devices(void);
21 extern void amd_iommu_init_notifier(void);
22 extern int amd_iommu_init_api(void);
23
24 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
25 void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
26 #else
amd_iommu_debugfs_setup(struct amd_iommu * iommu)27 static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
28 #endif
29
30 /* Needed for interrupt remapping */
31 extern int amd_iommu_prepare(void);
32 extern int amd_iommu_enable(void);
33 extern void amd_iommu_disable(void);
34 extern int amd_iommu_reenable(int);
35 extern int amd_iommu_enable_faulting(void);
36 extern int amd_iommu_guest_ir;
37 extern enum io_pgtable_fmt amd_iommu_pgtable;
38
39 /* IOMMUv2 specific functions */
40 struct iommu_domain;
41
42 extern bool amd_iommu_v2_supported(void);
43 extern struct amd_iommu *get_amd_iommu(unsigned int idx);
44 extern u8 amd_iommu_pc_get_max_banks(unsigned int idx);
45 extern bool amd_iommu_pc_supported(void);
46 extern u8 amd_iommu_pc_get_max_counters(unsigned int idx);
47 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
48 u8 fxn, u64 *value);
49 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
50 u8 fxn, u64 *value);
51
52 extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
53 extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
54 extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
55 extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
56 extern int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
57 u64 address);
58 extern void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
59 extern void amd_iommu_domain_update(struct protection_domain *domain);
60 extern void amd_iommu_domain_flush_complete(struct protection_domain *domain);
61 extern void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain);
62 extern int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
63 extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
64 unsigned long cr3);
65 extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
66
67 #ifdef CONFIG_IRQ_REMAP
68 extern int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
69 #else
amd_iommu_create_irq_domain(struct amd_iommu * iommu)70 static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
71 {
72 return 0;
73 }
74 #endif
75
76 #define PPR_SUCCESS 0x0
77 #define PPR_INVALID 0x1
78 #define PPR_FAILURE 0xf
79
80 extern int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
81 int status, int tag);
82
is_rd890_iommu(struct pci_dev * pdev)83 static inline bool is_rd890_iommu(struct pci_dev *pdev)
84 {
85 return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
86 (pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
87 }
88
iommu_feature(struct amd_iommu * iommu,u64 mask)89 static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
90 {
91 return !!(iommu->features & mask);
92 }
93
iommu_virt_to_phys(void * vaddr)94 static inline u64 iommu_virt_to_phys(void *vaddr)
95 {
96 return (u64)__sme_set(virt_to_phys(vaddr));
97 }
98
iommu_phys_to_virt(unsigned long paddr)99 static inline void *iommu_phys_to_virt(unsigned long paddr)
100 {
101 return phys_to_virt(__sme_clr(paddr));
102 }
103
104 static inline
amd_iommu_domain_set_pt_root(struct protection_domain * domain,u64 root)105 void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
106 {
107 atomic64_set(&domain->iop.pt_root, root);
108 domain->iop.root = (u64 *)(root & PAGE_MASK);
109 domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
110 }
111
112 static inline
amd_iommu_domain_clr_pt_root(struct protection_domain * domain)113 void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
114 {
115 amd_iommu_domain_set_pt_root(domain, 0);
116 }
117
118
119 extern bool translation_pre_enabled(struct amd_iommu *iommu);
120 extern bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
121 struct device *dev);
122 extern int __init add_special_device(u8 type, u8 id, u16 *devid,
123 bool cmd_line);
124
125 #ifdef CONFIG_DMI
126 void amd_iommu_apply_ivrs_quirks(void);
127 #else
amd_iommu_apply_ivrs_quirks(void)128 static inline void amd_iommu_apply_ivrs_quirks(void) { }
129 #endif
130
131 extern void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
132 u64 *root, int mode);
133 #endif
134