Home
last modified time | relevance | path

Searched refs:ASID (Results 1 – 11 of 11) sorted by relevance

/arch/arm/include/asm/
Dmmu.h27 #define ASID(mm) ((unsigned int)((mm)->context.id.counter & ~ASID_MASK)) macro
29 #define ASID(mm) (0) macro
Dtlbflush.h363 const int asid = ASID(mm); in __local_flush_tlb_mm()
381 const int asid = ASID(mm); in local_flush_tlb_mm()
405 tlb_op(TLB_V7_UIS_ASID, "c8, c3, 2", ASID(mm)); in __flush_tlb_mm()
418 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __local_flush_tlb_page()
439 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in local_flush_tlb_page()
456 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in __flush_tlb_page()
/arch/arm/mm/
Dtlb-v7.S38 asid r3, r3 @ mask ASID
47 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
76 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
Dtlb-v6.S40 asid r3, r3 @ mask ASID
DKconfig609 This indicates whether the CPU has the ASID register; used to
/arch/arm64/include/asm/
Dtlbflush.h251 asid = __TLBI_VADDR(0, ASID(mm)); in flush_tlb_mm()
263 addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); in flush_tlb_page_nosync()
308 asid = ASID(vma->vm_mm); in __flush_tlb_range()
Dmmu.h56 #define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff) macro
Dmmu_context.h182 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
/arch/arm64/mm/
Dcontext.c352 unsigned long asid = ASID(mm); in cpu_do_switch_mm()
/arch/arm/
DKconfig889 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
893 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
898 entries regardless of the ASID.
926 bool "ARM errata: possible faulty MMU translations following an ASID switch"
931 which starts prior to an ASID switch but completes afterwards. This
933 the new ASID. This workaround places two dsb instructions in the mm
934 switching code so that no page table walks can cross the ASID switch.
990 which sends an IPI to the CPUs that are running the same ASID
/arch/arm64/
DKconfig914 contains data for a non-current ASID. The fix is to
977 bool "Falkor E1003: Incorrect translation due to ASID change"
980 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
981 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1434 zeroed area and reserved ASID. The user access routines