Searched refs:CLK_RESET_PLLC_BASE (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 34 #define CLK_RESET_PLLC_BASE 0x80 macro
205 pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
296 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
307 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
309 str r0, [r5, #CLK_RESET_PLLC_BASE]
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| D | sleep-tegra30.S | 48 #define CLK_RESET_PLLC_BASE 0x80 macro
395 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK
406 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK
415 pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
692 store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK
717 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
719 str r0, [r5, #CLK_RESET_PLLC_BASE]
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