Searched refs:ID_AA64PFR0_EL1_SVE_SHIFT (Results 1 – 4 of 4) sorted by relevance
| /arch/arm64/include/asm/ |
| D | el2_setup.h | 135 ubfx x1, x1, #ID_AA64PFR0_EL1_SVE_SHIFT, #4
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| D | cpufeature.h | 618 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT); in id_aa64pfr0_sve()
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| D | sysreg.h | 851 #define ID_AA64PFR0_EL1_SVE_SHIFT 32 macro
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| /arch/arm64/kernel/ |
| D | cpufeature.c | 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
2226 .field_pos = ID_AA64PFR0_EL1_SVE_SHIFT,
2699 …HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_EL1_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_EL1_SVE_IMP…
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