1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CPUTYPE_H
6 #define __ASM_CPUTYPE_H
7
8 #define INVALID_HWID ULONG_MAX
9
10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14 #define MPIDR_LEVEL_BITS_SHIFT 3
15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18 #define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24 #define MIDR_REVISION_MASK 0xf
25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26 #define MIDR_PARTNUM_SHIFT 4
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28 #define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30 #define MIDR_ARCHITECTURE_SHIFT 16
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32 #define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34 #define MIDR_VARIANT_SHIFT 20
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36 #define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38 #define MIDR_IMPLEMENTOR_SHIFT 24
39 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
40 #define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43 #define MIDR_CPU_MODEL(imp, partnum) \
44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48 #define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54 #define ARM_CPU_IMP_ARM 0x41
55 #define ARM_CPU_IMP_APM 0x50
56 #define ARM_CPU_IMP_CAVIUM 0x43
57 #define ARM_CPU_IMP_BRCM 0x42
58 #define ARM_CPU_IMP_QCOM 0x51
59 #define ARM_CPU_IMP_NVIDIA 0x4E
60 #define ARM_CPU_IMP_FUJITSU 0x46
61 #define ARM_CPU_IMP_HISI 0x48
62 #define ARM_CPU_IMP_APPLE 0x61
63 #define ARM_CPU_IMP_AMPERE 0xC0
64 #define ARM_CPU_IMP_MICROSOFT 0x6D
65
66 #define ARM_CPU_PART_AEM_V8 0xD0F
67 #define ARM_CPU_PART_FOUNDATION 0xD00
68 #define ARM_CPU_PART_CORTEX_A57 0xD07
69 #define ARM_CPU_PART_CORTEX_A72 0xD08
70 #define ARM_CPU_PART_CORTEX_A53 0xD03
71 #define ARM_CPU_PART_CORTEX_A73 0xD09
72 #define ARM_CPU_PART_CORTEX_A75 0xD0A
73 #define ARM_CPU_PART_CORTEX_A35 0xD04
74 #define ARM_CPU_PART_CORTEX_A55 0xD05
75 #define ARM_CPU_PART_CORTEX_A76 0xD0B
76 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
77 #define ARM_CPU_PART_CORTEX_A77 0xD0D
78 #define ARM_CPU_PART_NEOVERSE_V1 0xD40
79 #define ARM_CPU_PART_CORTEX_A78 0xD41
80 #define ARM_CPU_PART_CORTEX_A78AE 0xD42
81 #define ARM_CPU_PART_CORTEX_X1 0xD44
82 #define ARM_CPU_PART_CORTEX_A510 0xD46
83 #define ARM_CPU_PART_CORTEX_A520 0xD80
84 #define ARM_CPU_PART_CORTEX_A710 0xD47
85 #define ARM_CPU_PART_CORTEX_X2 0xD48
86 #define ARM_CPU_PART_NEOVERSE_N2 0xD49
87 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
88
89 #define APM_CPU_PART_POTENZA 0x000
90
91 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
92 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
93 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
94 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
95
96 #define BRCM_CPU_PART_BRAHMA_B53 0x100
97 #define BRCM_CPU_PART_VULCAN 0x516
98
99 #define QCOM_CPU_PART_FALKOR_V1 0x800
100 #define QCOM_CPU_PART_FALKOR 0xC00
101 #define QCOM_CPU_PART_KRYO 0x200
102 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
103 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
104 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
105 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
106 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
107
108 #define NVIDIA_CPU_PART_DENVER 0x003
109 #define NVIDIA_CPU_PART_CARMEL 0x004
110
111 #define FUJITSU_CPU_PART_A64FX 0x001
112
113 #define HISI_CPU_PART_TSV110 0xD01
114
115 #define APPLE_CPU_PART_M1_ICESTORM 0x022
116 #define APPLE_CPU_PART_M1_FIRESTORM 0x023
117 #define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
118 #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
119 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
120 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
121
122 #define AMPERE_CPU_PART_AMPERE1 0xAC3
123
124 #define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
125
126 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
127 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
128 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
129 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
130 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
131 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
132 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
133 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
134 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
135 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
136 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
137 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
138 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
139 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
140 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
141 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
142 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
143 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
144 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
145 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
146 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
147 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
148 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
149 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
150 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
151 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
152 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
153 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
154 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
155 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
156 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
157 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
158 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
159 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
160 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
161 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
162 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
163 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
164 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
165 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
166 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
167 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
168 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
169 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
170 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
171 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
172
173 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
174 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
175 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
176 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
177
178 #ifndef __ASSEMBLY__
179
180 #include <asm/sysreg.h>
181
182 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
183
184 /*
185 * Represent a range of MIDR values for a given CPU model and a
186 * range of variant/revision values.
187 *
188 * @model - CPU model as defined by MIDR_CPU_MODEL
189 * @rv_min - Minimum value for the revision/variant as defined by
190 * MIDR_CPU_VAR_REV
191 * @rv_max - Maximum value for the variant/revision for the range.
192 */
193 struct midr_range {
194 u32 model;
195 u32 rv_min;
196 u32 rv_max;
197 };
198
199 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
200 { \
201 .model = m, \
202 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
203 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
204 }
205
206 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
207 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
208 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
209
midr_is_cpu_model_range(u32 midr,u32 model,u32 rv_min,u32 rv_max)210 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
211 u32 rv_max)
212 {
213 u32 _model = midr & MIDR_CPU_MODEL_MASK;
214 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
215
216 return _model == model && rv >= rv_min && rv <= rv_max;
217 }
218
is_midr_in_range(u32 midr,struct midr_range const * range)219 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
220 {
221 return midr_is_cpu_model_range(midr, range->model,
222 range->rv_min, range->rv_max);
223 }
224
225 static inline bool
is_midr_in_range_list(u32 midr,struct midr_range const * ranges)226 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
227 {
228 while (ranges->model)
229 if (is_midr_in_range(midr, ranges++))
230 return true;
231 return false;
232 }
233
234 /*
235 * The CPU ID never changes at run time, so we might as well tell the
236 * compiler that it's constant. Use this function to read the CPU ID
237 * rather than directly reading processor_id or read_cpuid() directly.
238 */
read_cpuid_id(void)239 static inline u32 __attribute_const__ read_cpuid_id(void)
240 {
241 return read_cpuid(MIDR_EL1);
242 }
243
read_cpuid_mpidr(void)244 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
245 {
246 return read_cpuid(MPIDR_EL1);
247 }
248
read_cpuid_implementor(void)249 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
250 {
251 return MIDR_IMPLEMENTOR(read_cpuid_id());
252 }
253
read_cpuid_part_number(void)254 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
255 {
256 return MIDR_PARTNUM(read_cpuid_id());
257 }
258
read_cpuid_cachetype(void)259 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
260 {
261 return read_cpuid(CTR_EL0);
262 }
263 #endif /* __ASSEMBLY__ */
264
265 #endif
266