Home
last modified time | relevance | path

Searched refs:MIPS_CPU_IRQ_BASE (Results 1 – 25 of 52) sorted by relevance

123

/arch/mips/include/asm/mach-cobalt/
Dirq.h40 #define MIPS_CPU_IRQ_BASE 16 macro
42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
/arch/mips/sgi-ip30/
Dip30-common.h13 #define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)
14 #define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)
15 #define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)
16 #define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)
17 #define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)
/arch/mips/include/asm/mach-ip27/
Dirq.h17 #define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2)
18 #define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3)
19 #define IP27_RT_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 4)
21 #define IP27_HUB_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/arch/mips/cobalt/
Dirq.c37 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in plat_irq_dispatch()
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in plat_irq_dispatch()
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in plat_irq_dispatch()
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in plat_irq_dispatch()
/arch/mips/include/asm/mach-generic/
Dirq.h23 #ifndef MIPS_CPU_IRQ_BASE
25 #define MIPS_CPU_IRQ_BASE 16 macro
27 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/generic/
Dirq.c26 mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; in get_c0_fdc_int()
42 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; in get_c0_perfcount_int()
58 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; in get_c0_compare_int()
/arch/mips/sni/
Dpcit.c214 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint()
216 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint()
218 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint()
228 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in sni_pcit_hwint_cplus()
230 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint_cplus()
232 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint_cplus()
234 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint_cplus()
262 if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA", in sni_pcit_cplus_irq_init()
/arch/mips/loongson2ef/lemote-2f/
Dirq.c18 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
19 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
20 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
21 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
/arch/mips/ath25/
Dar5312_regs.h17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
/arch/mips/loongson2ef/fuloong-2e/
Dirq.c27 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in mach_irq_dispatch()
58 irq = MIPS_CPU_IRQ_BASE + 2; in mach_init_irq()
62 irq = MIPS_CPU_IRQ_BASE + 5; in mach_init_irq()
/arch/mips/include/asm/mach-db1x00/
Dirq.h16 #ifndef MIPS_CPU_IRQ_BASE
17 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/ralink/
Dirq.c23 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
24 #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
25 #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
26 #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
27 #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
/arch/mips/txx9/rbtx4939/
Dirq.c58 return MIPS_CPU_IRQ_BASE + 7; in rbtx4939_irq_dispatch()
68 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4939_irq_dispatch()
70 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4939_irq_dispatch()
/arch/mips/txx9/rbtx4938/
Dirq.c115 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4938_irq_dispatch()
121 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4938_irq_dispatch()
123 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4938_irq_dispatch()
/arch/mips/txx9/rbtx4927/
Dirq.c177 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4927_irq_dispatch()
183 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4927_irq_dispatch()
185 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4927_irq_dispatch()
/arch/mips/include/asm/mach-ath79/
Dirq.h9 #define MIPS_CPU_IRQ_BASE 0 macro
12 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
/arch/mips/include/asm/mach-loongson32/
Dirq.h14 #define MIPS_CPU_IRQ_BASE 0 macro
15 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
26 #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
/arch/mips/mti-malta/
Dmalta-time.c143 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; in get_c0_fdc_int()
156 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; in get_c0_perfcount_int()
173 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; in get_c0_compare_int()
/arch/mips/include/asm/
Dsni.h146 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
154 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
179 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
/arch/mips/include/asm/vr41xx/
Dirq.h19 #define MIPS_CPU_IRQ_BASE 0 macro
20 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
/arch/mips/include/asm/mach-bcm63xx/
Dirq.h6 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/include/asm/mach-pic32/
Dirq.h10 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/include/asm/mach-netlogic/
Dirq.h15 #define MIPS_CPU_IRQ_BASE 0 macro
/arch/mips/include/asm/mach-loongson64/
Dirq.h11 #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY macro

123