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Searched refs:MSR_ARCH_PERFMON_EVENTSEL0 (Results 1 – 5 of 5) sorted by relevance

/arch/x86/kernel/cpu/
Dperfctr-watchdog.c89 return msr - MSR_ARCH_PERFMON_EVENTSEL0; in nmi_evntsel_msr_to_bit()
102 return msr - MSR_ARCH_PERFMON_EVENTSEL0; in nmi_evntsel_msr_to_bit()
/arch/x86/include/asm/
Dperf_event.h18 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186 macro
/arch/x86/events/zhaoxin/
Dcore.c468 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
/arch/x86/kvm/
Dx86.c1369 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1370 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1371 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1372 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
6486 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 7: in kvm_init_msr_list()
6487 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= in kvm_init_msr_list()
/arch/x86/events/intel/
Dcore.c2246 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); in intel_pmu_nhm_workaround()
2261 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); in intel_pmu_nhm_workaround()
4564 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4615 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,