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Searched refs:SW (Results 1 – 19 of 19) sorted by relevance

/arch/ia64/kernel/
Dentry.h25 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET) macro
43 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
44 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
45 .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
46 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
47 .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
48 .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
49 .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
50 .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
51 .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
[all …]
Dentry.S246 adds r14=SW(R4)+16,sp
256 adds r15=SW(R5)+16,sp
260 add r14=SW(R4)+16,sp
262 st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
270 adds r15=SW(R5)+16,sp
273 st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
275 add r2=SW(F2)+16,sp // r2 = &sw->f2
277 st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
279 add r3=SW(F3)+16,sp // r3 = &sw->f3
286 st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
[all …]
Dmca_asm.S567 add temp1=SW(F2), regs
568 add temp2=SW(F3), regs
603 stf.spill [temp1]=f30,SW(B2)-SW(F30)
604 stf.spill [temp2]=f31,SW(B3)-SW(F31)
613 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
726 add temp1=SW(F2), regs
727 add temp2=SW(F3), regs
762 ldf.fill f30=[temp1],SW(B2)-SW(F30)
763 ldf.fill f31=[temp2],SW(B3)-SW(F31)
770 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
Dunwind.c2253 unw.sw_off[unw.preg_index[UNW_REG_PRI_UNAT_GR]] = SW(CALLER_UNAT); in unw_init()
2254 unw.sw_off[unw.preg_index[UNW_REG_BSPSTORE]] = SW(AR_BSPSTORE); in unw_init()
2255 unw.sw_off[unw.preg_index[UNW_REG_PFS]] = SW(AR_PFS); in unw_init()
2256 unw.sw_off[unw.preg_index[UNW_REG_RP]] = SW(B0); in unw_init()
2257 unw.sw_off[unw.preg_index[UNW_REG_UNAT]] = SW(CALLER_UNAT); in unw_init()
2258 unw.sw_off[unw.preg_index[UNW_REG_PR]] = SW(PR); in unw_init()
2259 unw.sw_off[unw.preg_index[UNW_REG_LC]] = SW(AR_LC); in unw_init()
2260 unw.sw_off[unw.preg_index[UNW_REG_FPSR]] = SW(AR_FPSR); in unw_init()
2261 for (i = UNW_REG_R4, off = SW(R4); i <= UNW_REG_R7; ++i, off += 8) in unw_init()
2263 for (i = UNW_REG_B1, off = SW(B1); i <= UNW_REG_B5; ++i, off += 8) in unw_init()
[all …]
/arch/arm64/
DMakefile.postlink22 --dump-section=$(shell $(READELF) -SW $@|grep -Eo '\.rela\.text\S*')=$@.rela.text \
23 --dump-section=$(shell $(READELF) -SW $@|grep -Eo '\.rela\.rodata\S*')=$@.rela.rodata && \
/arch/parisc/include/asm/
Dfloppy.h28 #define SW fd_routine[use_virtual_dma&1] macro
40 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
41 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
42 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/arch/x86/include/asm/
Dfloppy.h30 #define SW fd_routine[use_virtual_dma & 1] macro
42 #define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA)
43 #define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size)
44 #define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io)
/arch/arm/boot/dts/
Dexynos5250-arndale.dts34 label = "SW-TACT2";
41 label = "SW-TACT3";
48 label = "SW-TACT4";
55 label = "SW-TACT5";
62 label = "SW-TACT6";
69 label = "SW-TACT7";
Dkirkwood-topkick.dts121 * [SW] [*] [*] [*]
Dsun8i-a83t-cubietruck-plus.dts308 * I/O is indirectly powered from DCDC1, through SW. It is rated
Dexynos5420-arndale-octa.dts46 label = "SW-TACT1";
Dtegra30-colibri.dtsi892 /* SW: +V1.2_VDD_CORE */
Dtegra30-apalis.dtsi1023 /* SW: +V1.2_VDD_CORE */
Dtegra30-apalis-v1.1.dtsi1040 /* SW: +V1.2_VDD_CORE */
/arch/powerpc/kernel/
Dalign.c41 #define SW 0x20 /* byte swap */ macro
227 if (flags & SW) { in emulate_spe()
/arch/arm64/boot/dts/renesas/
Dr8a77995-draak.dts355 * CVBS and HDMI inputs through SW[49-53]
422 * CVBS and HDMI inputs through SW[49-53]
/arch/powerpc/platforms/
DKconfig.cputype69 bool "Support for 603 SW loaded TLB"
74 processors don't have a HASH MMU and provide SW TLB loading.
/arch/arm/mm/
Dproc-v7.S549 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
/arch/mips/net/
Dbpf_jit.c334 emit_long_instr(ctx, SW, reg, offset, base); in emit_store_stack_reg()