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Searched refs:SYS_ZCR_EL1 (Results 1 – 8 of 8) sorted by relevance

/arch/arm64/include/asm/
Dfpsimd.h196 tmp = read_sysreg_s(SYS_ZCR_EL1) & ~ZCR_ELx_LEN_MASK; in write_vl()
197 write_sysreg_s(tmp | val, SYS_ZCR_EL1); in write_vl()
Dfpsimdmacros.h256 mrs_s \xtmp, SYS_ZCR_EL1
261 msr_s SYS_ZCR_EL1, \xtmp2 //self-synchronising
Dsysreg.h214 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) macro
/arch/arm64/kvm/
Dfpsimd.c172 SYS_ZCR_EL1); in kvm_arch_vcpu_put_fp()
Dsys_regs.c1489 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
/arch/arm64/kernel/
Dfpsimd.c1116 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); in read_zcr_features()
1118 zcr = read_sysreg_s(SYS_ZCR_EL1); in read_zcr_features()
1144 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); in sve_setup()
Dcpufeature.c720 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
1022 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); in init_cpu_features()
1262 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, in update_cpu_features()
3019 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); in verify_sve_features()
/arch/arm64/kvm/hyp/nvhe/
Dhyp-main.c677 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL1); in __hyp_sve_save_guest()