Home
last modified time | relevance | path

Searched refs:__raw_writel (Results 1 – 25 of 244) sorted by relevance

12345678910

/arch/mips/alchemy/common/
Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
58 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
141 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
150 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
/arch/mips/sgi-ip22/
Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/arch/arm/mach-mmp/
Dtime.c55 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
75 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
80 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
97 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
102 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
103 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
108 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
113 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
126 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_shutdown()
158 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ in timer_config()
[all …]
Dpm-mmp2.c48 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
53 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
64 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()
65 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()
70 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()
80 __raw_writel(0x03003003, CIU_REG(0x64)); in pm_scu_clk_enable()
81 __raw_writel(0x00303030, CIU_REG(0x68)); in pm_scu_clk_enable()
86 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()
97 __raw_writel(0x0000a010, MPMU_CGR_PJ); in pm_mpmu_clk_disable()
104 __raw_writel(0xdffefffe, MPMU_CGR_PJ); in pm_mpmu_clk_enable()
[all …]
/arch/mips/kernel/
Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift, in txx9tmr_set_state_periodic()
[all …]
Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
77 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_unmask()
78 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_unmask()
88 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
93 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_mask()
94 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_mask()
109 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); in txx9_irq_mask_ack()
135 __raw_writel(cr, crp); in txx9_irq_set_type()
162 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
164 __raw_writel(0, &txx9_ircptr->ilr[i]); in txx9_irq_init()
[all …]
/arch/arm/mach-pxa/
Dsmemc.c36 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
37 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
38 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
39 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
45 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
64 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/arch/sh/mm/
Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
Dtlb-sh4.c30 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
42 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
48 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA); in __update_tlb()
58 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
78 __raw_writel(data, addr); in local_flush_tlb_one()
100 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
103 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/arch/mips/loongson32/common/
Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/arch/m68k/coldfire/
Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
185 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
193 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
195 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); in mcf_pci_init()
[all …]
/arch/sh/drivers/pci/
Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
261 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/arch/arm/mach-s3c/
Dpm-s3c2416.c27 __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG); in s3c2416_cpu_suspend()
30 __raw_writel(0x2BED, S3C2443_PWRMODE); in s3c2416_cpu_suspend()
45 __raw_writel(0x2BED, S3C2412_INFORM0); in s3c2416_pm_prepare()
46 __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1); in s3c2416_pm_prepare()
74 __raw_writel(0x0, S3C2443_PWRMODE); in s3c2416_pm_resume()
75 __raw_writel(0x0, S3C2412_INFORM0); in s3c2416_pm_resume()
76 __raw_writel(0x0, S3C2412_INFORM1); in s3c2416_pm_resume()
Dmach-n30.c452 __raw_writel(0x007fffff, S3C2410_GPACON); in n30_hwinit()
454 __raw_writel(0x007fefff, S3C2410_GPACON); in n30_hwinit()
455 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
470 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
471 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
472 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
489 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
490 __raw_writel(0x0000014c, S3C2410_GPCDAT); in n30_hwinit()
491 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
501 __raw_writel(0xaa95aaa4, S3C2410_GPDCON); in n30_hwinit()
[all …]
Dpm-core-s3c24xx.h27 __raw_writel(tmp, S3C2410_CLKCON); in s3c_pm_debug_init_uart()
34 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); in s3c_pm_arch_prepare_irqs()
35 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); in s3c_pm_arch_prepare_irqs()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
47 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ in s3c_pm_arch_stop_clocks()
/arch/mips/pci/
Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
247 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
261 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
266 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
281 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
284 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
/arch/sh/kernel/cpu/sh4a/
Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
35 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
112 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
115 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
116 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
Dsmp-shx3.c36 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ in ipi_interrupt_handler()
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
87 __raw_writel(entry_point, RESET_REG(cpu)); in shx3_start_cpu()
89 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu)); in shx3_start_cpu()
92 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_start_cpu()
98 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_start_cpu()
112 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ in shx3_send_ipi()
117 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_update_boot_vector()
120 __raw_writel(STBCR_RESET, STBCR_REG(cpu)); in shx3_update_boot_vector()
/arch/arm/mach-lpc32xx/
Dserial.c109 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
116 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
117 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
122 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
126 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
130 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
131 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
135 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
141 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
146 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/arch/sh/boards/mach-sh7763rdp/
Dirq.c28 __raw_writel(1 << 25, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
31 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, in init_sh7763rdp_IRQ()
35 __raw_writel(1 << 17, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
38 __raw_writel(1 << 16, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
41 __raw_writel(1 << 8, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
/arch/mips/ath79/
Dcommon.c61 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
66 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); in ath79_ddr_set_pci_windows()
77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); in ath79_ddr_set_pci_windows()
78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); in ath79_ddr_set_pci_windows()
79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); in ath79_ddr_set_pci_windows()
80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); in ath79_ddr_set_pci_windows()
81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); in ath79_ddr_set_pci_windows()
82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); in ath79_ddr_set_pci_windows()
83 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); in ath79_ddr_set_pci_windows()
/arch/mips/txx9/generic/
Dirq_tx4939.c66 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_unmask()
84 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_mask()
98 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf)) in tx4939_irq_mask_ack()
141 __raw_writel(cr, crp); in tx4939_irq_set_type()
172 __raw_writel(0, &tx4939_ircptr->den.r); in tx4939_irq_init()
173 __raw_writel(0, &tx4939_ircptr->maskint.r); in tx4939_irq_init()
174 __raw_writel(0, &tx4939_ircptr->maskext.r); in tx4939_irq_init()
184 __raw_writel(0, &tx4939_ircptr->msk.r); in tx4939_irq_init()
186 __raw_writel(0, &tx4939_ircptr->lvl[i].r); in tx4939_irq_init()
189 __raw_writel(0, &tx4939_ircptr->dm[i].r); in tx4939_irq_init()
[all …]
/arch/mips/include/asm/mach-au1x00/
Dau1000_dma.h160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
177 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
242 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); in init_dma()
248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
249 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
307 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); in set_dma_fifo_addr()
[all …]

12345678910