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/arch/arm/mach-s3c/
Diotiming-s3c2412.c41 unsigned int bank; in s3c2412_print_timing() local
43 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_print_timing()
44 bt = iot->bank[bank].io_2412; in s3c2412_print_timing()
49 "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank, in s3c2412_print_timing()
142 int bank; in s3c2412_iotiming_calc() local
145 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_calc()
146 bt = iot->bank[bank].io_2412; in s3c2412_iotiming_calc()
153 __func__, bank); in s3c2412_iotiming_calc()
176 int bank; in s3c2412_iotiming_set() local
180 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2412_iotiming_set()
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Diotiming-s3c2410.c35 int bank; in s3c2410_print_timing() local
37 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_print_timing()
38 bt = timings->bank[bank].io_2410; in s3c2410_print_timing()
43 "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank, in s3c2410_print_timing()
56 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() argument
58 return S3C2410_BANKCON0 + (bank << 2); in bank_reg()
362 int bank; in s3c2410_iotiming_calc() local
365 for (bank = 0; bank < MAX_BANKS; bank++) { in s3c2410_iotiming_calc()
366 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
367 bt = iot->bank[bank].io_2410; in s3c2410_iotiming_calc()
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/arch/x86/kernel/cpu/mce/
Damd.c122 static enum smca_bank_types smca_get_bank_type(unsigned int bank) in smca_get_bank_type() argument
126 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
129 b = &smca_banks[bank]; in smca_get_bank_type()
227 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
235 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
241 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
245 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
249 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
254 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
286 smca_set_misc_banks_map(bank, cpu); in smca_configure()
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Dintel.c158 int bank; in cmci_toggle_interrupt_mode() local
163 for_each_set_bit(bank, owned, MAX_NR_BANKS) { in cmci_toggle_interrupt_mode()
164 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
171 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
356 static void __cmci_disable_bank(int bank) in __cmci_disable_bank() argument
360 if (!test_bit(bank, this_cpu_ptr(mce_banks_owned))) in __cmci_disable_bank()
362 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
364 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
365 __clear_bit(bank, this_cpu_ptr(mce_banks_owned)); in __cmci_disable_bank()
416 void cmci_disable_bank(int bank) in cmci_disable_bank() argument
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Dinternal.h51 void cmci_disable_bank(int bank);
60 static inline void cmci_disable_bank(int bank) { } in cmci_disable_bank() argument
101 return m1->bank != m2->bank || in mce_cmp()
178 u32 mca_msr_reg(int bank, enum mca_msr reg);
Dcore.c82 u8 bank; /* bank number */ member
125 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
180 u32 mca_msr_reg(int bank, enum mca_msr reg) in mca_msr_reg() argument
184 case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank); in mca_msr_reg()
185 case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank); in mca_msr_reg()
186 case MCA_MISC: return MSR_AMD64_SMCA_MCx_MISC(bank); in mca_msr_reg()
187 case MCA_STATUS: return MSR_AMD64_SMCA_MCx_STATUS(bank); in mca_msr_reg()
192 case MCA_CTL: return MSR_IA32_MCx_CTL(bank); in mca_msr_reg()
193 case MCA_ADDR: return MSR_IA32_MCx_ADDR(bank); in mca_msr_reg()
194 case MCA_MISC: return MSR_IA32_MCx_MISC(bank); in mca_msr_reg()
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/arch/mips/sgi-ip32/
Dip32-memory.c24 int bank; in prom_meminit() local
28 for (bank=0; bank < CRIME_MAXBANKS; bank++) { in prom_meminit()
29 u64 bankctl = crime->bank_ctrl[bank]; in prom_meminit()
31 if (bank != 0 && base == 0) in prom_meminit()
39 bank, base, size >> 20); in prom_meminit()
/arch/arm/mach-omap2/
Dpowerdomain-common.c47 u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) in omap2_pwrdm_get_mem_bank_onstate_mask() argument
49 switch (bank) { in omap2_pwrdm_get_mem_bank_onstate_mask()
67 u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_retst_mask() argument
69 switch (bank) { in omap2_pwrdm_get_mem_bank_retst_mask()
87 u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) in omap2_pwrdm_get_mem_bank_stst_mask() argument
89 switch (bank) { in omap2_pwrdm_get_mem_bank_stst_mask()
Dpowerdomain.h185 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
186 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
190 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
191 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
228 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
229 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
234 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
235 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
236 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
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Dprm2xxx_3xxx.c111 int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_onst() argument
116 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); in omap2_pwrdm_set_mem_onst()
124 int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in omap2_pwrdm_set_mem_retst() argument
129 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_set_mem_retst()
137 int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_pwrst() argument
141 m = omap2_pwrdm_get_mem_bank_stst_mask(bank); in omap2_pwrdm_read_mem_pwrst()
147 int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in omap2_pwrdm_read_mem_retst() argument
151 m = omap2_pwrdm_get_mem_bank_retst_mask(bank); in omap2_pwrdm_read_mem_retst()
Dpowerdomain.c665 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) in pwrdm_set_mem_onst() argument
672 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_onst()
675 if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst))) in pwrdm_set_mem_onst()
679 pwrdm->name, bank, pwrst); in pwrdm_set_mem_onst()
682 ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); in pwrdm_set_mem_onst()
703 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) in pwrdm_set_mem_retst() argument
710 if (pwrdm->banks < (bank + 1)) in pwrdm_set_mem_retst()
713 if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst))) in pwrdm_set_mem_retst()
717 pwrdm->name, bank, pwrst); in pwrdm_set_mem_retst()
720 ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); in pwrdm_set_mem_retst()
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Dprm33xx.c235 static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, in am33xx_pwrdm_set_mem_onst() argument
240 m = pwrdm->mem_on_mask[bank]; in am33xx_pwrdm_set_mem_onst()
250 static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, in am33xx_pwrdm_set_mem_retst() argument
255 m = pwrdm->mem_ret_mask[bank]; in am33xx_pwrdm_set_mem_retst()
265 static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) in am33xx_pwrdm_read_mem_pwrst() argument
269 m = pwrdm->mem_pwrst_mask[bank]; in am33xx_pwrdm_read_mem_pwrst()
280 static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) in am33xx_pwrdm_read_mem_retst() argument
284 m = pwrdm->mem_retst_mask[bank]; in am33xx_pwrdm_read_mem_retst()
Dprm2xxx_3xxx.h110 extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
112 extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
114 extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
115 extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
/arch/alpha/kernel/
Dsys_ruffian.c184 unsigned long bank_addr, bank, ret = 0; in ruffian_get_bank_size() local
189 bank = *(vulp)bank_addr; in ruffian_get_bank_size()
192 if (bank & 0x01) { in ruffian_get_bank_size()
205 bank = (bank & 0x1e) >> 1; in ruffian_get_bank_size()
206 if (bank < ARRAY_SIZE(size)) in ruffian_get_bank_size()
207 ret = size[bank]; in ruffian_get_bank_size()
/arch/powerpc/boot/dts/
Dmedia5200.dts113 bank-width = <4>; // Width in bytes of the flash bank
114 device-width = <2>; // Two devices on each bank
120 bank-width = <4>; // Width in bytes of the flash bank
121 device-width = <2>; // Two devices on each bank
127 #interrupt-cells = <2>; // 0:bank 1:id; no type field
131 interrupts = <0 0 3 // IRQ bank 0
132 1 1 3>; // IRQ bank 1
/arch/x86/platform/scx200/
Dscx200_32.c51 int bank; in scx200_init_shadow() local
54 for (bank = 0; bank < 2; ++bank) in scx200_init_shadow()
55 scx200_gpio_shadow[bank] = inl(scx200_gpio_base + 0x10 * bank); in scx200_init_shadow()
/arch/x86/events/amd/
Diommu.c158 u32 shift, bank, cntr; in get_next_avail_iommu_bnk_cntr() local
164 for (bank = 0, shift = 0; bank < max_banks; bank++) { in get_next_avail_iommu_bnk_cntr()
166 shift = bank + (bank*3) + cntr; in get_next_avail_iommu_bnk_cntr()
171 event->hw.iommu_bank = bank; in get_next_avail_iommu_bnk_cntr()
185 u8 bank, u8 cntr) in clear_avail_iommu_bnk_cntr() argument
194 if ((bank > max_banks) || (cntr > max_cntrs)) in clear_avail_iommu_bnk_cntr()
197 shift = bank + cntr + (bank*3); in clear_avail_iommu_bnk_cntr()
241 u8 bank = hwc->iommu_bank; in perf_iommu_enable_event() local
246 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, &reg); in perf_iommu_enable_event()
252 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, &reg); in perf_iommu_enable_event()
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/arch/arm/mach-omap1/
Dirq.c70 static inline unsigned int irq_bank_readl(int bank, int offset) in irq_bank_readl() argument
72 return readl_relaxed(irq_banks[bank].va + offset); in irq_bank_readl()
74 static inline void irq_bank_writel(unsigned long value, int bank, int offset) in irq_bank_writel() argument
76 writel_relaxed(value, irq_banks[bank].va + offset); in irq_bank_writel()
104 signed int bank; in omap_irq_set_cfg() local
107 bank = IRQ_BANK(irq); in omap_irq_set_cfg()
109 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
112 irq_bank_writel(val, bank, offset); in omap_irq_set_cfg()
/arch/um/drivers/
Dpty.c81 char *pty, *bank, *cp; in getmaster() local
85 for (bank = "pqrs"; *bank; bank++) { in getmaster()
86 line[strlen("/dev/pty")] = *bank; in getmaster()
/arch/powerpc/sysdev/
Dfsl_lbc.c73 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { in fsl_lbc_find()
74 u32 br = in_be32(&lbc->bank[i].br); in fsl_lbc_find()
75 u32 or = in_be32(&lbc->bank[i].or); in fsl_lbc_find()
96 int bank; in fsl_upm_find() local
100 bank = fsl_lbc_find(addr_base); in fsl_upm_find()
101 if (bank < 0) in fsl_upm_find()
102 return bank; in fsl_upm_find()
108 br = in_be32(&lbc->bank[bank].br); in fsl_upm_find()
/arch/mips/boot/dts/pic32/
Dpic32mzda.dtsi96 microchip,gpio-bank = <0>;
110 microchip,gpio-bank = <1>;
124 microchip,gpio-bank = <2>;
138 microchip,gpio-bank = <3>;
152 microchip,gpio-bank = <4>;
166 microchip,gpio-bank = <5>;
180 microchip,gpio-bank = <6>;
194 microchip,gpio-bank = <7>;
210 microchip,gpio-bank = <8>;
224 microchip,gpio-bank = <9>;
/arch/arm/kernel/
Dtcm.c111 static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks, in setup_tcm_bank() argument
127 : "r" (bank)); in setup_tcm_bank()
140 type ? "I" : "D", bank); in setup_tcm_bank()
144 type ? "I" : "D", bank); in setup_tcm_bank()
149 bank, in setup_tcm_bank()
176 bank, in setup_tcm_bank()
/arch/arm/mach-pxa/
Dmfp-pxa2xx.c55 int bank = gpio_to_bank(gpio); in __mfp_config_gpio() local
65 gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank); in __mfp_config_gpio()
69 GAFR_L(bank) = gafr; in __mfp_config_gpio()
71 GAFR_U(bank) = gafr; in __mfp_config_gpio()
81 PGSR(bank) |= mask; in __mfp_config_gpio()
85 PGSR(bank) &= ~mask; in __mfp_config_gpio()
99 gpdr_lpm[bank] |= mask; in __mfp_config_gpio()
101 gpdr_lpm[bank] &= ~mask; in __mfp_config_gpio()
/arch/powerpc/platforms/85xx/
Dp1022_ds.c233 br0 = in_be32(&lbc->bank[0].br); in p1022ds_set_monitor_port()
234 br1 = in_be32(&lbc->bank[1].br); in p1022ds_set_monitor_port()
235 or0 = in_be32(&lbc->bank[0].or); in p1022ds_set_monitor_port()
236 or1 = in_be32(&lbc->bank[1].or); in p1022ds_set_monitor_port()
252 out_be32(&lbc->bank[0].br, br0); in p1022ds_set_monitor_port()
253 out_be32(&lbc->bank[0].or, or0); in p1022ds_set_monitor_port()
258 out_be32(&lbc->bank[1].br, br1); in p1022ds_set_monitor_port()
259 out_be32(&lbc->bank[1].or, or1); in p1022ds_set_monitor_port()
/arch/arm/boot/dts/
Dstm32f7-pinctrl.dtsi27 st,bank-name = "GPIOA";
37 st,bank-name = "GPIOB";
47 st,bank-name = "GPIOC";
57 st,bank-name = "GPIOD";
67 st,bank-name = "GPIOE";
77 st,bank-name = "GPIOF";
87 st,bank-name = "GPIOG";
97 st,bank-name = "GPIOH";
107 st,bank-name = "GPIOI";
117 st,bank-name = "GPIOJ";
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