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Searched refs:base_reg (Results 1 – 7 of 7) sorted by relevance

/arch/sparc/include/asm/
Dwinmacro.h38 #define LOAD_PT_INS(base_reg) \ argument
39 ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \
40 ldd [%base_reg + STACKFRAME_SZ + PT_I2], %i2; \
41 ldd [%base_reg + STACKFRAME_SZ + PT_I4], %i4; \
42 ldd [%base_reg + STACKFRAME_SZ + PT_I6], %i6;
44 #define LOAD_PT_GLOBALS(base_reg) \ argument
45 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \
46 ldd [%base_reg + STACKFRAME_SZ + PT_G2], %g2; \
47 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
48 ldd [%base_reg + STACKFRAME_SZ + PT_G6], %g6;
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/arch/arm/mach-omap1/
Dirq.c59 unsigned long base_reg; member
117 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
118 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
119 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
125 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
126 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
129 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
130 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
137 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
138 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
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/arch/nds32/kernel/
Dtraps.c57 static void __dump(struct task_struct *tsk, unsigned long *base_reg, in __dump() argument
64 while (!kstack_end(base_reg)) { in __dump()
65 ret_addr = *base_reg++; in __dump()
75 while (!kstack_end((void *)base_reg) && in __dump()
76 !((unsigned long)base_reg & 0x3) && in __dump()
77 ((unsigned long)base_reg >= TASK_SIZE)) { in __dump()
79 ret_addr = base_reg[LP_OFFSET]; in __dump()
80 next_fp = base_reg[FP_OFFSET]; in __dump()
89 base_reg = (unsigned long *)next_fp; in __dump()
97 unsigned long *base_reg; in show_stack() local
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/arch/mips/kernel/
Dmips-cm.c201 u32 base_reg; in __mips_cm_l2sync_phys_base() local
207 base_reg = read_gcr_l2_only_sync_base(); in __mips_cm_l2sync_phys_base()
208 if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN) in __mips_cm_l2sync_phys_base()
209 return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE; in __mips_cm_l2sync_phys_base()
244 u32 base_reg; in mips_cm_probe() local
264 base_reg = read_gcr_base(); in mips_cm_probe()
265 if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) { in mips_cm_probe()
/arch/powerpc/perf/
Dimc-pmu.c225 u32 handle, base_reg; in update_events_in_group() local
254 of_property_read_u32(node, "reg", &base_reg); in update_events_in_group()
264 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]); in update_events_in_group()
/arch/x86/kvm/
Demulate.c1201 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) in adjust_modrm_seg() argument
1203 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) in adjust_modrm_seg()
1211 int index_reg, base_reg, scale; in decode_modrm() local
1217 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ in decode_modrm()
1221 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); in decode_modrm()
1303 base_reg |= sib & 7; in decode_modrm()
1306 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) in decode_modrm()
1309 modrm_ea += reg_read(ctxt, base_reg); in decode_modrm()
1310 adjust_modrm_seg(ctxt, base_reg); in decode_modrm()
1313 base_reg == VCPU_REGS_RSP) in decode_modrm()
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/arch/x86/kvm/vmx/
Dnested.c4757 int base_reg = (vmx_instruction_info >> 23) & 0xf; in get_vmx_mem_address() local
4773 off += kvm_register_read(vcpu, base_reg); in get_vmx_mem_address()