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Searched refs:csr_read (Results 1 – 9 of 9) sorted by relevance

/arch/riscv/errata/
Dalternative.c30 cpu_mfr_info.vendor_id = csr_read(CSR_MVENDORID); in riscv_fill_cpu_mfr_info()
31 cpu_mfr_info.arch_id = csr_read(CSR_MARCHID); in riscv_fill_cpu_mfr_info()
32 cpu_mfr_info.imp_id = csr_read(CSR_MIMPID); in riscv_fill_cpu_mfr_info()
/arch/riscv/include/asm/
Dtimex.h53 return csr_read(CSR_TIME); in get_cycles()
59 return csr_read(CSR_TIMEH); in get_cycles_hi()
Dirqflags.h16 return csr_read(CSR_STATUS); in arch_local_save_flags()
Dcsr.h175 #define csr_read(csr) \ macro
/arch/riscv/include/asm/vdso/
Dgettimeofday.h71 return csr_read(CSR_TIME); in __arch_get_hw_counter()
/arch/riscv/mm/
Dcontext.c233 old = csr_read(CSR_SATP); in asids_init()
236 asid_bits = (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; in asids_init()
Dfault.c125 pfn = csr_read(CSR_SATP) & SATP_PPN; in vmalloc_fault()
/arch/riscv/kernel/
Dperf_event.c188 val = csr_read(CSR_CYCLE); in read_counter()
191 val = csr_read(CSR_INSTRET); in read_counter()
Dtraps_misaligned.c245 unsigned long addr = csr_read(mtval); in handle_misaligned_load()
328 unsigned long addr = csr_read(mtval); in handle_misaligned_store()