Searched refs:enable_mask (Results 1 – 6 of 6) sorted by relevance
| /arch/arm/mach-ep93xx/ |
| D | clock.c | 33 u32 enable_mask; member
54 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
61 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
68 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
89 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
95 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
102 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
117 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
124 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
132 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
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| /arch/arm/mach-omap2/ |
| D | display.c | 83 u32 enable_mask, enable_shift; in omap4_dsi_mux_pads() local
89 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; in omap4_dsi_mux_pads()
94 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; in omap4_dsi_mux_pads()
108 reg &= ~enable_mask; in omap4_dsi_mux_pads()
111 reg |= (lanes << enable_shift) & enable_mask; in omap4_dsi_mux_pads()
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| /arch/mips/kernel/ |
| D | sysrq.c | 59 .enable_mask = SYSRQ_ENABLE_DUMP,
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| /arch/x86/events/amd/ |
| D | ibs.c | 88 u64 enable_mask; member
382 wrmsrl(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
384 wrmsrl(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
400 config &= ~perf_ibs->enable_mask; in perf_ibs_disable_event()
558 .enable_mask = IBS_FETCH_ENABLE,
584 .enable_mask = IBS_OP_ENABLE,
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| /arch/x86/events/ |
| D | perf_event.h | 1106 u64 enable_mask) in __x86_pmu_enable_event() argument
1120 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); in __x86_pmu_enable_event()
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| /arch/alpha/kernel/ |
| D | setup.c | 433 .enable_mask = SYSRQ_ENABLE_BOOT,
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