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/arch/arm/mach-omap1/
Dams-delta-fiq-handler.S95 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
97 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
121 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
123 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
143 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
145 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
166 data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
170 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
183 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
/arch/m68k/ifpsp060/src/
Disp.S886 # (An) - fetch An value from stack #
887 # -(An) - fetch An value from stack; return decr value; #
891 # (An)+ - fetch An value from stack; return value; #
895 # (d16,An) - fetch An value from stack; read d16 using #
896 # _imem_read_word(); fetch may fail -> branch to #
898 # (xxx).w,(xxx).l - use _imem_read_{word,long}() to fetch #
899 # address; fetch may fail #
902 # (d16,PC) - fetch stacked PC value; read d16 using #
903 # _imem_read_word(); fetch may fail -> branch to #
917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
[all …]
Dpfpsp.S954 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1234 bsr.l _imem_read_long # fetch the instruction words
1322 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1327 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1439 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent
1531 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1843 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1850 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1867 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
[all …]
Dfplsp.S577 bsr.l tag # fetch operand type
634 bsr.l tag # fetch operand type
693 bsr.l tag # fetch operand type
754 bsr.l tag # fetch operand type
811 bsr.l tag # fetch operand type
870 bsr.l tag # fetch operand type
931 bsr.l tag # fetch operand type
988 bsr.l tag # fetch operand type
1047 bsr.l tag # fetch operand type
1108 bsr.l tag # fetch operand type
[all …]
Dfpsp.S955 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
1233 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1235 bsr.l _imem_read_long # fetch the instruction words
1323 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1328 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1440 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent
1532 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1844 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1851 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1868 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
[all …]
Dilsp.S134 mov.l 0x8(%a6),%d7 # fetch divisor
/arch/ia64/lib/
Dclear_page.S47 .fetch: stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE label
49 br.cloop.sptk.few .fetch
/arch/alpha/lib/
Dev6-memcpy.S146 ldq $1, 0($17) # L : fetch 8
166 ldbu $1, 0($17) # L : fetch a byte
189 ldbu $1, 0($17) # L : fetch a byte
228 ldbu $1, 0($17) # L : fetch 1
Dev6-copy_user.S85 EXI( ldq_u $3,0($17) ) # .. L .. .. : Forward fetch for fallthrough code
/arch/m68k/ifpsp060/
Dos.S155 dmrbuae:movs.b (%a0),%d0 | fetch user byte
157 dmrbs: move.b (%a0),%d0 | fetch super byte
191 dmrwuae:movs.w (%a0), %d0 | fetch user word
193 dmrws: move.w (%a0), %d0 | fetch super word
226 dmrluae:movs.l (%a0),%d0 | fetch user longword
228 dmrls: move.l (%a0),%d0 | fetch super longword
/arch/sh/kernel/cpu/sh3/
Dswsusp.S113 stc r2_bank, k0 ! fetch old sp from r2_bank0
117 stc r0_bank, k3 ! fetch old pr from r0_bank0
/arch/arm/nwfpe/
Dentry.S73 ldr r1, [sp, #S_PSR] @ fetch the PSR
/arch/x86/kvm/
Dkvm_emulate.h146 int (*fetch)(struct x86_emulate_ctxt *ctxt, member
370 struct fetch_cache fetch; member
Demulate.c724 bool write, bool fetch, in __linearize() argument
758 if (!fetch && (desc.type & 8) && !(desc.type & 2)) in __linearize()
930 int cur_size = ctxt->fetch.end - ctxt->fetch.data; in __do_insn_fetch_bytes()
961 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, in __do_insn_fetch_bytes()
965 ctxt->fetch.end += size; in __do_insn_fetch_bytes()
972 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; in do_insn_fetch_bytes()
988 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \
989 ctxt->fetch.ptr += sizeof(_type); \
999 memcpy(_arr, ctxt->fetch.ptr, _size); \
1000 ctxt->fetch.ptr += (_size); \
[all …]
Dtrace.h797 __entry->len = vcpu->arch.emulate_ctxt->fetch.ptr
798 - vcpu->arch.emulate_ctxt->fetch.data;
801 vcpu->arch.emulate_ctxt->fetch.data,
/arch/nios2/
DKconfig80 Nios II CPUs cannot fetch/store data which is not bus aligned,
81 i.e., a 2 or 4 byte fetch must start at an address divisible by
/arch/sh/
DKconfig.cpu69 This enables support for a speculative instruction fetch for
/arch/arc/kernel/
Dentry-arcv2.S121 ; Instruction fetch or Data access, under a single Exception Vector
/arch/x86/kvm/mmu/
Dpaging_tmpl.h663 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr, in FNAME() argument
935 r = FNAME(fetch)(vcpu, addr, &walker, error_code, max_level, pfn, in FNAME()
/arch/nds32/
DKconfig.cpu51 instruction fetch and execution overhead of loop-control instructions.
/arch/x86/events/intel/
Dcore.c362 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
377 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
1609 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1611 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1765 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
5237 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", …
/arch/sparc/lib/
Dchecksum_32.S140 addx %g0, %o2, %o2 ! fetch final carry
DM7memcpy.S725 EX_LD_FP(LOAD(ldd, %o4, %f0), memcpy_retl_o2_plus_o5)! fetch partialword
/arch/x86/math-emu/
DREADME134 The FPU instruction may be (usually will be) loaded into the pre-fetch
/arch/arm/
DKconfig1547 ARM processors cannot fetch/store information which is not
1548 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1550 fetch/store instructions will be emulated in software if you say

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