| /arch/x86/platform/intel-quark/ |
| D | imr.c | 92 static inline int imr_is_enabled(struct imr_regs *imr) in imr_is_enabled() argument
94 return !(imr->rmask == IMR_READ_ACCESS_ALL && in imr_is_enabled()
95 imr->wmask == IMR_WRITE_ACCESS_ALL && in imr_is_enabled()
96 imr_to_phys(imr->addr_lo) == 0 && in imr_is_enabled()
97 imr_to_phys(imr->addr_hi) == 0); in imr_is_enabled()
110 static int imr_read(struct imr_device *idev, u32 imr_id, struct imr_regs *imr) in imr_read() argument
115 ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_lo); in imr_read()
119 ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->addr_hi); in imr_read()
123 ret = iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->rmask); in imr_read()
127 return iosf_mbi_read(QRK_MBI_UNIT_MM, MBI_REG_READ, reg++, &imr->wmask); in imr_read()
[all …]
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| D | Makefile | 2 obj-$(CONFIG_INTEL_IMR) += imr.o
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| /arch/m68k/coldfire/ |
| D | intc.c | 47 u16 imr; in mcf_setimr() local
48 imr = __raw_readw(MCFSIM_IMR); in mcf_setimr()
49 __raw_writew(imr | (0x1 << index), MCFSIM_IMR); in mcf_setimr()
54 u16 imr; in mcf_clrimr() local
55 imr = __raw_readw(MCFSIM_IMR); in mcf_clrimr()
56 __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR); in mcf_clrimr()
61 u16 imr; in mcf_maskimr() local
62 imr = __raw_readw(MCFSIM_IMR); in mcf_maskimr()
63 imr |= mask; in mcf_maskimr()
64 __raw_writew(imr, MCFSIM_IMR); in mcf_maskimr()
[all …]
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| D | intc-525x.c | 23 u32 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask() local
28 imr &= ~(0x001 << irq); in intc2_irq_gpio_mask()
30 imr &= ~(0x100 << irq); in intc2_irq_gpio_mask()
31 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
36 u32 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask() local
41 imr |= (0x001 << irq); in intc2_irq_gpio_unmask()
43 imr |= (0x100 << irq); in intc2_irq_gpio_unmask()
44 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
49 u32 imr = 0; in intc2_irq_gpio_ack() local
54 imr |= (0x001 << irq); in intc2_irq_gpio_ack()
[all …]
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| D | intc-5249.c | 22 u32 imr; in intc2_irq_gpio_mask() local
23 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
24 imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0)); in intc2_irq_gpio_mask()
25 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_mask()
30 u32 imr; in intc2_irq_gpio_unmask() local
31 imr = readl(MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
32 imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0)); in intc2_irq_gpio_unmask()
33 writel(imr, MCFSIM2_GPIOINTENABLE); in intc2_irq_gpio_unmask()
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| /arch/mips/sgi-ip30/ |
| D | ip30-irq.c | 51 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
60 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
94 heart_write(mask, &heart_regs->imr[cpu]); in ip30_error_irq()
105 mask = (heart_read(&heart_regs->imr[cpu]) & in ip30_normal_irq()
150 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_heart_irq()
159 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_mask_and_ack_heart_irq()
169 heart_write(*mask, &heart_regs->imr[hd->cpu]); in ip30_unmask_heart_irq()
259 heart_write(*mask, &heart_regs->imr[cpu]); in ip30_install_ipi()
272 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]); in arch_init_irq()
273 heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[1]); in arch_init_irq()
[all …]
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| /arch/mips/kernel/ |
| D | irq_txx9.c | 28 u32 imr; member
77 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_unmask()
78 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_unmask()
93 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_mask()
94 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_mask()
162 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
170 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_init()
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| /arch/m68k/include/asm/ |
| D | mcfintc.h | 79 static inline void mcf_mapirq2imr(int irq, int imr) in mcf_mapirq2imr() argument
81 mcf_irq2imr[irq] = imr; in mcf_mapirq2imr()
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| /arch/x86/kvm/ |
| D | i8259.c | 112 return (s->imr & mask) ? -1 : ret; in pic_set_irq1()
137 mask = s->irr & ~s->imr; in pic_get_irq()
198 s->pics[irq >> 3].imr, ret == 0); in kvm_pic_set_irq()
281 s->imr = 0; in kvm_pic_reset()
368 u8 imr_diff = s->imr ^ val, in pic_ioport_write()
370 s->imr = val; in pic_ioport_write()
377 !!(s->imr & (1 << irq))); in pic_ioport_write()
436 ret = s->imr; in pic_ioport_read()
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| D | irq.h | 31 u8 imr; /* interrupt mask register */ member
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| D | trace.h | 464 TP_PROTO(__u8 chip, __u8 pin, __u8 elcr, __u8 imr, bool coalesced),
465 TP_ARGS(chip, pin, elcr, imr, coalesced),
471 __field( __u8, imr )
479 __entry->imr = imr;
486 (__entry->imr & (1 << __entry->pin)) ? "|masked":"",
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| /arch/powerpc/include/asm/ |
| D | mpc52xx_psc.h | 184 u16 imr; member
187 #define mpc52xx_psc_imr isr_imr.imr
330 u16 imr; /* PSC + 0x24 */ member
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| /arch/powerpc/sysdev/ |
| D | fsl_rmu.c | 118 u32 imr; member
904 out_be32(&rmu->msg_regs->imr, 0x001b0060); in fsl_open_inb_mbox()
907 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); in fsl_open_inb_mbox()
910 setbits32(&rmu->msg_regs->imr, 0x1); in fsl_open_inb_mbox()
930 out_be32(&rmu->msg_regs->imr, 0); in fsl_close_inb_mbox()
1013 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); in fsl_get_inb_message()
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| /arch/mips/include/asm/sgi/ |
| D | heart.h | 112 u64 imr[HEART_MAX_CPUS]; /* + 0x10000 */ member
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| /arch/x86/include/uapi/asm/ |
| D | kvm.h | 68 __u8 imr; /* interrupt mask register */ member
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| /arch/arm64/boot/dts/renesas/ |
| D | r8a77951.dtsi | 2839 imr-lx4@fe860000 {
2840 compatible = "renesas,r8a7795-imr-lx4",
2841 "renesas,imr-lx4";
2849 imr-lx4@fe870000 {
2850 compatible = "renesas,r8a7795-imr-lx4",
2851 "renesas,imr-lx4";
2859 imr-lx4@fe880000 {
2860 compatible = "renesas,r8a7795-imr-lx4",
2861 "renesas,imr-lx4";
2869 imr-lx4@fe890000 {
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| D | r8a77960.dtsi | 2589 imr-lx4@fe860000 {
2590 compatible = "renesas,r8a7796-imr-lx4",
2591 "renesas,imr-lx4";
2599 imr-lx4@fe870000 {
2600 compatible = "renesas,r8a7796-imr-lx4",
2601 "renesas,imr-lx4";
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