Searched refs:in_be64 (Results 1 – 21 of 21) sorted by relevance
31 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_and()39 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_or()50 return in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_get()60 return in_be64(&spu->priv1->int_stat_RW[class]); in int_stat_get()83 return in_be64(&spu->priv1->mfc_dar_RW); in mfc_dar_get()88 return in_be64(&spu->priv1->mfc_dsisr_RW); in mfc_dsisr_get()108 return in_be64(&spu->priv1->mfc_sr1_RW); in mfc_sr1_get()118 return in_be64(&spu->priv1->mfc_tclass_id_RW); in mfc_tclass_id_get()133 return in_be64(&spu->priv1->resource_allocation_groupID_RW); in resource_allocation_groupID_get()143 return in_be64(&spu->priv1->resource_allocation_enable_RW); in resource_allocation_enable_get()
39 in_be64(&pregs->checkstop_fir)); in dump_fir()41 in_be64(&pregs->checkstop_fir)); in dump_fir()43 in_be64(&pregs->spec_att_mchk_fir)); in dump_fir()48 in_be64(&iregs->ioc_fir)); in dump_fir()288 if (in_be64(®s->ras_esc_0) & 0x0000ffff) { in cbe_sysreset_hack()
83 value.val = in_be64(®->val); in spu_read_register_value()105 value = in_be64(&pmd_regs->tm_tpr.val); in show_throttle()127 reg_value = in_be64(&pmd_regs->tm_tpr.val); in store_throttle()180 value = in_be64(&pmd_regs->ts_ctsr2); in ppe_show_temp()
146 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) in invalidate_tce_cache()235 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); in ioc_interrupt()393 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); in cell_iommu_enable_hardware()409 in_be64(iommu->xlate_regs + IOC_IOST_Origin); in cell_iommu_enable_hardware()412 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; in cell_iommu_enable_hardware()700 (void)in_be64(xregs + IOC_IOST_Origin); in cell_disable_iommus()701 val = in_be64(cregs + IOC_IOCmd_Cfg); in cell_disable_iommus()704 (void)in_be64(cregs + IOC_IOCmd_Cfg); in cell_disable_iommus()
54 (val) = (u32)(in_be64(&pmd_regs->reg) >> 32); \328 *buf++ = in_be64(&pmd_regs->trace_buffer_0_63); in cbe_read_trace_buffer()329 *buf++ = in_be64(&pmd_regs->trace_buffer_64_127); in cbe_read_trace_buffer()
120 out_be64(®s->pmcr, in_be64(®s->pmcr) | in cbe_pervasive_init()
100 bits = in_be64(&node_iic->iic_is); in iic_ioexc_cascade()137 in_be64((u64 __iomem *) &iic->regs->pending_destr); in iic_get_irq()
174 switch (in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()177 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()184 in_be64(&priv2->mfc_control_RW) | in save_mfc_cntl()189 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()194 in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()260 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask; in save_mfc_stopped_status()304 POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING); in do_mfc_mssync()342 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) { in save_mfc_queues()345 in_be64(&priv2->puq[i].mfc_cq_data0_RW); in save_mfc_queues()347 in_be64(&priv2->puq[i].mfc_cq_data1_RW); in save_mfc_queues()[all …]
92 *data = in_be64(&priv2->puint_mb_R); in spu_hw_ibox_read()141 tmp = in_be64(&priv2->spu_cfg_RW); in spu_hw_signal1_type_set()152 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0); in spu_hw_signal1_type_get()162 tmp = in_be64(&priv2->spu_cfg_RW); in spu_hw_signal2_type_set()173 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0); in spu_hw_signal2_type_get()
110 while ((in_be64(mfc_cntl) & MFC_CNTL_PURGE_DMA_STATUS_MASK) in spu_setup_isolated()
2499 mfc_control_RW = in_be64(&priv2->mfc_control_RW); in spufs_show_ctx()
90 *v = rng_whiten(rng, in_be64(rng->regs)); in powernv_get_random_long()140 val = in_be64(rng->regs); in rng_create()
585 val = in_be64(arva + PNV_OCXL_ATSD_STAT); in pnv_ocxl_tlb_invalidate()595 val = in_be64(arva + PNV_OCXL_ATSD_STAT); in pnv_ocxl_tlb_invalidate()
475 return in_be64(win->hvwc_map+reg); in read_hvwc_reg()
119 *val = in_be64(phb->regs + offset); in pnv_eeh_dbgfs_get()
368 while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status) in ps3_create_spu()514 return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW); in mfc_dar_get()524 return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW); in mfc_dsisr_get()
167 DEF_MMIO_IN_D(in_be64, 64, ld);172 return swab64(in_be64(addr)); in in_le64()184 static inline u64 in_be64(const volatile u64 __iomem *addr) in in_be64() function548 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
418 u64 val = in_be64(addr); in eeh_readq_be()
401 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); in xive_native_setup_cpu()438 in_be64(xive_tima + TM_SPC_PULL_POOL_CTX); in xive_native_teardown_cpu()
217 val = in_be64(xd->eoi_mmio + offset); in xive_esb_read()
40 val = in_be64(xd->eoi_mmio + offset); in xive_vm_esb_load()