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/arch/arm/boot/dts/
Dintel-ixp45x-ixp46x.dtsi8 #include "intel-ixp4xx.dtsi"
13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
19 compatible = "intel,ixp46x-rng";
24 compatible = "intel,ixp43x-interrupt";
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
50 intel,npe = <1>;
58 compatible = "intel,ixp4xx-ethernet";
61 intel,npe = <2>;
[all …]
Dintel-ixp42x-arcom-vulcan.dts10 #include "intel-ixp42x.dtsi"
15 compatible = "arcom,vulcan", "intel,ixp42x";
42 compatible = "intel,ixp4xx-flash", "cfi-flash";
55 intel,ixp4xx-eb-t3 = <3>;
56 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
57 intel,ixp4xx-eb-write-enable = <1>;
71 intel,ixp4xx-eb-t3 = <1>;
72 intel,ixp4xx-eb-t4 = <2>;
73 intel,ixp4xx-eb-ahb-split-transfers = <1>;
74 intel,ixp4xx-eb-write-enable = <1>;
[all …]
Dintel-ixp46x-ixdp465.dts9 #include "intel-ixp45x-ixp46x.dtsi"
10 #include "intel-ixp4xx-reference-design.dtsi"
15 compatible = "intel,ixdp465", "intel,ixp46x";
22 compatible = "intel,ixp4xx-flash", "cfi-flash";
25 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp43x-kixrp435.dts9 #include "intel-ixp43x.dtsi"
10 #include "intel-ixp4xx-reference-design.dtsi"
15 compatible = "intel,kixrp435", "intel,ixp43x";
22 compatible = "intel,ixp4xx-flash", "cfi-flash";
25 intel,ixp4xx-eb-write-enable = <1>;
65 intel,npe-handle = <&npe 0>;
Dintel-ixp42x-gateworks-gw2348.dts9 #include "intel-ixp42x.dtsi"
14 compatible = "gateworks,gw2348", "intel,ixp42x";
69 compatible = "intel,ixp4xx-flash", "cfi-flash";
72 intel,ixp4xx-eb-write-enable = <1>;
83 compatible = "intel,ixp4xx-compact-flash";
89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
[all …]
Dintel-ixp42x.dtsi6 #include "intel-ixp4xx.dtsi"
11 compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
16 compatible = "intel,ixp42x-pci";
20 compatible = "intel,ixp42x-interrupt";
28 compatible = "intel,ixp4xx-udc";
Dintel-ixp43x-gateworks-gw2358.dts8 #include "intel-ixp43x.dtsi"
12 compatible = "gateworks,gw2358", "intel,ixp43x";
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
85 intel,ixp4xx-eb-write-enable = <1>;
99 compatible = "intel,ixp4xx-compact-flash";
105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
[all …]
Dintel-ixp42x-ixdp425.dts13 #include "intel-ixp42x.dtsi"
14 #include "intel-ixp4xx-reference-design.dtsi"
19 compatible = "intel,ixdp425", "intel,ixp42x";
26 compatible = "intel,ixp4xx-flash", "cfi-flash";
29 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp4xx.dtsi45 compatible = "intel,ixp4xx-ahb-queue-manager";
87 compatible = "intel,xscale-uart";
101 compatible = "intel,xscale-uart";
115 compatible = "intel,ixp4xx-gpio";
136 compatible = "intel,ixp4xx-timer";
142 compatible = "intel,ixp4xx-network-processing-engine";
147 compatible = "intel,ixp4xx-crypto";
148 intel,npe-handle = <&npe 2>;
156 compatible = "intel,ixp4xx-ethernet";
162 intel,npe-handle = <&npe 1>;
[all …]
Dintel-ixp43x.dtsi7 #include "intel-ixp4xx.dtsi"
12 compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
18 compatible = "intel,ixp43x-pci";
22 compatible = "intel,ixp43x-interrupt";
Dintel-ixp4xx-reference-design.dtsi62 intel,ixp4xx-eb-t1 = <0>;
63 intel,ixp4xx-eb-t2 = <0>;
64 intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
65 intel,ixp4xx-eb-t4 = <0>;
66 intel,ixp4xx-eb-t5 = <0>;
67 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
68 intel,ixp4xx-eb-byte-access-on-halfword = <0>;
69 intel,ixp4xx-eb-mux-address-and-data = <0>;
70 intel,ixp4xx-eb-ahb-split-transfers = <0>;
71 intel,ixp4xx-eb-write-enable = <1>;
[all …]
Dintel-ixp42x-welltech-epbx100.dts8 #include "intel-ixp42x.dtsi"
12 compatible = "welltech,epbx100", "intel,ixp42x";
34 compatible = "intel,ixp4xx-flash", "cfi-flash";
Dintel-ixp42x-netgear-wg302v2.dts9 #include "intel-ixp42x.dtsi"
14 compatible = "netgear,wg302v2", "intel,ixp42x";
38 compatible = "intel,ixp4xx-flash", "cfi-flash";
47 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp42x-ixdpg425.dts17 #include "intel-ixp42x.dtsi"
22 compatible = "intel,ixdpg425", "intel,ixp42x";
44 compatible = "intel,ixp4xx-flash", "cfi-flash";
53 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp42x-adi-coyote.dts10 #include "intel-ixp42x.dtsi"
15 compatible = "adieng,coyote", "intel,ixp42x";
39 compatible = "intel,ixp4xx-flash", "cfi-flash";
48 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp42x-freecom-fsg-3.dts10 #include "intel-ixp42x.dtsi"
15 compatible = "freecom,fsg-3", "intel,ixp42x";
87 compatible = "intel,ixp4xx-flash", "cfi-flash";
90 intel,ixp4xx-eb-write-enable = <1>;
Dintel-ixp42x-linksys-wrv54g.dts11 #include "intel-ixp42x.dtsi"
16 compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x";
85 compatible = "intel,ixp4xx-flash", "cfi-flash";
88 intel,ixp4xx-eb-write-enable = <1>;
/arch/x86/events/intel/
DMakefile5 obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += intel-uncore.o
6 intel-uncore-objs := uncore.o uncore_nhmex.o uncore_snb.o uncore_snbep.o uncore_discovery.o
7 obj-$(CONFIG_PERF_EVENTS_INTEL_CSTATE) += intel-cstate.o
8 intel-cstate-objs := cstate.o
/arch/x86/platform/
DMakefile8 obj-y += intel/
9 obj-y += intel-mid/
10 obj-y += intel-quark/
/arch/x86/platform/ce4100/
Dfalconfalls.dts9 model = "intel,falconfalls";
10 compatible = "intel,falconfalls";
20 compatible = "intel,ce4100";
29 compatible = "intel,ce4100-cp";
34 compatible = "intel,ce4100-ioapic";
40 compatible = "intel,ce4100-hpet";
45 compatible = "intel,ce4100-lapic";
52 compatible = "intel,ce4100-pci", "pci";
62 compatible = "intel,ce4100-ioapic";
71 compatible = "intel,ce4100-pci", "pci";
[all …]
/arch/x86/crypto/
DMakefile49 obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o
50 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o
51 aesni-intel-$(CONFIG_64BIT) += aesni-intel_avx-x86_64.o aes_ctrby8_avx-x86_64.o
67 obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
68 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
73 obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
74 crc32c-intel-y := crc32c-intel_glue.o
75 crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
/arch/arm64/boot/dts/intel/
Dkeembay-evm.dts14 compatible = "intel,keembay-evm", "intel,keembay";
/arch/x86/kvm/
DMakefile29 kvm-intel-y += vmx/vmx.o vmx/vmenter.o vmx/pmu_intel.o vmx/vmcs12.o \
31 kvm-intel-$(CONFIG_X86_SGX_KVM) += vmx/sgx.o
40 obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
/arch/x86/platform/intel-mid/
DMakefile2 obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o pwr.o
/arch/x86/kernel/cpu/microcode/
DMakefile4 microcode-$(CONFIG_MICROCODE_INTEL) += intel.o

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