| /arch/mips/kernel/ |
| D | irq-msc01.c | 24 static unsigned int irq_base; variable
31 if (irq < (irq_base + 32)) in mask_msc_irq()
32 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); in mask_msc_irq()
34 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); in mask_msc_irq()
42 if (irq < (irq_base + 32)) in unmask_msc_irq()
43 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); in unmask_msc_irq()
45 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); in unmask_msc_irq()
86 do_IRQ(irq + irq_base); in ll_msc_irq()
152 irq_base = irqbase; in init_msc_irqs()
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| /arch/arm/mach-sa1100/ |
| D | neponset.c | 80 unsigned irq_base; member
180 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); in neponset_irq_handler()
183 generic_handle_irq(d->irq_base + NEP_IRQ_USAR); in neponset_irq_handler()
189 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); in neponset_irq_handler()
307 d->irq_base = ret; in neponset_probe()
309 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, in neponset_probe()
311 irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE); in neponset_probe()
312 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip, in neponset_probe()
314 irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE); in neponset_probe()
315 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip); in neponset_probe()
[all …]
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| /arch/sh/cchips/hd6446x/ |
| D | hd64461.c | 77 int irq_base, i; in setup_hd64461() local
90 irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1); in setup_hd64461()
91 if (IS_ERR_VALUE(irq_base)) { in setup_hd64461()
93 return irq_base; in setup_hd64461()
97 irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip, in setup_hd64461()
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| /arch/arm/mach-omap1/ |
| D | irq.c | 196 int i, j, irq_base; in omap1_init_irq() local
230 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); in omap1_init_irq()
231 if (irq_base < 0) { in omap1_init_irq()
233 irq_base = 0; in omap1_init_irq()
235 omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; in omap1_init_irq()
238 domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, in omap1_init_irq()
267 omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); in omap1_init_irq()
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| /arch/mips/pci/ |
| D | pci-ar71xx.c | 51 int irq_base; member
238 generic_handle_irq(apc->irq_base + 0); in ar71xx_pci_irq_handler()
241 generic_handle_irq(apc->irq_base + 1); in ar71xx_pci_irq_handler()
244 generic_handle_irq(apc->irq_base + 2); in ar71xx_pci_irq_handler()
247 generic_handle_irq(apc->irq_base + 4); in ar71xx_pci_irq_handler()
261 irq = d->irq - apc->irq_base; in ar71xx_pci_irq_unmask()
278 irq = d->irq - apc->irq_base; in ar71xx_pci_irq_mask()
304 apc->irq_base = ATH79_PCI_IRQ_BASE; in ar71xx_pci_irq_init()
305 for (i = apc->irq_base; in ar71xx_pci_irq_init()
306 i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) { in ar71xx_pci_irq_init()
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| D | pci-ar724x.c | 45 int irq_base; member
242 generic_handle_irq(apc->irq_base + 0); in ar724x_pci_irq_handler()
257 offset = apc->irq_base - d->irq; in ar724x_pci_irq_unmask()
278 offset = apc->irq_base - d->irq; in ar724x_pci_irq_mask()
316 apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); in ar724x_pci_irq_init()
318 for (i = apc->irq_base; in ar724x_pci_irq_init()
319 i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { in ar724x_pci_irq_init()
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| /arch/arm/mach-imx/ |
| D | tzic.c | 151 int irq_base; in tzic_init_dt() local
175 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); in tzic_init_dt()
176 WARN_ON(irq_base < 0); in tzic_init_dt()
178 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, in tzic_init_dt()
182 for (i = 0; i < 4; i++, irq_base += 32) in tzic_init_dt()
183 tzic_init_gc(i, irq_base); in tzic_init_dt()
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| D | avic.c | 169 int irq_base; in mxc_init_irq() local
200 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); in mxc_init_irq()
201 WARN_ON(irq_base < 0); in mxc_init_irq()
204 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, in mxc_init_irq()
208 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) in mxc_init_irq()
209 avic_init_gc(i, irq_base); in mxc_init_irq()
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| /arch/sh/boards/mach-se/7724/ |
| D | irq.c | 114 int irq_base, i; in init_se7724_IRQ() local
124 irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE, in init_se7724_IRQ()
126 if (IS_ERR_VALUE(irq_base)) { in init_se7724_IRQ()
132 irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip, in init_se7724_IRQ()
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| /arch/arm/mach-pxa/ |
| D | irq.c | 53 static inline void __iomem *irq_base(int i) in irq_base() function
124 void __iomem *base = irq_base(hw / 32); in pxa_irq_map()
157 void __iomem *base = irq_base(n >> 5); in pxa_init_irq_common()
163 __raw_writel(1, irq_base(0) + ICCR); in pxa_init_irq_common()
186 void __iomem *base = irq_base(i); in pxa_irq_suspend()
205 void __iomem *base = irq_base(i); in pxa_irq_resume()
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| D | eseries.c | 187 .irq_base = IRQ_BOARD_START,
307 .irq_base = IRQ_BOARD_START,
497 .irq_base = IRQ_BOARD_START,
694 .irq_base = IRQ_BOARD_START,
913 .irq_base = IRQ_BOARD_START,
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| /arch/sh/boards/mach-se/7722/ |
| D | irq.c | 70 unsigned int irq_base; in se7722_gc_init() local
72 irq_base = irq_linear_revmap(se7722_irq_domain, 0); in se7722_gc_init()
74 gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs, in se7722_gc_init()
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| /arch/sh/boards/mach-dreamcast/ |
| D | irq.c | 144 int irq_base, i; in systemasic_irq_init() local
146 irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE, in systemasic_irq_init()
148 if (IS_ERR_VALUE(irq_base)) { in systemasic_irq_init()
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| /arch/sh/boards/mach-se/7343/ |
| D | irq.c | 71 unsigned int irq_base; in se7343_gc_init() local
73 irq_base = irq_linear_revmap(se7343_irq_domain, 0); in se7343_gc_init()
75 gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs, in se7343_gc_init()
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| /arch/arm/mach-ep93xx/ |
| D | vision_ep9307.c | 122 .irq_base = EP93XX_BOARD_IRQ(0),
127 .irq_base = -1,
132 .irq_base = -1,
137 .irq_base = -1,
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| /arch/arm/mach-mmp/ |
| D | jasper.c | 101 .irq_base = MMP_GPIO_TO_IRQ(0),
141 .irq_base = MMP_NR_IRQS,
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| D | ttc_dkb.c | 77 .irq_base = MMP_GPIO_TO_IRQ(0),
141 .irq_base = MMP_NR_IRQS,
146 .irq_base = IRQ_BOARD_START,
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| D | avengers_lite.c | 34 .irq_base = MMP_GPIO_TO_IRQ(0),
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| D | brownstone.c | 107 .irq_base = MMP_GPIO_TO_IRQ(0),
171 .irq_base = MMP_NR_IRQS,
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| D | teton_bga.c | 51 .irq_base = MMP_GPIO_TO_IRQ(0),
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| D | tavorevb.c | 62 .irq_base = MMP_GPIO_TO_IRQ(0),
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| D | flint.c | 79 .irq_base = MMP_GPIO_TO_IRQ(0),
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| /arch/arm/common/ |
| D | locomo.c | 64 int irq_base; member
153 irq = lchip->irq_base; in locomo_handler()
172 r &= ~(0x0010 << (d->irq - lchip->irq_base)); in locomo_mask_irq()
181 r |= (0x0010 << (d->irq - lchip->irq_base)); in locomo_unmask_irq()
194 int irq = lchip->irq_base; in locomo_setup_irq()
203 for ( ; irq <= lchip->irq_base + 3; irq++) { in locomo_setup_irq()
252 dev->irq[0] = (lchip->irq_base == NO_IRQ) ? in locomo_init_one_child()
253 NO_IRQ : lchip->irq_base + info->irq[0]; in locomo_init_one_child()
386 lchip->irq_base = (pdata) ? pdata->irq_base : NO_IRQ; in __locomo_probe()
453 if (lchip->irq != NO_IRQ && lchip->irq_base != NO_IRQ) in __locomo_probe()
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| D | sa1111.c | 104 int irq_base; /* base for cascaded on-chip IRQs */ member
376 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base) in sa1111_setup_irq() argument
386 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1); in sa1111_setup_irq()
395 sachip->irq_base = ret; in sa1111_setup_irq()
420 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR); in sa1111_setup_irq()
425 sachip->irq_base + IRQ_GPAIN0, in sa1111_setup_irq()
428 sachip->irq_base + AUDXMTDMADONEA, in sa1111_setup_irq()
440 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1); in sa1111_setup_irq()
862 ret = sa1111_setup_irq(sachip, pd->irq_base); in __sa1111_probe()
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| /arch/arm/mach-s3c/ |
| D | gpio-core.h | 72 int irq_base; member
|