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Searched refs:prio (Results 1 – 25 of 36) sorted by relevance

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/arch/powerpc/sysdev/
Dipic.c35 .prio = IPIC_SIPRR_C,
42 .prio = IPIC_SIPRR_C,
49 .prio = IPIC_SIPRR_C,
56 .prio = IPIC_SIPRR_C,
63 .prio = IPIC_SIPRR_C,
70 .prio = IPIC_SIPRR_C,
77 .prio = IPIC_SIPRR_C,
84 .prio = IPIC_SIPRR_C,
91 .prio = IPIC_SIPRR_D,
98 .prio = IPIC_SIPRR_D,
[all …]
Dehv_pic.c75 unsigned int config, prio, cpu_dest; in ehv_pic_set_affinity() local
80 ev_int_get_config(src, &config, &prio, &cpu_dest); in ehv_pic_set_affinity()
81 ev_int_set_config(src, config, prio, cpuid); in ehv_pic_set_affinity()
115 unsigned int vecpri, vold, vnew, prio, cpu_dest; in ehv_pic_set_irq_type() local
126 ev_int_get_config(src, &vold, &prio, &cpu_dest); in ehv_pic_set_irq_type()
137 prio = 8; in ehv_pic_set_irq_type()
139 ev_int_set_config(src, vecpri, prio, cpu_dest); in ehv_pic_set_irq_type()
Dipic.h49 u8 prio; /* priority register offset from base */ member
/arch/powerpc/sysdev/xive/
Dspapr.c209 unsigned long prio, in plpar_int_set_source_config() argument
216 flags, lisn, target, prio, sw_irq); in plpar_int_set_source_config()
221 target, prio, sw_irq); in plpar_int_set_source_config()
226 lisn, target, prio, rc); in plpar_int_set_source_config()
236 unsigned long *prio, in plpar_int_get_source_config() argument
246 target, prio, sw_irq); in plpar_int_get_source_config()
256 *prio = retbuf[1]; in plpar_int_get_source_config()
447 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) in xive_spapr_configure_irq() argument
452 prio, sw_irq); in xive_spapr_configure_irq()
457 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, in xive_spapr_get_irq_config() argument
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Dnative.c97 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq) in xive_native_configure_irq() argument
102 rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq); in xive_native_configure_irq()
111 static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio, in xive_native_get_irq_config() argument
118 rc = opal_xive_get_irq_config(hw_irq, &vp, prio, &lirq); in xive_native_get_irq_config()
129 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio, in xive_native_configure_queue() argument
150 rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL, in xive_native_configure_queue()
155 vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc); in xive_native_configure_queue()
172 rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags); in xive_native_configure_queue()
178 vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc); in xive_native_configure_queue()
193 static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio) in __xive_native_disable_queue() argument
[all …]
Dxive-internal.h42 int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
43 int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio,
45 int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
46 void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
Dcommon.c144 u8 prio = 0; in xive_scan_interrupts() local
150 prio = ffs(xc->pending_prio) - 1; in xive_scan_interrupts()
151 DBG_VERBOSE("scan_irq: trying prio %d\n", prio); in xive_scan_interrupts()
154 irq = xive_read_eq(&xc->queue[prio], just_peek); in xive_scan_interrupts()
172 xc->pending_prio &= ~(1 << prio); in xive_scan_interrupts()
179 q = &xc->queue[prio]; in xive_scan_interrupts()
191 prio = 0xff; in xive_scan_interrupts()
194 if (prio != xc->cppr) { in xive_scan_interrupts()
195 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio); in xive_scan_interrupts()
196 xc->cppr = prio; in xive_scan_interrupts()
[all …]
/arch/powerpc/kvm/
Dbook3s_xive_template.c114 u8 prio = 0xff; in GLUE() local
126 prio = ffs(pending) - 1; in GLUE()
129 if (prio >= xc->cppr || prio > 7) { in GLUE()
131 prio = xc->mfrr; in GLUE()
138 q = &xc->queues[prio]; in GLUE()
171 if (hirq == XICS_IPI || (prio == 0 && !qpage)) { in GLUE()
192 pending &= ~(1 << prio); in GLUE()
214 if (prio >= xc->mfrr && xc->mfrr < xc->cppr) { in GLUE()
215 prio = xc->mfrr; in GLUE()
252 xc->cppr = prio; in GLUE()
[all …]
Dbook3s_xive.c261 int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio, in kvmppc_xive_attach_escalation() argument
265 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_attach_escalation()
270 if (xc->esc_virq[prio]) in kvmppc_xive_attach_escalation()
274 xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); in kvmppc_xive_attach_escalation()
275 if (!xc->esc_virq[prio]) { in kvmppc_xive_attach_escalation()
277 prio, xc->server_num); in kvmppc_xive_attach_escalation()
286 vcpu->kvm->arch.lpid, xc->server_num, prio); in kvmppc_xive_attach_escalation()
289 prio, xc->server_num); in kvmppc_xive_attach_escalation()
294 pr_devel("Escalation %s irq %d (prio %d)\n", name, xc->esc_virq[prio], prio); in kvmppc_xive_attach_escalation()
296 rc = request_irq(xc->esc_virq[prio], xive_esc_irq, in kvmppc_xive_attach_escalation()
[all …]
Dbook3s_xive.h261 static inline u8 xive_prio_from_guest(u8 prio) in xive_prio_from_guest() argument
263 if (prio == 0xff || prio < 6) in xive_prio_from_guest()
264 return prio; in xive_prio_from_guest()
268 static inline u8 xive_prio_to_guest(u8 prio) in xive_prio_to_guest() argument
270 return prio; in xive_prio_to_guest()
305 int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
306 int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
De500_emulate.c35 int prio = -1; in dbell2prio() local
39 prio = BOOKE_IRQPRIO_DBELL; in dbell2prio()
42 prio = BOOKE_IRQPRIO_DBELL_CRIT; in dbell2prio()
48 return prio; in dbell2prio()
54 int prio = dbell2prio(param); in kvmppc_e500_emul_msgclr() local
56 if (prio < 0) in kvmppc_e500_emul_msgclr()
59 clear_bit(prio, &vcpu->arch.pending_exceptions); in kvmppc_e500_emul_msgclr()
66 int prio = dbell2prio(rb); in kvmppc_e500_emul_msgsnd() local
71 if (prio < 0) in kvmppc_e500_emul_msgsnd()
77 set_bit(prio, &cvcpu->arch.pending_exceptions); in kvmppc_e500_emul_msgsnd()
Dbook3s_xive_native.c44 static void kvmppc_xive_native_cleanup_queue(struct kvm_vcpu *vcpu, int prio) in kvmppc_xive_native_cleanup_queue() argument
47 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_native_cleanup_queue()
49 xive_native_disable_queue(xc->vp_id, q, prio); in kvmppc_xive_native_cleanup_queue()
57 u8 prio, __be32 *qpage, in kvmppc_xive_native_configure_queue() argument
63 rc = xive_native_configure_queue(vp_id, q, prio, qpage, order, in kvmppc_xive_native_configure_queue()
818 unsigned int prio; in kvmppc_xive_reset() local
825 for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) { in kvmppc_xive_reset()
828 if (prio == 7 && kvmppc_xive_has_single_escalation(xive)) in kvmppc_xive_reset()
831 if (xc->esc_virq[prio]) { in kvmppc_xive_reset()
832 free_irq(xc->esc_virq[prio], vcpu); in kvmppc_xive_reset()
[all …]
Dbook3s.c142 unsigned int prio; in kvmppc_book3s_vec2irqprio() local
145 case 0x100: prio = BOOK3S_IRQPRIO_SYSTEM_RESET; break; in kvmppc_book3s_vec2irqprio()
146 case 0x200: prio = BOOK3S_IRQPRIO_MACHINE_CHECK; break; in kvmppc_book3s_vec2irqprio()
147 case 0x300: prio = BOOK3S_IRQPRIO_DATA_STORAGE; break; in kvmppc_book3s_vec2irqprio()
148 case 0x380: prio = BOOK3S_IRQPRIO_DATA_SEGMENT; break; in kvmppc_book3s_vec2irqprio()
149 case 0x400: prio = BOOK3S_IRQPRIO_INST_STORAGE; break; in kvmppc_book3s_vec2irqprio()
150 case 0x480: prio = BOOK3S_IRQPRIO_INST_SEGMENT; break; in kvmppc_book3s_vec2irqprio()
151 case 0x500: prio = BOOK3S_IRQPRIO_EXTERNAL; break; in kvmppc_book3s_vec2irqprio()
152 case 0x600: prio = BOOK3S_IRQPRIO_ALIGNMENT; break; in kvmppc_book3s_vec2irqprio()
153 case 0x700: prio = BOOK3S_IRQPRIO_PROGRAM; break; in kvmppc_book3s_vec2irqprio()
[all …]
Dbook3s_xics.c1192 u64 val, prio; in xics_get_source() local
1205 prio = irqp->priority; in xics_get_source()
1206 if (prio == MASKED) { in xics_get_source()
1208 prio = irqp->saved_priority; in xics_get_source()
1210 val |= prio << KVM_XICS_PRIORITY_SHIFT; in xics_get_source()
1242 u8 prio; in xics_set_source() local
1260 prio = val >> KVM_XICS_PRIORITY_SHIFT; in xics_set_source()
1261 if (prio != MASKED && in xics_set_source()
1268 irqp->saved_priority = prio; in xics_set_source()
1270 prio = MASKED; in xics_set_source()
[all …]
/arch/ia64/kernel/
Dsys_ia64.c73 long prio; in ia64_getpriority() local
75 prio = sys_getpriority(which, who); in ia64_getpriority()
76 if (prio >= 0) { in ia64_getpriority()
78 prio = 20 - prio; in ia64_getpriority()
80 return prio; in ia64_getpriority()
/arch/powerpc/include/asm/
Dxive.h116 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
118 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
120 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
131 int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
138 int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
140 int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
Dcell-regs.h173 u8 prio; member
183 u64 prio; member
Dopal.h250 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
252 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
258 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
277 int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
280 int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
/arch/powerpc/platforms/cell/spufs/
Dsched.c74 #define SCALE_PRIO(x, prio) \ argument
75 max(x * (MAX_PRIO - prio) / (NICE_WIDTH / 2), MIN_SPU_TIMESLICE)
87 if (ctx->prio < NORMAL_PRIO) in spu_set_timeslice()
88 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE * 4, ctx->prio); in spu_set_timeslice()
90 ctx->time_slice = SCALE_PRIO(DEF_SPU_TIMESLICE, ctx->prio); in spu_set_timeslice()
117 if (rt_prio(current->prio)) in __spu_update_sched_info()
118 ctx->prio = current->prio; in __spu_update_sched_info()
120 ctx->prio = current->static_prio; in __spu_update_sched_info()
492 list_add_tail(&ctx->rq, &spu_prio->runq[ctx->prio]); in __spu_add_to_rq()
493 set_bit(ctx->prio, spu_prio->bitmap); in __spu_add_to_rq()
[all …]
/arch/arc/kernel/
Dintc-arcv2.c17 unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8; member
19 unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
67 irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */ in arc_init_IRQ()
Dentry-arcv2.S74 # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
89 ; so a higher prio interrupt taken here won't clobber prev prio icause
/arch/powerpc/platforms/cell/
Dinterrupt.c57 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4); in iic_pending_to_hwnum()
73 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); in iic_eoi()
143 iic->eoi_stack[++iic->eoi_ptr] = pending.prio; in iic_get_irq()
150 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff); in iic_setup_cpu()
287 out_be64(&iic->regs->prio, 0); in init_one_iic()
/arch/x86/kernel/
Ditmt.c189 void sched_set_itmt_core_prio(int prio, int core_cpu) in sched_set_itmt_core_prio() argument
201 smt_prio = prio * smp_num_siblings / i; in sched_set_itmt_core_prio()
/arch/x86/include/asm/
Dtopology.h173 void sched_set_itmt_core_prio(int prio, int core_cpu);
184 static inline void sched_set_itmt_core_prio(int prio, int core_cpu) in sched_set_itmt_core_prio() argument
/arch/arm/mach-pxa/
Ddevices.h3 .prio = PXAD_PRIO_##_prio, .drcmr = _requestor })

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