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/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
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/arch/mips/mm/
Dc-octeon.c179 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
183 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
187 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
189 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
192 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
199 c->icache.sets = 8; in probe_octeon()
202 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
206 c->dcache.sets = 8; in probe_octeon()
207 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
213 c->icache.sets = 16; in probe_octeon()
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Dsc-mips.c153 unsigned long sets, line_sz, assoc; in mips_sc_probe_cm3() local
158 sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE; in mips_sc_probe_cm3()
159 sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE); in mips_sc_probe_cm3()
160 if (sets) in mips_sc_probe_cm3()
161 c->scache.sets = 64 << sets; in mips_sc_probe_cm3()
171 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe_cm3()
214 c->scache.sets = 64 << tmp; in mips_sc_probe()
241 c->scache.sets = 256; in mips_sc_probe()
247 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe()
Dc-r4k.c1284 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_pcache()
1286 icache_size = c->icache.sets * in probe_pcache()
1296 c->dcache.sets = 64 << ((config1 >> 13) & 7); in probe_pcache()
1298 dcache_size = c->dcache.sets * in probe_pcache()
1311 c->icache.sets = 16; in probe_pcache()
1314 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_pcache()
1318 c->dcache.sets = 8; in probe_pcache()
1319 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_pcache()
1341 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); in probe_pcache()
1344 icache_size = c->icache.sets * in probe_pcache()
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/arch/riscv/kernel/
Dcacheinfo.c69 unsigned int sets, unsigned int line_size) in ci_leaf_init() argument
74 this_leaf->number_of_sets = sets; in ci_leaf_init()
81 if (sets == 1) in ci_leaf_init()
88 if (sets > 0 && size > 0 && line_size > 0) in ci_leaf_init()
89 this_leaf->ways_of_associativity = (size / sets) / line_size; in ci_leaf_init()
95 unsigned int size, sets, line_size; in fill_cacheinfo() local
99 !of_property_read_u32(node, "cache-sets", &sets)) { in fill_cacheinfo()
100 ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); in fill_cacheinfo()
104 !of_property_read_u32(node, "i-cache-sets", &sets) && in fill_cacheinfo()
106 ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); in fill_cacheinfo()
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/arch/arm64/boot/dts/marvell/
Darmada-ap806-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
90 cache-sets = <512>;
Darmada-ap807-quad.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
57 i-cache-sets = <256>;
60 d-cache-sets = <256>;
72 i-cache-sets = <256>;
75 d-cache-sets = <256>;
83 cache-sets = <512>;
90 cache-sets = <512>;
Darmada-ap806-dual.dtsi27 i-cache-sets = <256>;
30 d-cache-sets = <256>;
42 i-cache-sets = <256>;
45 d-cache-sets = <256>;
53 cache-sets = <512>;
/arch/arm64/boot/dts/ti/
Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
98 cache-sets = <512>;
107 cache-sets = <512>;
Dk3-am642.dtsi36 i-cache-sets = <256>;
39 d-cache-sets = <128>;
50 i-cache-sets = <256>;
53 d-cache-sets = <128>;
63 cache-sets = <256>;
/arch/riscv/boot/dts/microchip/
Dmicrochip-mpfs.dtsi21 i-cache-sets = <128>;
38 d-cache-sets = <64>;
40 d-tlb-sets = <1>;
44 i-cache-sets = <64>;
46 i-tlb-sets = <1>;
65 d-cache-sets = <64>;
67 d-tlb-sets = <1>;
71 i-cache-sets = <64>;
73 i-tlb-sets = <1>;
92 d-cache-sets = <64>;
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/arch/arm64/boot/dts/arm/
Djuno.dts93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
111 i-cache-sets = <256>;
114 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
147 i-cache-sets = <256>;
150 d-cache-sets = <128>;
165 i-cache-sets = <256>;
168 d-cache-sets = <128>;
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Djuno-r1.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
111 i-cache-sets = <256>;
114 d-cache-sets = <256>;
128 i-cache-sets = <256>;
131 d-cache-sets = <128>;
145 i-cache-sets = <256>;
148 d-cache-sets = <128>;
162 i-cache-sets = <256>;
165 d-cache-sets = <128>;
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Djuno-r2.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
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/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi29 i-cache-sets = <128>;
43 d-cache-sets = <64>;
45 d-tlb-sets = <1>;
49 i-cache-sets = <64>;
51 i-tlb-sets = <1>;
67 d-cache-sets = <64>;
69 d-tlb-sets = <1>;
73 i-cache-sets = <64>;
75 i-tlb-sets = <1>;
91 d-cache-sets = <64>;
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Dfu740-c000.dtsi29 i-cache-sets = <128>;
44 d-cache-sets = <64>;
46 d-tlb-sets = <1>;
50 i-cache-sets = <128>;
52 i-tlb-sets = <1>;
68 d-cache-sets = <64>;
70 d-tlb-sets = <1>;
74 i-cache-sets = <128>;
76 i-tlb-sets = <1>;
92 d-cache-sets = <64>;
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/arch/arm/boot/dts/
Dbcm2837.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
73 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
76 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
88 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
91 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
103 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
106 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
110 /* Source for cache-line-size + cache-sets
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/arch/sh/kernel/cpu/sh4/
Dprobe.c37 boot_cpu_data.icache.sets = 256; in cpu_probe()
46 boot_cpu_data.dcache.sets = 512; in cpu_probe()
205 boot_cpu_data.icache.sets = (size >> 6); in cpu_probe()
213 boot_cpu_data.dcache.sets = (size >> 6); in cpu_probe()
251 boot_cpu_data.scache.sets = size / in cpu_probe()
256 (boot_cpu_data.scache.sets * in cpu_probe()
/arch/powerpc/kernel/
Dsetup_64.c503 u32 bsize, u32 sets) in init_cache_info() argument
506 info->sets = sets; in init_cache_info()
515 if (sets == 0) in init_cache_info()
518 info->assoc = size / (sets * lsize); in init_cache_info()
539 u32 size, lsize, bsize, sets; in parse_cache_info() local
543 sets = -1u; in parse_cache_info()
550 sets = be32_to_cpu(*setsp); in parse_cache_info()
570 if (sets == 1) in parse_cache_info()
571 sets = 0; in parse_cache_info()
572 else if (sets == 0) in parse_cache_info()
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/arch/powerpc/boot/dts/
Dmicrowatt.dts68 i-cache-sets = <2>;
73 i-tlb-sets = <1>;
77 d-cache-sets = <2>;
84 tlb-sets = <0>;
87 d-tlb-sets = <2>;
/arch/sh/kernel/cpu/sh3/
Dprobe.c62 boot_cpu_data.dcache.sets = 128; in cpu_probe()
69 boot_cpu_data.dcache.sets = 256; in cpu_probe()
93 boot_cpu_data.dcache.sets = 512; in cpu_probe()
/arch/sparc/mm/
Dleon_mm.c247 unsigned int ssize, sets; in leon_flush_needed() local
255 sets = (cregs.dccr & LEON3_XCCR_SETS_MASK) >> 24; in leon_flush_needed()
260 sets > 3 ? "unknown" : setStr[sets], ssize); in leon_flush_needed()
261 if ((ssize <= (PAGE_SIZE / 1024)) && (sets == 0)) { in leon_flush_needed()
/arch/nds32/kernel/
Dsetup.c106 L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); in dump_cpu_info()
109 L1_cache_info[ICACHE].sets / 1024; in dump_cpu_info()
111 L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, in dump_cpu_info()
115 L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE); in dump_cpu_info()
118 L1_cache_info[DCACHE].sets / 1024; in dump_cpu_info()
120 L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways, in dump_cpu_info()
/arch/sh/kernel/cpu/sh2/
Dprobe.c36 boot_cpu_data.dcache.sets = 256; in cpu_probe()
57 boot_cpu_data.dcache.sets = 256; in cpu_probe()
/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a.dtsi37 d-cache-sets = <128>;
40 i-cache-sets = <192>;
54 d-cache-sets = <128>;
57 i-cache-sets = <192>;
71 d-cache-sets = <128>;
74 i-cache-sets = <192>;
88 d-cache-sets = <128>;
91 i-cache-sets = <192>;
105 d-cache-sets = <128>;
108 i-cache-sets = <192>;
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