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/arch/mips/include/asm/octeon/
Dcvmx-fau.h62 int64_t value:63; member
72 int32_t value:31; member
82 int16_t value:15; member
92 int8_t value:7; member
153 int64_t value) in __cvmx_fau_atomic_address() argument
156 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | in __cvmx_fau_atomic_address()
171 int64_t value) in cvmx_fau_fetch_and_add64() argument
173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64()
186 int32_t value) in cvmx_fau_fetch_and_add32() argument
189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32()
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/arch/mips/include/asm/
Dunaligned-emul.h8 #define _LoadHW(addr, value, res, type) \ argument
26 : "=&r" (value), "=r" (res) \
31 #define _LoadW(addr, value, res, type) \ argument
47 : "=&r" (value), "=r" (res) \
53 #define _LoadW(addr, value, res, type) \ argument
82 : "=&r" (value), "=r" (res) \
88 #define _LoadHWU(addr, value, res, type) \ argument
108 : "=&r" (value), "=r" (res) \
113 #define _LoadWU(addr, value, res, type) \ argument
131 : "=&r" (value), "=r" (res) \
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/arch/mips/cavium-octeon/crypto/
Docteon-crypto.h31 #define write_octeon_64bit_hash_dword(value, index) \ argument
36 : [rt] "d" (cpu_to_be64(value))); \
57 #define write_octeon_64bit_block_dword(value, index) \ argument
62 : [rt] "d" (cpu_to_be64(value))); \
68 #define octeon_md5_start(value) \ argument
73 : [rt] "d" (cpu_to_be64(value))); \
79 #define octeon_sha1_start(value) \ argument
84 : [rt] "d" (value)); \
90 #define octeon_sha256_start(value) \ argument
95 : [rt] "d" (value)); \
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/arch/xtensa/kernel/
Dmodule.c57 uint32_t value; in apply_relocate_add() local
67 value = sym->st_value + rela[i].r_addend; in apply_relocate_add()
79 *(uint32_t *)location += value; in apply_relocate_add()
84 value -= ((unsigned long)location & -4) + 4; in apply_relocate_add()
85 if ((value & 3) != 0 || in apply_relocate_add()
86 ((value + (1 << 19)) >> 20) != 0) { in apply_relocate_add()
94 value = (signed int)value >> 2; in apply_relocate_add()
97 ((value >> 16) & 0x3)); in apply_relocate_add()
98 location[1] = (value >> 8) & 0xff; in apply_relocate_add()
99 location[2] = value & 0xff; in apply_relocate_add()
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/arch/alpha/kernel/
Dmodule.c156 unsigned long value, hi, lo; in apply_relocate_add() local
165 value = sym->st_value + rela[i].r_addend; in apply_relocate_add()
171 *(u32 *)location = value; in apply_relocate_add()
175 ((u32 *)location)[0] = value; in apply_relocate_add()
176 ((u32 *)location)[1] = value >> 32; in apply_relocate_add()
179 value -= gp; in apply_relocate_add()
180 if ((int)value != value) in apply_relocate_add()
182 *(u32 *)location = value; in apply_relocate_add()
190 *(u64 *)hi = value; in apply_relocate_add()
195 value = gp - (u64)location; in apply_relocate_add()
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/arch/x86/pci/
Dce4100.c25 u32 value; member
33 void (*read)(struct sim_dev_reg *reg, u32 *value);
34 void (*write)(struct sim_dev_reg *reg, u32 value);
40 void (*read)(struct sim_dev_reg *reg, u32 value);
41 void (*write)(struct sim_dev_reg *reg, u32 value);
58 &reg->sim_reg.value); in reg_init()
61 static void reg_read(struct sim_dev_reg *reg, u32 *value) in reg_read() argument
63 *value = reg->sim_reg.value; in reg_read()
66 static void reg_write(struct sim_dev_reg *reg, u32 value) in reg_write() argument
68 reg->sim_reg.value = (value & reg->sim_reg.mask) | in reg_write()
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Ddirect.c22 unsigned int devfn, int reg, int len, u32 *value) in pci_conf1_read() argument
27 *value = -1; in pci_conf1_read()
37 *value = inb(0xCFC + (reg & 3)); in pci_conf1_read()
40 *value = inw(0xCFC + (reg & 2)); in pci_conf1_read()
43 *value = inl(0xCFC); in pci_conf1_read()
53 unsigned int devfn, int reg, int len, u32 value) in pci_conf1_write() argument
66 outb((u8)value, 0xCFC + (reg & 3)); in pci_conf1_write()
69 outw((u16)value, 0xCFC + (reg & 2)); in pci_conf1_write()
72 outl((u32)value, 0xCFC); in pci_conf1_write()
96 unsigned int devfn, int reg, int len, u32 *value) in pci_conf2_read() argument
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/arch/sh/boards/
Dboard-apsh4ad0a.c73 int value = 0; in apsh4ad0a_mode_pins() local
79 value |= MODE_PIN0; /* Clock Mode 3 */ in apsh4ad0a_mode_pins()
80 value |= MODE_PIN1; in apsh4ad0a_mode_pins()
81 value &= ~MODE_PIN2; in apsh4ad0a_mode_pins()
82 value &= ~MODE_PIN3; in apsh4ad0a_mode_pins()
83 value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ in apsh4ad0a_mode_pins()
84 value |= MODE_PIN5; in apsh4ad0a_mode_pins()
85 value |= MODE_PIN6; in apsh4ad0a_mode_pins()
86 value |= MODE_PIN7; /* Normal mode */ in apsh4ad0a_mode_pins()
87 value |= MODE_PIN8; /* Little Endian */ in apsh4ad0a_mode_pins()
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Dboard-apsh4a3a.c148 int value = 0; in apsh4a3a_mode_pins() local
154 value &= ~MODE_PIN0; /* Clock Mode 16 */ in apsh4a3a_mode_pins()
155 value &= ~MODE_PIN1; in apsh4a3a_mode_pins()
156 value &= ~MODE_PIN2; in apsh4a3a_mode_pins()
157 value &= ~MODE_PIN3; in apsh4a3a_mode_pins()
158 value |= MODE_PIN4; in apsh4a3a_mode_pins()
159 value &= ~MODE_PIN5; /* 16-bit Area0 bus width */ in apsh4a3a_mode_pins()
160 value |= MODE_PIN6; /* Area 0 SRAM interface */ in apsh4a3a_mode_pins()
161 value |= MODE_PIN7; in apsh4a3a_mode_pins()
162 value |= MODE_PIN8; /* Little Endian */ in apsh4a3a_mode_pins()
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/arch/microblaze/lib/
Dmemcpy.c63 unsigned value, buf_hold; in memcpy() local
102 value = *i_src++; in memcpy()
103 *i_dst++ = buf_hold | value >> 24; in memcpy()
104 buf_hold = value << 8; in memcpy()
111 value = *i_src++; in memcpy()
112 *i_dst++ = buf_hold | ((value & 0xFF) << 24); in memcpy()
113 buf_hold = (value & 0xFFFFFF00) >> 8; in memcpy()
128 value = *i_src++; in memcpy()
129 *i_dst++ = buf_hold | value >> 16; in memcpy()
130 buf_hold = value << 16; in memcpy()
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Dmemmove.c84 unsigned value, buf_hold; in memmove() local
124 value = *--i_src; in memmove()
125 *--i_dst = buf_hold << 8 | value; in memmove()
126 buf_hold = value >> 24; in memmove()
133 value = *--i_src; in memmove()
135 ((value & 0xFFFFFF00) >> 8); in memmove()
136 buf_hold = (value & 0xFF) << 24; in memmove()
151 value = *--i_src; in memmove()
152 *--i_dst = buf_hold << 16 | value; in memmove()
153 buf_hold = value >> 16; in memmove()
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/arch/mips/kernel/
Dunaligned.c114 unsigned long origpc, orig31, value; in emulate_load_store_insn() local
169 LoadW(addr, value, res); in emulate_load_store_insn()
173 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
178 LoadHW(addr, value, res); in emulate_load_store_insn()
182 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
199 LoadHWE(addr, value, res); in emulate_load_store_insn()
203 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
208 LoadWE(addr, value, res); in emulate_load_store_insn()
212 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
217 LoadHWUE(addr, value, res); in emulate_load_store_insn()
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/arch/csky/abiv1/inc/abi/
Dckmmu.h12 static inline void write_mmu_index(int value) in write_mmu_index() argument
14 cpwcr("cpcr0", value); in write_mmu_index()
27 static inline void write_mmu_pagemask(int value) in write_mmu_pagemask() argument
29 cpwcr("cpcr6", value); in write_mmu_pagemask()
37 static inline void write_mmu_entryhi(int value) in write_mmu_entryhi() argument
39 cpwcr("cpcr4", value); in write_mmu_entryhi()
47 static inline void write_mmu_msa0(unsigned long value) in write_mmu_msa0() argument
49 cpwcr("cpcr30", value); in write_mmu_msa0()
57 static inline void write_mmu_msa1(unsigned long value) in write_mmu_msa1() argument
59 cpwcr("cpcr31", value); in write_mmu_msa1()
/arch/csky/abiv2/inc/abi/
Dckmmu.h14 static inline void write_mmu_index(int value) in write_mmu_index() argument
16 mtcr("cr<0, 15>", value); in write_mmu_index()
29 static inline void write_mmu_pagemask(int value) in write_mmu_pagemask() argument
31 mtcr("cr<6, 15>", value); in write_mmu_pagemask()
39 static inline void write_mmu_entryhi(int value) in write_mmu_entryhi() argument
41 mtcr("cr<4, 15>", value); in write_mmu_entryhi()
49 static inline void write_mmu_msa0(unsigned long value) in write_mmu_msa0() argument
51 mtcr("cr<30, 15>", value); in write_mmu_msa0()
59 static inline void write_mmu_msa1(unsigned long value) in write_mmu_msa1() argument
61 mtcr("cr<31, 15>", value); in write_mmu_msa1()
/arch/mips/loongson64/
Dcop2-ex.c32 unsigned long ra, value, value_next; in loongson_cu2_call() local
74 LoadDW(addr, value, res); in loongson_cu2_call()
82 regs->regs[insn.loongson3_lswc2_format.rt] = value; in loongson_cu2_call()
90 LoadDW(addr, value, res); in loongson_cu2_call()
98 set_fpr64(&current->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0, value); in loongson_cu2_call()
119 value = regs->regs[insn.loongson3_lswc2_format.rt]; in loongson_cu2_call()
121 StoreDW(addr, value, res); in loongson_cu2_call()
137 value = get_fpr64(&current->thread.fpu.fpr[insn.loongson3_lswc2_format.rt], 0); in loongson_cu2_call()
139 StoreDW(addr, value, res); in loongson_cu2_call()
163 LoadHW(addr, value, res); in loongson_cu2_call()
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/arch/powerpc/xmon/
Dppc-dis.c29 long value; in operand_value_powerpc() local
33 value = (*operand->extract) (insn, dialect, &invalid); in operand_value_powerpc()
37 value = (insn >> operand->shift) & operand->bitm; in operand_value_powerpc()
39 value = (insn << -operand->shift) & operand->bitm; in operand_value_powerpc()
49 value = (value ^ top) - top; in operand_value_powerpc()
53 return value; in operand_value_powerpc()
184 long value; in print_insn_powerpc() local
205 value = operand_value_powerpc (operand, insn, dialect); in print_insn_powerpc()
215 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) in print_insn_powerpc()
216 printf("r%ld", value); in print_insn_powerpc()
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/arch/x86/include/asm/
Dsegment.h304 #define __loadsegment_simple(seg, value) \ argument
306 unsigned short __val = (value); \
321 #define __loadsegment_ss(value) __loadsegment_simple(ss, (value)) argument
322 #define __loadsegment_ds(value) __loadsegment_simple(ds, (value)) argument
323 #define __loadsegment_es(value) __loadsegment_simple(es, (value)) argument
331 #define __loadsegment_fs(value) __loadsegment_simple(fs, (value)) argument
332 #define __loadsegment_gs(value) __loadsegment_simple(gs, (value)) argument
336 static inline void __loadsegment_fs(unsigned short value) in __loadsegment_fs() argument
344 : : "rm" (value) : "memory"); in __loadsegment_fs()
351 #define loadsegment(seg, value) __loadsegment_ ## seg (value) argument
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Ddebugreg.h17 #define set_debugreg(value, register) \ argument
18 native_set_debugreg(register, value)
63 static __always_inline void native_set_debugreg(int regno, unsigned long value) in native_set_debugreg() argument
67 asm("mov %0, %%db0" ::"r" (value)); in native_set_debugreg()
70 asm("mov %0, %%db1" ::"r" (value)); in native_set_debugreg()
73 asm("mov %0, %%db2" ::"r" (value)); in native_set_debugreg()
76 asm("mov %0, %%db3" ::"r" (value)); in native_set_debugreg()
79 asm("mov %0, %%db6" ::"r" (value)); in native_set_debugreg()
91 asm volatile("mov %0, %%db7" ::"r" (value), __FORCE_ORDER); in native_set_debugreg()
/arch/openrisc/kernel/
Dmodule.c26 uint32_t value; in apply_relocate_add() local
39 value = sym->st_value + rel[i].r_addend; in apply_relocate_add()
43 *location = value; in apply_relocate_add()
46 *((uint16_t *)location + 1) = value; in apply_relocate_add()
49 *((uint16_t *)location + 1) = value >> 16; in apply_relocate_add()
52 value -= (uint32_t)location; in apply_relocate_add()
53 value >>= 2; in apply_relocate_add()
54 value &= 0x03ffffff; in apply_relocate_add()
55 value |= *location & 0xfc000000; in apply_relocate_add()
56 *location = value; in apply_relocate_add()
/arch/mips/loongson2ef/common/cs5536/
Dcs5536_isa.c84 void pci_isa_write_bar(int n, u32 value) in pci_isa_write_bar() argument
86 u32 hi = 0, lo = value; in pci_isa_write_bar()
88 if (value == PCI_BAR_RANGE_MASK) { in pci_isa_write_bar()
92 } else if (value & 0x01) { in pci_isa_write_bar()
99 hi = ((value & 0x000ffffc) << 12) | in pci_isa_write_bar()
101 lo = ((value & 0x000ffffc) << 12) | 0x01; in pci_isa_write_bar()
134 void pci_isa_write_reg(int reg, u32 value) in pci_isa_write_reg() argument
136 u32 hi = 0, lo = value; in pci_isa_write_reg()
141 if (value & PCI_COMMAND_IO) in pci_isa_write_reg()
149 if ((value & PCI_STATUS_SIG_TARGET_ABORT) && in pci_isa_write_reg()
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Dcs5536_ide.c15 void pci_ide_write_reg(int reg, u32 value) in pci_ide_write_reg() argument
17 u32 hi = 0, lo = value; in pci_ide_write_reg()
22 if (value & PCI_COMMAND_MASTER) in pci_ide_write_reg()
29 if (value & PCI_STATUS_PARITY) { in pci_ide_write_reg()
38 value &= 0x0000ff00; in pci_ide_write_reg()
41 hi |= (value >> 8); in pci_ide_write_reg()
45 if (value == PCI_BAR_RANGE_MASK) { in pci_ide_write_reg()
49 } else if (value & 0x01) { in pci_ide_write_reg()
51 lo = (value & 0xfffffff0) | 0x1; in pci_ide_write_reg()
54 value &= 0xfffffffc; in pci_ide_write_reg()
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/arch/parisc/math-emu/
Dfloat.h74 #define Deposit_ssign(object,value) Bitfield_deposit(value,0,1,object) argument
75 #define Deposit_sexponent(object,value) Bitfield_deposit(value,1,8,object) argument
76 #define Deposit_smantissa(object,value) Bitfield_deposit(value,9,23,object) argument
77 #define Deposit_shigh2mantissa(object,value) Bitfield_deposit(value,9,2,object) argument
78 #define Deposit_sexponentmantissa(object,value) \ argument
79 Bitfield_deposit(value,1,31,object)
80 #define Deposit_ssignexponent(object,value) Bitfield_deposit(value,0,9,object) argument
81 #define Deposit_slow(object,value) Bitfield_deposit(value,31,1,object) argument
82 #define Deposit_shigh4(object,value) Bitfield_deposit(value,0,4,object) argument
127 #define Deposit_dsign(object,value) Bitfield_deposit(value,0,1,object) argument
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/arch/powerpc/kernel/
Dmodule_64.c536 unsigned long value; in apply_relocate_add() local
565 value = sym->st_value + rela[i].r_addend; in apply_relocate_add()
570 *(u32 *)location = value; in apply_relocate_add()
575 *(unsigned long *)location = value; in apply_relocate_add()
584 value -= my_r2(sechdrs, me); in apply_relocate_add()
585 if (value + 0x8000 > 0xffff) { in apply_relocate_add()
587 me->name, value); in apply_relocate_add()
592 | (value & 0xffff); in apply_relocate_add()
597 value -= my_r2(sechdrs, me); in apply_relocate_add()
600 | (value & 0xffff); in apply_relocate_add()
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/arch/m68k/include/asm/
Dmovs.h39 #define SET_CONTROL_BYTE(addr,value) \ argument
40 __asm__ __volatile__ (" movsb %0, %1@" : : "d" (value), "a" (addr));
44 #define GET_CONTROL_BYTE(addr,value) \ argument
45 __asm__ __volatile__ (" movsb %1@, %0" : "=d" (value) : "a" (addr));
49 #define SET_CONTROL_WORD(addr,value) \ argument
50 __asm__ __volatile__ (" movsl %0, %1@" : : "d" (value), "a" (addr));
54 #define GET_CONTROL_WORD(addr,value) \ argument
55 __asm__ __volatile__ (" movsl %1@, %0" : "=d" (value) : "a" (addr));
/arch/mips/ar7/
Dprom.c25 char *value; member
36 return adam2_env[i].value; in prom_getenv()
73 char *value; member
124 return psp_var_map[i].value; in lookup_psp_var_map()
129 static void __init add_adam2_var(char *name, char *value) in add_adam2_var() argument
136 adam2_env[i].value = value; in add_adam2_var()
139 adam2_env[i].value = value; in add_adam2_var()
148 char *name, *value; in parse_psp_env() local
158 value = chunks[i].data; in parse_psp_env()
162 name = value; in parse_psp_env()
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